CN104300968A - Clock pulse and data reply device, sampler and sampling method - Google Patents
Clock pulse and data reply device, sampler and sampling method Download PDFInfo
- Publication number
- CN104300968A CN104300968A CN201310303312.5A CN201310303312A CN104300968A CN 104300968 A CN104300968 A CN 104300968A CN 201310303312 A CN201310303312 A CN 201310303312A CN 104300968 A CN104300968 A CN 104300968A
- Authority
- CN
- China
- Prior art keywords
- phase
- data
- clock pulse
- edge
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
The invention discloses a clock pulse and data reply device, a sampler and a sampling method. The sampler comprises a phase generation circuit and a first edge sampling circuit electrically connected with the phase generation circuit, wherein the phase generation circuit is used for generating multiple first phases, the multiple first phases have different phase values, the first edge sampling circuit is used for sampling multiple first edge values of multiple bits of a data signal according to the multiple first phases, so a clock pulse of the data signal can be determined by the clock pulse and data reply device according to the first edge values.
Description
Technical field
The present invention about a kind of clock pulse and return apparatus, sampler and sampling method thereof, the clock pulse particularly sampled about a kind of edge and return apparatus, sampler and sampling method thereof.
Background technology
In recent years, due to the fast development of technology, the service speed of integrated circuit also has breakthrough thereupon.So, in response to people for the demand of high-speed transfer and serious hope, industry gradually adopts high speed serialization formula transmission system to replace the block form transmission system of the low data transmission rate of tool, wherein high speed serialization formula transmission system is also known as serializer-deserializerSERDES (Serializer-Deserializer, SERDES), its feature is passed through in high speed differential to line transmitting serialized data, but not transmits in low-speed parallel bus.
Generally speaking, because the data transmission rate of high speed serialization formula transmission system is high, the signal received by receiving terminal is made to be generally asynchronous data.In addition, be limited to the non-ideal effects that noise disturbs and passage causes, such as: reflection, diffraction, transmission, symbol intersymbol interference (Inter Symbol Interference, ISI), cross-talk ... etc. problem, receiving terminal must be more accurate for the synchronous process of data, just can effectively the data that transmitting terminal transmits be reduced.
The receiving terminal of high speed serialization formula transmission system adopts source of synchronising signal (Source Synchronous usually, SS) interface or clock pulse and data recovery (Clock Data Recovery, CDR) interface solves the problem of data syn-chronization, and its difference is that the method realizing clock pulse is separately different.Source of synchronising signal interface adopts a clock signal separated separately, along with transfer of data; Clock pulse and data recovery interface then do not have independent clock signal, but adopt embedded sequential (Embedded Clock) in the transmission means of data flow.Relative to source of synchronising signal interface, although clock pulse and data recovery interface have larger design challenge, it has more following advantage: improve the problems such as crooked (Skew) that in fact clock pulse causes and cross-talk (Crosstalk); Save passage cost; Promote the speed of service; And increase transmission range etc.
Generally speaking, the design challenges of clock pulse and data recovery interface is to shake (Jitter).The signal displacement to each other that shake and real data and ideally expecting occurs, it easily destroys the synchronous accuracy of the signal of receiving terminal, especially operates on the clock pulse of receiving terminal and data recovery circuit interface the impact caused very large.Shake can generally be divided into quantitative shake and Random jitter, and wherein quantitative shake comprises interference, cross-talk, work period distortion and periodic jitter etc. between character, and Random jitter is generally the byproduct caused by semiconductor heat effect.
The sampling accuracy rate improving sampler is overcome the effective means that clock pulse and data recovery circuit interface are subject to effect of jitter.Generally speaking, clock pulse and data recovery circuit interface all need one in order to sample the sampler of Received signal strength.Ideally, when sampler can sample out required data exactly in Received signal strength, then mean that the shake tolerance (Jitter Tolerance) of clock pulse and data recovery circuit interface can be higher, wherein said shake tolerance, at receiving terminal usually with unit gap (Unit Interval, UI) represent, and larger unit gap means that receiver can tolerate more shake.
For traditional clock pulse and data recovery circuit interface, a kind of method of promoting sampling accuracy rate is sample according to multiple edges of a stationary phase to multiple bits of data-signal, and the marginal position of multiple bits of this data-signal is estimated according to the result of sampling, thus judge the clock pulse that this data-signal is embedded, use and sample out required data in Received signal strength.But said method is limited to fixing sampling point (corresponding to stationary phase), therefore for the speed of marginal position of multiple bits of this data-signal of estimation and accuracy, still has and sizablely improve space.
In sum, before realizing high speed serialization formula transmission system, shaking the impact caused for clock pulse and data recovery circuit interface certainly will overcome in advance.In view of this, how promoting the sampling accuracy rate of sampler, use the shake tolerance promoting clock pulse and data recovery interface, is the target that industry still needs to make great efforts in fact.
Summary of the invention
The object of the present invention is to provide a kind of sampler, for a clock pulse and data recovery (clock and data recovery) device.This sampler comprises the first edge sample circuit that a phase generating circuit and is electrically connected to this phase generating circuit.This phase generating circuit is in order to produce multiple first phase, and wherein these first phase have different phase number.This first edge sample circuit, in order to sample multiple first edge value of multiple bits of a data-signal according to these first phase, judges a clock pulse of this data-signal with this clock pulse and return apparatus according to the plurality of first edge value.
The present invention more provides a kind of clock pulse and return apparatus.This clock pulse and return apparatus comprise a sampler and a treatment circuit.This sampler comprises the first edge sample circuit that a phase generating circuit and is electrically connected to this phase generating circuit.This phase generating circuit is in order to produce multiple first phase, and wherein these first phase have different phase number.This first edge sample circuit is in order to sample multiple first edge value of multiple bits of a data-signal according to these first phase.This treatment circuit, in order to judge a clock pulse of this data-signal according to these first edge value.
The present invention also provides a kind of sampling method, for a clock pulse and return apparatus.This clock pulse and return apparatus comprise a sampler and a treatment circuit, and this sampler comprises the first edge sample circuit that a phase generating circuit and is electrically connected to this phase generating circuit.This sampling method comprises the following step:
A () makes this phase generating circuit produce multiple first phase, wherein these first phase have different phase number;
B () makes this first edge sample circuit sample multiple first edge value of multiple bits of a data-signal according to these first phase; And
C () makes this treatment circuit judge a clock pulse of this data-signal according to these first edge value.
In sum, the invention provides a kind of clock pulse and return apparatus, sampler and sampling method thereof.Be different from traditional clock pulse and data recovery circuit interface, clock pulse provided by the invention and return apparatus, sampler and sampling method thereof produce multiple out of phase by phasescan, and according to the phase place of these out of phase numerical value, the edge of multiple bits of data-signal is sampled respectively.
Sampled by described phasescan mode, sampling point will be no longer fixing, the edge value sampled for multiple edges of multiple bits of data-signal can contain wider scope, therefore the marginal position of the multiple bits data-signal can be estimated more quickly and more accurately, thus judge the correct clock pulse that this data-signal is embedded.Accordingly, clock pulse provided by the invention and return apparatus, sampler and sampling method thereof improve the accuracy rate of sampling effectively, the related shake tolerance adding receiving terminal.
After consulting execution mode that is graphic and that describe subsequently, art technical staff technical staff can more understand technological means of the present invention and embodiment.
Accompanying drawing explanation
The schematic diagram that Figure 1A is a kind of clock pulse described in the first embodiment of the present invention and return apparatus;
Figure 1B carries out the schematic diagram of sample of signal for a kind of clock pulse described in the first embodiment of the present invention and return apparatus;
The schematic diagram that Fig. 2 A is a kind of clock pulse described in the second embodiment of the present invention and return apparatus;
Fig. 2 B carries out the schematic diagram of sample of signal for a kind of clock pulse described in the second embodiment of the present invention and return apparatus;
The schematic diagram that Fig. 3 A is a kind of clock pulse described in the third embodiment of the present invention and return apparatus;
Fig. 3 B carries out the schematic diagram of sample of signal for a kind of clock pulse described in the third embodiment of the present invention and return apparatus;
The schematic diagram that Fig. 4 A is a kind of clock pulse described in the fourth embodiment of the present invention and return apparatus;
Fig. 4 B carries out the schematic diagram of sample of signal for a kind of clock pulse described in the fourth embodiment of the present invention and return apparatus; And
Fig. 5 is the flow chart of a kind of sampling method described in the fifth embodiment of the present invention.
Wherein, description of reference numerals is as follows:
1: clock pulse and return apparatus
11: sampler
111: phase generating circuit
113: the first edge sample circuits
115: the second edge sample circuits
117: sampling core circuit
13: treatment circuit
20: first phase
201: first phase
202: first phase
203: first phase
204: first phase
205: first phase
22: second phase
24: third phase
3: clock pulse and return apparatus
31: sampler
33: treatment circuit
40: data-signal
401: the first bits
402: second bit
403: the three bits
404: the nibbles
405: the five bits
42: the first edge value
44: the second edge value
46: center value
5: clock pulse and return apparatus
51: sampler
53: treatment circuit
7: clock pulse and return apparatus
71: sampler
73: treatment circuit
UI: unit gap
Embodiment
Content of the present invention is explained by following examples, but embodiments of the invention and be not used to restriction the present invention can must implement in any specific environment as will be illustrated in the example below, application or mode.Therefore, the explanation of following examples is only to explain the present invention, and is not used to limit the present invention.Following examples and graphic in, the element relevant to non-immediate of the present invention omits and does not illustrate, and be illustrated in graphic in each element between dimension scale only for ease of understanding, and be not used to be restricted to actual enforcement ratio.
The first embodiment of the present invention is in order to set forth a kind of clock pulse of the present invention and return apparatus, and its related description refers to Figure 1A and Figure 1B.Figure 1A is the clock pulse of the present embodiment and the schematic diagram of return apparatus 1, and Figure 1B is the schematic diagram that clock pulse and return apparatus 1 carry out sample of signal.As shown in Figure 1A, clock pulse and return apparatus 1 comprise sampler 11 and a treatment circuit 13, and sampler 11 comprises the first edge sample circuit 113 that a phase generating circuit 111 and is electrically connected to phase generating circuit 111.Clock pulse and return apparatus 1 can be used for the receiving terminal of the high speed serialization formula transmission system of various mode, the data that the transmitting terminal in order to reply high speed serialization formula transmission system transmits.
Phase generating circuit 111 is in order to produce multiple first phase 20, and wherein these first phase 20 have different phase number separately.In the present embodiment, phase generating circuit 111 is a phasescan circuit, and it such as, based on a characteristic frequency, 2.5GHz, by the mode of phasescan, can produce these first phase 20 with out of phase numerical value.First edge sample circuit 113 can sample multiple first edge value 42 of multiple bits of a data-signal 40 according to these first phase 20, treatment circuit 13 in order to judge the clock pulse of data-signal 40 according to these first edge value 42, thus correctly captures from data-signal 40 data that transmitting terminal transmits.
Treatment circuit 13 generally can be divided into analog and digital treatment circuit.For analog treatment circuit, it may be including but not limited to: phase detectors (Phase Detector), charge pump (Charge Pump), loop filter (Loop Filter) and voltage-controlled oscillator (VCO) (Voltage control oscillator, VCO); And in order to the signal transacting by analog form, the process such as the data sampled from data-signal 40 sampler 11 are added up, assess, calculating, and then judge the clock pulse that data-signal 40 is embedded, and according to judged clock pulse, carry out the reply program of data.
Similarly, for digital treatment circuit, it may be including but not limited to: demultiplexer (Demultiplexer), phase detectors, loop filter; And in order to the signal transacting by digital form, the process such as the data sampled from data-signal 40 sampler 11 are added up, assess, calculating, and then judge the clock pulse that data-signal 40 is embedded, and according to judged clock pulse, carry out the reply program of data.
More specifically, treatment circuit 13 in the Main Function of the present embodiment be the process such as the data sampled from data-signal 40 sampler 11 are added up, assessed, calculating.Accordingly, embodiments of the present invention do not affect to some extent because of the execution mode difference for the treatment of circuit 13.In other words, for treatment circuit 13, no matter adopt existing various execution mode, or can think easily future and various execution modes, neither affect normal operation of the present invention in essence.In addition, the concrete running of the above-mentioned various element (comprising analog and digital) comprised because for the treatment of circuit 13 can be those skilled in the art and understands easily, seldom repeats in this.
Data-signal 40 can comprise multiple bit.But for convenience of explanation, the present embodiment will only be described for wherein five bits, be expressed as the first bit 401, second bit 402, the 3rd bit 403, nibble 404 and the 5th bit 405.In addition, the data types of the first bit 401, second bit 402, the 3rd bit 403, nibble 404 and the 5th bit 405 is expressed as 1,1,0,1 and 0.The quantity of the bit described in the present embodiment and the data shape of bit only in order to explain the present invention, and are not used to limit the present invention; And according to the disclosure of the present embodiment, those skilled in the art can touch and to the execution mode of the different quantity of bit or the data shape of different bits.
As shown in Figure 1B, the data types of the first bit 401, second bit 402, the 3rd bit 403, nibble 404 and the 5th bit 405 is respectively 1,1,0,1 and 0, and wherein the minimum resolution of the unit gap (UI) of each bit is 1/8UI.According to above-mentioned five bits, phase generating circuit 111 can produce five corresponding first phase 20, sequentially represents with first phase 201, second phase 202, third phase 203, the 4th phase place 204 and the 5th phase place 205.Now, by the process that phase place scans, first phase 201, second phase 202, third phase 203, the 4th phase place 204 and the 5th phase place 205 can have different phase number, such as can be sequentially-4 π/8 ,-2 π/8,0,2 π/8 and 4 π/8, with corresponding with the first bit 401, second bit 402, the 3rd bit 403, nibble 404 and the 5th bit 405.
First edge sample circuit 113 according to first phase 201, second phase 202, third phase 203, the 4th phase place 204 and the 5th phase place 205, can learn that this equiphase corresponds to the representation of time zone lattice.For example, suppose first phase 201, second phase 202, third phase 203, the phase number of the 4th phase place 204 and the 5th phase place 205 be sequentially-4 π/8 ,-2 π/8,0,2 π/8 and 4 π/8, then correspond to time zone every sampling point (or sampling interval) be sequentially-2/8UI ,-1/8UI, 0,1/8UI and 2/8UI.Then, first edge sample circuit 113 can according to above-mentioned sampling point, namely-2/8UI ,-1/8UI, 0,1/8UI and 2/8UI, sequentially edge sampling (Edge Sample) is carried out to the first bit 401 of data-signal 40, second bit 402, the 3rd bit 403, nibble 404 and the 5th bit 405, use and sample out multiple first edge value 42.
Edge sampling described in the present embodiment is the leading edge (Early Edge) for each bit, and in other embodiments, also can sample for the back edge of each bit (Late Edge), or optionally replace between the two, be not limited to the execution mode described in the present embodiment.
Pass through aforesaid operations, the phase place sampling institute's foundation for the edge that the first bit 401, second bit 402, the 3rd bit 403, nibble 404 and the 5th bit 405 carry out due to the first edge sample circuit 113 is not fixing, namely, the sampling point carrying out edge sampling for each bit is not fixing, makes these sampled first edge value 42 can have larger covering scope.Due to the reference data that these first edge value 42 can provide treatment circuit 13 wider, make treatment circuit 13 can judge the clock pulse of data-signal 40 more accurately, thus in data-signal 40, correctly capture the data that transmitting terminal transmits.
Palpus expositor, the minimum resolution of the unit gap described in the present embodiment and these phase number are only in order to illustrate the present invention, and be not used to limit embodiments of the present invention, namely, the minimum resolution of the unit gap described in the present embodiment and these phase number can be adjusted equivalently according to different performances or be changed, and can not affect normal operation of the present invention.
The second embodiment of the present invention is in order to set forth a kind of clock pulse of the present invention and return apparatus, and its related description refers to Fig. 2 A and Fig. 2 B.Fig. 2 A is the clock pulse of the present embodiment and the schematic diagram of return apparatus 3, and Fig. 2 B is the schematic diagram that clock pulse and return apparatus 3 carry out sample of signal.As shown in Figure 2 A, clock pulse and return apparatus 3 comprise sampler 31 and a treatment circuit 33, and sampler 31 comprises the first edge sample circuit 113 and one second edge sample circuit 115 that a phase generating circuit 111, is electrically connected to phase generating circuit 111.Clock pulse and return apparatus 3 can be used for the receiving terminal of the high speed serialization formula transmission system of various mode, the data that the transmitting terminal in order to reply high speed serialization formula transmission system transmits.
Except the element illustrated in the present embodiment, other elements all can be regarded as the corresponding element of previous embodiment, and the label of subelement that the present embodiment will be continued to use described in previous embodiment, the element wherein with identical label can be regarded as element identical or approximate in essence.The present embodiment is by only just different with previous embodiment technology contents, and the technology contents relevant to previous embodiment, because can think easily according to previous embodiment and, will no longer repeat in the present embodiment.
The Main Differences of the present embodiment and the first embodiment is that sampler 31 also comprises the second edge sample circuit 115, and wherein the second edge sample circuit 115 can in order to multiple second edge value 44 of the multiple bits according to a second phase 22 sampled data signal 40.On the other hand, treatment circuit 33 can judge the clock pulse of data-signal 40 according to multiple first edge value 42 and multiple second edge value 44, thus correctly captures from data-signal 40 data that transmitting terminal transmits.
The first edge sample circuit 113 of the present embodiment is identical with the running described in the first embodiment, namely by the first phase 20 of multiple out of phase numerical value, such as first phase 201, second phase 202, third phase 203, the 4th phase place 204 and the 5th phase place 205, to data-signal 40, such as the first bit 401, second bit 402, the 3rd bit 403, nibble 404 and the 5th bit 405, carry out edge sampling.As for the second edge sample circuit 115, be then according to a stationary phase numerical value (i.e. second phase 22) to data-signal 40, such as the first bit 401, second bit 402, the 3rd bit 403, nibble 404 and the 5th bit 405 carry out edge sampling.
As shown in Figure 2 B, the phase number of second phase 22 is a fixed numbers, such as can be 0 or 16 π/8(and zero phases), now, the second edge sample circuit 115 can judge second phase 22 correspond to time zone every sampling point (or sampling interval) should be 1UI.Then, second edge sample circuit 115 can according to above-mentioned fixing sampling point, namely 1UI, sequentially edge sampling is carried out to the first bit 401 of data-signal 40, second bit 402, the 3rd bit 403, nibble 404 and the 5th bit 405, use and sample out multiple second edge value 44.
The phase number of the second phase 22 described in the present embodiment is only in order to illustrate the present invention, and be not used to limit embodiments of the present invention, namely, the phase number of the second phase 22 described in the present embodiment can be adjusted equivalently according to different performances or be changed, and can not affect normal operation of the present invention.
By aforesaid operations, sampler 31 can with stationary phase and non-stationary phase two kinds of patterns, the multiple bits to data-signal 40 carry out edge sampling simultaneously.The data sampled due to sampler 31 to contain aspect wider, making treatment circuit 33 when judging the embedded clock pulse of data-signal 40, more reference data can be had.In other words, treatment circuit 33 can judge the clock pulse of data-signal 40 more accurately, thus in data-signal 40, correctly capture the data that transmitting terminal transmits.
Except above-mentioned running, clock pulse described in the present embodiment and return apparatus 3 also can perform all operations described by previous embodiment and produce corresponding function, and art technical staff can be directly acquainted with clock pulse described in the present embodiment and return apparatus 3 is how perform these based on the disclosure of previous embodiment operate and produce these functions, repeat no more in this.
The third embodiment of the present invention is in order to set forth a kind of clock pulse of the present invention and return apparatus, and its related description refers to Fig. 3 A and Fig. 3 B.Fig. 3 A is the clock pulse of the present embodiment and the schematic diagram of return apparatus 5, and Fig. 3 B is the schematic diagram that clock pulse and return apparatus 5 carry out sample of signal.As shown in Figure 3A, clock pulse and return apparatus 5 comprise sampler 51 and a treatment circuit 53, and sampler 51 comprises the first edge sample circuit 113 and sampling core circuit 117 that a phase generating circuit 111, is electrically connected to phase generating circuit 111.Clock pulse and return apparatus 5 can be used for the receiving terminal of the high speed serialization formula transmission system of various mode, the data that the transmitting terminal in order to reply high speed serialization formula transmission system transmits.
Except the element illustrated in the present embodiment, other elements all can be regarded as the corresponding element of previous embodiment, and the label of subelement that the present embodiment will be continued to use described in previous embodiment, the element wherein with identical label can be regarded as element identical or approximate in essence.The present embodiment is by only just different with previous embodiment technology contents, and the technology contents relevant to previous embodiment, because can think easily according to previous embodiment and, will no longer repeat in the present embodiment.
Under the structure of twice oversampling (2x Over sampling), clock pulse and return apparatus can carry out two sub-samplings to each bit (or each unit gap), once sample for the data center of each bit, be once sample for the edge of each bit, wherein data center's sampling refers to that the center of each bit comprised for the signal received samples.
Be different from the clock pulse described in the first embodiment and return apparatus 1, sampler 51 also comprises sampling core circuit 117, and wherein sampling core circuit 117 can in order to multiple center value 46 of the multiple bits according to a third phase 24 sampled data signal 40.On the other hand, treatment circuit 53 can judge the clock pulse of data-signal 40 according to multiple first edge value 42 and multiple center value 46, thus correctly captures from data-signal 40 data that transmitting terminal transmits.
The first edge sample circuit 113 of the present embodiment is identical with the running described in the first embodiment, namely by the first phase 20 of multiple out of phase numerical value, such as first phase 201, second phase 202, third phase 203, the 4th phase place 204 and the 5th phase place 205, to data-signal 40, such as the first bit 401, second bit 402, the 3rd bit 403, nibble 404 and the 5th bit 405, carry out edge sampling.As for sampling core circuit 117, then that data center's point that such as the first bit 401, second bit 402, the 3rd bit 403, nibble 404 and the 5th bit 405 are respective samples according to a stationary phase numerical value (i.e. third phase 22) and in order to for data-signal 40.
As shown in Figure 3 B, the phase number of third phase 24 is a fixed numbers, such as, can be π, now, sampling core circuit 117 can judge third phase 24 correspond to time zone every sampling point (or sampling interval) should be 4/8UI.Then, sampling core circuit 117 can according to above-mentioned sampling point, namely 4/8UI, sequentially respective to the first bit 401 of data-signal 40, second bit 402, the 3rd bit 403, nibble 404 and the 5th bit 405 data center's point samples, and uses and samples out multiple center value 46.
The phase number of the third phase 24 described in the present embodiment is only in order to illustrate the present invention, and be not used to limit embodiments of the present invention, namely, the phase number of the third phase 24 described in the present embodiment can be adjusted equivalently according to different performances or be changed, and can not affect normal operation of the present invention.Moreover data center's point of the sampling core circuit 117 multiple bits how sampled data signal 40 comprises, not only as described in the embodiment, and other execution modes of sampling core circuit 117 are by those skilled in the art are understood, and repeat no more in this.
Be different from traditional twice oversampling structure, the phase place that the first edge sample circuit 113 of the present embodiment samples institute's foundation for the edge that the first bit 401, second bit 402, the 3rd bit 403, nibble 404 and the 5th bit 405 carry out is not fixing, namely, the sampling point carrying out edge sampling for each bit is not fixing, makes these sampled first edge value 42 can have larger covering scope.Due to the reference data that these first edge value 42 can provide treatment circuit 13 wider, make treatment circuit 13 can judge the clock pulse of data-signal 40 more accurately, thus in data-signal 40, correctly capture the data that transmitting terminal transmits.Accordingly, the clock pulse described in the present embodiment and return apparatus 5 can realize the structure of twice oversampling easily, and have better performance.
Except above-mentioned running, clock pulse described in the present embodiment and return apparatus 5 also can perform all operations described by previous embodiment and produce corresponding function, and art technical staff can be directly acquainted with clock pulse described in the present embodiment and return apparatus 5 is how perform these based on the disclosure of previous embodiment operate and produce these functions, repeat no more in this.
The fourth embodiment of the present invention is in order to set forth a kind of clock pulse of the present invention and return apparatus, and its related description refers to Fig. 4 A and Fig. 4 B.Fig. 4 A is the clock pulse of the present embodiment and the schematic diagram of return apparatus 7, and Fig. 4 B is the schematic diagram that clock pulse and return apparatus 7 carry out sample of signal.As shown in Figure 4 A, clock pulse and return apparatus 7 comprise sampler 71 and a treatment circuit 73, and sampler 71 comprises the first edge sample circuit 113,1 second edge sample circuit 115 and sampling core circuit 117 that a phase generating circuit 111, is electrically connected to phase generating circuit 111.Clock pulse and return apparatus 7 can be used for the receiving terminal of the high speed serialization formula transmission system of various mode, the data that the transmitting terminal in order to reply high speed serialization formula transmission system transmits.
Except the element illustrated in the present embodiment, other elements all can be regarded as the corresponding element of previous embodiment, and the label of subelement that the present embodiment will be continued to use described in previous embodiment, the element wherein with identical label can be regarded as element identical or approximate in essence.The present embodiment is by only just different with previous embodiment technology contents, and the technology contents relevant to previous embodiment, because can think easily according to previous embodiment and, will no longer repeat in the present embodiment.
The Main Differences of the present embodiment and previous embodiment is sampler 31 except comprising phase generating circuit 111 and the first edge sample circuit 113, comprises the second edge sample circuit 115 and sampling core circuit 117 more simultaneously.Be same as described in the second embodiment, the second edge sample circuit 115 described in the present embodiment can in order to multiple second edge value 44 of the multiple bits according to a second phase 22 sampled data signal 40; And being same as described in the 3rd embodiment, the sampling core circuit 117 described in the present embodiment can in order to multiple center value 46 of the multiple bits according to a third phase 24 sampled data signal 40.On the other hand, treatment circuit 73 can judge the clock pulse of data-signal 40 according to multiple first edge value 42, multiple second edge value 44 and multiple center value 46, thus correctly captures from data-signal 40 data that transmitting terminal transmits.
Further, identical with described in the second embodiment and the 3rd embodiment in the second edge sample circuit 115 of the present embodiment and the respective running of sampling core circuit 117 and respective possessed function quintessence thereof.Therefore, by the disclosure of the second embodiment and the 3rd embodiment, those skilled in the art can think and the clock pulse of the present embodiment and return apparatus 7 function mode easily, repeat no more in this.
Except above-mentioned running, clock pulse described in the present embodiment and return apparatus 7 also can perform all operations described by previous embodiment and produce corresponding function, and art technical staff can be directly acquainted with clock pulse described in the present embodiment and return apparatus 7 is how perform these based on the disclosure of previous embodiment operate and produce these functions, repeat no more in this.
The fifth embodiment of the present invention is in order to set forth a kind of sampling method for a clock pulse and return apparatus of the present invention, and its related description refers to Fig. 5.Fig. 5 is the flow chart of a kind of sampling method of the present embodiment.Sampling method described in the present embodiment can be used for clock pulse that foregoing individual embodiments discloses and return apparatus, i.e. return apparatus 1, clock pulse and return apparatus 3, clock pulse and return apparatus 5 and clock pulse and return apparatus 7.Therefore, the clock pulse described in the present embodiment and return apparatus can comprise a sampler and a treatment circuit, and wherein this sampler can comprise the first edge sample circuit that a phase generating circuit and is electrically connected to this phase generating circuit.
As shown in Figure 5, in step S51, make this phase generating circuit produce multiple first phase, wherein these first phase have different phase number; In step S53, this first edge sample circuit is made to sample multiple first edge value of multiple bits of a data-signal according to these first phase; And in step S55, make this treatment circuit judge a clock pulse of this data-signal according to these first edge value.
When the sampling method of the present embodiment is used for the clock pulse that discloses of the second embodiment and return apparatus 3, the sampling method of the present embodiment also comprises step S57: make one second edge sample circuit of this sampler sample multiple second edge value of multiple bits of this data-signal according to a second phase.Now, step S55 is step S551: make this treatment circuit judge this clock pulse of this data-signal according to these first edge value and these the second edge value.
When the sampling method of the present embodiment is used for the clock pulse that discloses of the 3rd embodiment and return apparatus 5, the sampling method of the present embodiment also comprises step S57: make a sampling core circuit of this sampler sample multiple center value of these bits of this data-signal according to a third phase.Now, step S55 is step S553: make this treatment circuit judge this clock pulse of this data-signal according to these first edge value and these center value.
When the sampling method of the present embodiment is used for the clock pulse that discloses of the 4th embodiment and return apparatus 7, the sampling method of the present embodiment also comprises step S57 and step S59.Now, step S55 is step S555: make this treatment circuit judge this clock pulse of this data-signal according to these first edge value, these second edge value and these center value.
Except above-mentioned steps, sampling method described in 5th embodiment also can perform all operations described by previous embodiment and produce corresponding function, and the art technical staff sampling method that can be directly acquainted with described in the present embodiment how performs these operations based on the disclosure of previous embodiment and produce these functions, repeats no more in this.
In sum, the present invention provides a kind of clock pulse and return apparatus, sampler and sampling method thereof altogether.Be different from traditional clock pulse and data recovery circuit interface, clock pulse provided by the invention and return apparatus, sampler and sampling method thereof produce multiple out of phase by phasescan, and according to the phase place of these out of phase numerical value, the edge of multiple bits of data-signal is sampled respectively.
Sampled by described phasescan mode, sampling point will be no longer fixing, the edge value sampled for multiple edges of multiple bits of data-signal can contain wider scope, therefore the marginal position of the multiple bits data-signal can be estimated more quickly and more accurately, thus judge the correct clock pulse that this data-signal is embedded.Accordingly, clock pulse provided by the invention and return apparatus, sampler and sampling method thereof improve the accuracy rate of sampling effectively, the related shake tolerance adding receiving terminal.
The content that above-described embodiment is set forth only in order to exemplify some embodiments of the present invention, and explains technical characteristic of the present invention, and is not used to limit essence of the present invention protection category.Therefore, any those skilled in the art the arrangement of unlabored change or isotropism can all belong to the scope that the present invention advocates, and protection scope of the present invention is as the criterion with right.
Claims (12)
1. a sampler, for a clock pulse and return apparatus, this sampler comprises:
One phase generating circuit, in order to produce multiple first phase, the plurality of first phase has different phase number; And
One first edge sample circuit, be electrically connected to this phase generating circuit, this the first edge sample circuit, in order to sample multiple first edge value of multiple bits of a data-signal according to the plurality of first phase, makes this clock pulse and return apparatus judge a clock pulse of this data-signal according to the plurality of first edge value.
2. sampler as claimed in claim 1, also comprises:
One second edge sample circuit, in order to sample multiple second edge value of the plurality of bit of this data-signal according to a second phase, judge this clock pulse of this data-signal with this clock pulse and return apparatus according to the plurality of first edge value and the plurality of second edge value.
3. sampler as claimed in claim 1, also comprises:
One sampling core circuit, in order to sample multiple center value of the plurality of bit of this data-signal according to a third phase, judges this clock pulse of this data-signal with this clock pulse and return apparatus according to the plurality of first edge value and the plurality of center value.
4. sampler as claimed in claim 2, also comprises:
One sampling core circuit, in order to sample multiple center value of the plurality of bit of this data-signal according to a third phase, judge this clock pulse of this data-signal with this clock pulse and return apparatus according to the plurality of first edge value, the plurality of second edge value and the plurality of center value.
5. clock pulse and a return apparatus, comprises:
One sampler, comprises
One phase generating circuit, in order to produce multiple first phase, the plurality of first phase has different phase number; And
One first edge sample circuit, is electrically connected to this phase generating circuit, and this first edge sample circuit is in order to sample multiple first edge value of multiple bits of a data-signal according to the plurality of first phase; And
One treatment circuit, in order to judge a clock pulse of this data-signal according to the plurality of first edge value.
6. clock pulse as claimed in claim 5 and return apparatus, wherein this sampler also comprises:
One second edge sample circuit, in order to sample multiple second edge value of the plurality of bit of this data-signal according to a second phase; And
This treatment circuit judges this clock pulse of this data-signal according to the plurality of first edge value and the plurality of second edge value.
7. clock pulse as claimed in claim 5 and return apparatus, wherein this sampler also comprises:
One sampling core circuit, in order to sample multiple center value of the plurality of bit of this data-signal according to a third phase; And
This treatment circuit judges this clock pulse of this data-signal according to the plurality of first edge value and the plurality of center value.
8. clock pulse as claimed in claim 6 and return apparatus, wherein this sampler also comprises:
One sampling core circuit, in order to sample multiple center value of the plurality of bit of this data-signal according to a third phase; And
This treatment circuit judges this clock pulse of this data-signal according to the plurality of first edge value, the plurality of second edge value and the plurality of center value.
9. a sampling method, for a clock pulse and return apparatus, this clock pulse and return apparatus comprise a sampler and a treatment circuit, this sampler comprises the first edge sample circuit that a phase generating circuit and is electrically connected to this phase generating circuit, and this sampling method comprises the following step:
A () makes this phase generating circuit produce multiple first phase, wherein the plurality of first phase has different phase number;
B () makes this first edge sample circuit sample multiple first edge value of multiple bits of a data-signal according to the plurality of first phase; And
C () makes this treatment circuit judge a clock pulse of this data-signal according to the plurality of first edge value.
10. sampling method as claimed in claim 9, also comprises the following step:
D () makes one second edge sample circuit of this sampler sample multiple second edge value of multiple bits of this data-signal according to a second phase;
Wherein this step (c) is the following step:
(c1) this treatment circuit is made to judge this clock pulse of this data-signal according to the plurality of first edge value and the plurality of second edge value.
11. sampling methods as claimed in claim 9, also comprise the following step:
E () makes a sampling core circuit of this sampler sample multiple center value of the plurality of bit of this data-signal according to a third phase;
Wherein this step (c) is the following step:
(c2) this treatment circuit is made to judge this clock pulse of this data-signal according to the plurality of first edge value and the plurality of center value.
12. sampling methods as claimed in claim 10, also comprise the following step:
E () makes a sampling core circuit of this sampler sample multiple center value of the plurality of bit of this data-signal according to a third phase;
Wherein this step (c1) is the following step:
(c3) this treatment circuit is made to judge this clock pulse of this data-signal according to the plurality of first edge value, the plurality of second edge value and the plurality of center value.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310303312.5A CN104300968A (en) | 2013-07-18 | 2013-07-18 | Clock pulse and data reply device, sampler and sampling method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310303312.5A CN104300968A (en) | 2013-07-18 | 2013-07-18 | Clock pulse and data reply device, sampler and sampling method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN104300968A true CN104300968A (en) | 2015-01-21 |
Family
ID=52320566
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201310303312.5A Pending CN104300968A (en) | 2013-07-18 | 2013-07-18 | Clock pulse and data reply device, sampler and sampling method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN104300968A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107800427A (en) * | 2016-09-05 | 2018-03-13 | 创意电子股份有限公司 | Clock data recovery module |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6266799B1 (en) * | 1997-10-02 | 2001-07-24 | Xaqti, Corporation | Multi-phase data/clock recovery circuitry and methods for implementing same |
| US20040114632A1 (en) * | 2002-11-29 | 2004-06-17 | Fumio Yuuki | Clock and data recovery method and digital circuit for the same |
| US20080175310A1 (en) * | 2007-01-19 | 2008-07-24 | Samsung Electronics Co., Ltd. | Receiver with equalizer and method of operation |
| US7492850B2 (en) * | 2005-08-31 | 2009-02-17 | International Business Machines Corporation | Phase locked loop apparatus with adjustable phase shift |
| CN101496286A (en) * | 2006-07-27 | 2009-07-29 | 松下电器产业株式会社 | Pulse synchronization demodulation device |
| US7765074B2 (en) * | 2003-02-11 | 2010-07-27 | Rambus Inc. | Circuit, apparatus and method for capturing a representation of a waveform from a clock-data recovery (CDR) unit |
-
2013
- 2013-07-18 CN CN201310303312.5A patent/CN104300968A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6266799B1 (en) * | 1997-10-02 | 2001-07-24 | Xaqti, Corporation | Multi-phase data/clock recovery circuitry and methods for implementing same |
| US20040114632A1 (en) * | 2002-11-29 | 2004-06-17 | Fumio Yuuki | Clock and data recovery method and digital circuit for the same |
| US7765074B2 (en) * | 2003-02-11 | 2010-07-27 | Rambus Inc. | Circuit, apparatus and method for capturing a representation of a waveform from a clock-data recovery (CDR) unit |
| US7492850B2 (en) * | 2005-08-31 | 2009-02-17 | International Business Machines Corporation | Phase locked loop apparatus with adjustable phase shift |
| CN101496286A (en) * | 2006-07-27 | 2009-07-29 | 松下电器产业株式会社 | Pulse synchronization demodulation device |
| US20080175310A1 (en) * | 2007-01-19 | 2008-07-24 | Samsung Electronics Co., Ltd. | Receiver with equalizer and method of operation |
Non-Patent Citations (5)
| Title |
|---|
| A fully digital clock and data recovery with fast frequency offset acquisition technique for MIPI LLI applications;June-Hee Lee，Sang-Hoon Kim,Young-Hyun Jun,Kee-Won Kwon;《IEICE Electronics Express》;20130525;第10卷(第10期);全文 * |
| A fully digital clock and data recovery with fast frequency offset acquisition technique for MIPI LLI applications;June-Hee Lee，Sang-Hoon Kim,Young-Hyun Jun,Kee-Won Kwon;《IEICE Electronics Express》;20130525;第10卷(第10期);正文第2页第4段-第3页第1段，第6页第3段，图2 * |
| A Multiple一Rotating-Clock一Phase Architecture forDigital Data Recovery Circuits using Verilog-A;S.J.Ahmed and Tad A. Kwasniewski;《IEEE International Behavioral Modelingn and Simulation Conference》;20050923;全文 * |
| JUNE-HEE LEE，SANG-HOON KIM,YOUNG-HYUN JUN,KEE-WON KWON: "A fully digital clock and data recovery with fast frequency offset acquisition technique for MIPI LLI applications", 《IEICE ELECTRONICS EXPRESS》 * |
| S.J.AHMED AND TAD A. KWASNIEWSKI: "A Multiple一Rotating-Clock一Phase Architecture forDigital Data Recovery Circuits using Verilog-A", 《IEEE INTERNATIONAL BEHAVIORAL MODELINGN AND SIMULATION CONFERENCE》 * |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107800427A (en) * | 2016-09-05 | 2018-03-13 | 创意电子股份有限公司 | Clock data recovery module |
| CN107800427B (en) * | 2016-09-05 | 2021-04-06 | 创意电子股份有限公司 | Clock data recovery module |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US9577815B1 (en) | Clock data alignment system for vector signaling code communications link | |
| US10965290B2 (en) | Phase rotation circuit for eye scope measurements | |
| US10587394B2 (en) | High performance phase locked loop | |
| CN105391537B (en) | The method and device thereof of data sampling control are executed in the electronic device | |
| KR102384609B1 (en) | Clock data recovery for multi-lane data receivers | |
| EP3114792B1 (en) | Clock recovery circuit for multiple wire data signals | |
| TWI467919B (en) | Multi-phase clock signal generating circuit having improved phase difference and a controlling method thereof | |
| US20080187080A1 (en) | Oversampling data recovery circuit and method for a receiver | |
| CN108449086B (en) | Method and circuit for synchronizing parallel ports of multi-channel high-speed serial bus sending end | |
| TW201739207A (en) | Device and method for recovering clock and data | |
| CN104300968A (en) | Clock pulse and data reply device, sampler and sampling method | |
| TWI775389B (en) | Clock data calibration circuit | |
| US20150016579A1 (en) | Clock and data recovery device, sampler and sampling method thereof | |
| US7321647B2 (en) | Clock extracting circuit and clock extracting method | |
| US8666006B1 (en) | Systems and methods for high speed data recovery with free running sampling clock | |
| CN105099410B (en) | Clock pulse data reflex circuit and method and grade signal analysis circuit and method | |
| CN101997543A (en) | Frequency discriminator and method for realizing frequency discrimination | |
| Kadayinti et al. | A clock synchronizer for repeaterless low swing on-chip links | |
| CN213152037U (en) | High-speed low-jitter data synchronous phase discriminator | |
| Park et al. | A 1.0 Gbps CMOS oversampling data recovery circuit with fine delay generation method | |
| Du et al. | A low-power, fast acquisition, data recovery circuit with digital threshold decision for SFI-5 application | |
| Luan et al. | A 1.25-8.5 Gb/s wide range CDR with locking detector in 40 nm CMOS technology | |
| CN105512069B (en) | Deserializer device and its asynchronous conversion method | |
| Lin et al. | A novel 1.2 Gbps LVDS receiver for multi-channel applications | |
| Nagavarapu et al. | An asynchronous data recovery/retransmission technique with foreground DLL calibration |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| WD01 | Invention patent application deemed withdrawn after publication | ||
| WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20150121 |