CN104410132B - Voltage balancing device of supercapacitor and control method of voltage balancing device - Google Patents
Voltage balancing device of supercapacitor and control method of voltage balancing device Download PDFInfo
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- CN104410132B CN104410132B CN201410798400.1A CN201410798400A CN104410132B CN 104410132 B CN104410132 B CN 104410132B CN 201410798400 A CN201410798400 A CN 201410798400A CN 104410132 B CN104410132 B CN 104410132B
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Abstract
The invention provides a voltage balancing device of a supercapacitor and a control method of the voltage balancing device, relates to the energy storage technology of the supercapacitor, and aims to solve the problem that the service life of the supercapacitor is shortened due to inconsistent voltage of shunt sections of the supercapacitor. According to the voltage balancing device of the supercapacitor and the control method of the voltage balancing device, each energy storage unit is equipped with a balance controller which is controlled by a master controller, so that voltage of the shunt sections of the supercapacitor is balanced, consistent voltage of the shunt sections is kept, the service life of the supercapacitor is prolonged, and the energy storage quality of the supercapacitor is improved; and besides, the voltage balancing device of the supercapacitor and the control method of the voltage balancing device have the advantages that detection for voltage of the shunt sections of the supercapacitor is accurate, charge and discharge efficiency of the supercapacitor is high, the voltage balancing speed is high, the voltage consistency is good, capacity and internal resistance of the supercapacitor are identified accurately, module power density is high and the like.
Description
Technical field
The present invention relates to the energy storage technology of ultracapacitor.
Background technology
Ultracapacitor be from the 1970s and 1980s in last century grow up by polarized electrolytic matter come a kind of electricity of energy storage
Chemical component.Outstanding advantages are that power density is high, the discharge and recharge time is short, have extended cycle life, operating temperature range width, are in the world
Put into maximum one kind of capacity in the double layer capacitor of volume production.But ultracapacitor there is also some problems, for example each
Economize on electricity pressure in parallel is inconsistent, shortens service life of ultracapacitor etc..
Content of the invention
The invention aims to each parallel connection economize on electricity pressure of solution ultracapacitor is inconsistent, ultracapacitor is led to make
With the problem of the lost of life, provide the control method of a kind of ultracapacitor voltage balancer and this device.
Ultracapacitor voltage balancer of the present invention includes master controller, total current/voltage detection unit, many
Individual balance controller and DC-DC power module；
DC-DC power module is master controller, total current/voltage detection unit and multiple balance controller offer work
Power supply；
Master controller connects described multiple balance controllers and total current/voltage detection unit；
Each balance controller is used for measuring the n of ultracapacitor and the terminal voltage of interlink be described n simultaneously interlink
Charge；
Total current/voltage detection unit is used for detecting total voltage and the total current of ultracapacitor output port.
Balance controller include n interlink balancing unit, m simulate switching circuit, AD process circuit, at Balance route
Reason device, processes temperature signal circuit, light-coupled isolation communicating circuit and insulating power supply, m is less than n；
It is one that each and interlink balancing unit are used for and interlink charges, and the control signal input of interlink balancing unit
Connect the charging control signal outfan of Balance route processor；
Each simulation switching circuit is used for measuring multiple and interlink terminal voltage, and m simulation switching circuit measures n simultaneously altogether
The terminal voltage of interlink, and measurement result is sent to Balance route processor by AD process circuit；
The outfan of processes temperature signal circuit connects the temperature signal input of Balance route processor, at temperature signal
The input of reason circuit is used for connecting temperature sensor；
Temperature sensor is used for measuring the temperature of energy-storage units, and measurement result is sent by processes temperature signal circuit
To Balance route processor, described energy-storage units include balance controller and the simultaneously interlink being connected with this balance controller；
Balance route processor refrigeration control signal output part is used for the control signal input of connecting fan；
Balance route processor is carried out data transmission by CAN signal transmission line and master controller.
Described Balance route processor is embedded in the Balance route interrupting submodule realized by software, this module include with
Lower unit：
Economize on electricity pressure reading unit in parallel：Constantly read and store the n economize on electricity pressure in parallel that m simulation switching circuit is sent
Value；And start economize on electricity pressure sequencing unit in parallel after this unit end of run；
Economize on electricity pressure sequencing unit in parallel：Described n section magnitude of voltage in parallel is ranked up according to by high order on earth；
And start overall charging instruction judging unit after this unit end of run；
Overall charging instruction judging unit：Judge whether to receive the overall charging instruction that master controller is sent, and sentencing
Disconnected result is to start overall charging instruction transmitting element when being, judged result for no when start the first maximum voltage difference judge single
Unit；
Overall charging instruction transmitting element：Send charging instruction to the individual simultaneously interlink balancing unit of n；And run knot in this unit
Start overall charging END instruction judging unit after bundle；
Overall charging END instruction judging unit：Judge whether to receive the entirety charging END instruction that master controller is sent,
And stop overall charging instruction transmitting element in judged result for starting when being；Judged result for no when restart overall filling
Electric END instruction judging unit；
Stop overall charging instruction transmitting element：Send to the individual simultaneously interlink balancing unit of n and stop charging instruction；And it is single at this
Start the first maximum voltage difference judging unit after first end of run；
First maximum voltage difference judging unit：Whether judge the difference of maxima and minima in n section magnitude of voltage in parallel
More than Δ U, and judged result be when start selective charge instruction sending unit, judged result for no when start identification
Unit；
Selective charge instruction sending unit：To magnitude of voltage minimum three and corresponding to interlink and interlink balancing unit
Send charging instruction；And start the second maximum voltage difference judging unit after this unit end of run；
Second maximum voltage difference judging unit：Whether judge the difference of maxima and minima in n section magnitude of voltage in parallel
More than Δ U, and judged result be when restart the second maximum voltage difference judging unit, judged result for no when start
Stop selective charge instruction forwarding step；
Stop selective charge instruction forwarding step：Corresponding to three and interlink and interlink balancing unit sends and stops
Charging instruction；And start identification unit after this unit end of run；
Identification unit：Calculate capacity and the internal resistance of super capacitor；And start identification result after this unit end of run
Transmitting element；
Identification result transmitting element：Calculated for identification unit and interlink capacity and internal resistance are sent to master controller；
And start temperature conditioning unit after this unit end of run；
Temperature conditioning unit：The temperature controlling energy-storage units is within the temperature range of its normal work；And run knot in this unit
Start overall charging instruction judging unit after bundle.
The control method of above-mentioned ultracapacitor voltage balancer comprises the following steps：
Economize on electricity pressure read step in parallel：Constantly read and store the n economize on electricity pressure in parallel that m simulation switching circuit is sent
Value；And execute economize on electricity pressure sequence step in parallel after this step terminates；
Economize on electricity pressure sequence step in parallel：Described n section magnitude of voltage in parallel is ranked up according to by high order on earth；
And execute overall charging instruction after this step terminates and judge step；
Overall charging instruction judges step：Judge whether to receive the overall charging instruction that master controller is sent, and sentencing
Disconnected result is execution overall charging instruction forwarding step when being, judged result for no when execute the first maximum voltage difference and judge step
Suddenly；
Overall charging instruction forwarding step：Send charging instruction to the individual simultaneously interlink balancing unit of n；And terminate it in this step
Execute overall charging END instruction afterwards and judge step；
Overall charging END instruction judges step：Judge whether to receive the entirety charging END instruction that master controller is sent,
And stop overall charging instruction forwarding step in judged result for execution when being；Judged result for no when re-execute overall filling
Electric END instruction judges step；
Stop overall charging instruction forwarding step：Send to the individual simultaneously interlink balancing unit of n and stop charging instruction；And in this step
Suddenly execute the first maximum voltage difference after terminating and judge step；
First maximum voltage difference judges step：Whether judge the difference of maxima and minima in n section magnitude of voltage in parallel
More than Δ U, and judged result be when execution selective charge instruction forwarding step, judged result for no when execute identification
Step；
Selective charge instructs forwarding step：To magnitude of voltage minimum three and corresponding to interlink and interlink balancing unit
Send charging instruction；And execute the second maximum voltage difference after this step terminates and judge step；
Second maximum voltage difference judges step：Whether judge the difference of maxima and minima in n section magnitude of voltage in parallel
More than Δ U, and re-execute the second maximum voltage difference and judge step when judged result is and is, judged result for no when execute
Stop selective charge instruction forwarding step；
Stop selective charge instruction forwarding step：Corresponding to three and interlink and interlink balancing unit sends and stops
Charging instruction；And execute identification step after this step terminates；
Identification step：Calculate capacity and the internal resistance of super capacitor；And execute identification result transmission after this step terminates
Step；
Identification result forwarding step：To recognize that step is calculated and interlink capacity and internal resistance send to master controller；
And execute temperature control step after this step terminates；
Temperature control step：The temperature controlling energy-storage units is within the temperature range of its normal work；And terminate in this step row
Return the overall charging instruction of execution afterwards and judge step.
Ultracapacitor voltage balancer of the present invention and the control method of this device, join for each energy-storage units
Put balance controller, balance controller, by by main controller controls, equalizes the voltage of each simultaneously interlink of super capacitor, makes each parallel connection
Junction voltage is consistent, thus extending the life-span of super capacitor, the energy storage quality of lifting ultracapacitor.DC-DC power module
Condenser voltage is converted into 24V constant voltage source and supplements pressure reduction for energy-storage units.This device has the economize on electricity in parallel to super capacitor
Accurately, super capacitor efficiency for charge-discharge is high for pressure detection, and electric voltage equalization speed is fast, and voltage concordance is good, super capacitor capacity and interior
The advantages of resistance recognizes accurate, module power density is high.
Brief description
Fig. 1 is the theory diagram of the ultracapacitor voltage balancer described in embodiment；
Fig. 2 is the functional block diagram of the master controller chip in embodiment one；
Fig. 3 is the theory diagram of energy-storage units in embodiment two；
Fig. 4 is the functional block diagram of Balance route processor in embodiment two；
Fig. 5 is the theory diagram of the AD process circuit in embodiment three；
Fig. 6 is the circuit structure diagram of the simulation switching circuit in embodiment three and AD process circuit；
Fig. 7 is the circuit structure diagram of processes temperature signal circuit in embodiment four；
Fig. 8 is the control method flow chart in embodiment ten；
Fig. 9 is the flow chart of temperature control step in embodiment 11；
Figure 10 is the equivalent circuit diagram of section capacitance in parallel and internal resistance in embodiment 12；
Figure 11 is the schematic diagram of the calculating voltage in embodiment 12；
Figure 12 is the discrimination method flow chart in embodiment 12；
Figure 13 is the circuit structure diagram of DC-DC power module in embodiment eight.
Specific embodiment
Specific embodiment one：In conjunction with Fig. 1 and Fig. 2, present embodiment, the ultracapacitor described in present embodiment are described
Voltage balancing device includes master controller 1, total current/voltage detection unit 2, multiple balance controller 3 and DC-DC power module
4；
DC-DC power module 4 is master controller 1, total current/voltage detection unit 2 and multiple balance controller 3 provide
Working power；
Master controller 1 connects described multiple balance controllers 3 and total current/voltage detection unit 2；
Each balance controller 3 is used for measuring the n of ultracapacitor and the terminal voltage of interlink be described n simultaneously interlink
Charge；
Total current/voltage detection unit 2 is used for detecting total voltage and the total current of ultracapacitor output port.
In present embodiment, the capacitor that is connected with balance controller 3 be ultracapacitor and connect.Master controller
1 chip selects the ARM chip of model STM32F407, and the framework of this chip is Cortex-M4, and 32 MCU are mono- with FPU
, there are a 210DMIPS, up to 1MB FLASH/192+4KB RAM in unit, USB OTG HS/FS, Ethernet, 17 intervalometer, 3
ADC, 15 communication interfaces and a shooting mouth, clock frequency is 168MHz.Master controller 1 is responsible for energy-storage units total current with always
The sampling of voltage, LEM current sensor selected by current sensor, and output voltage is 5V, sends into 16 after sampling processing circuit
Bit AD sample chip.Voltage sensor selects LEM voltage sample module, and output voltage is 5V, send after sampling processing circuit
Enter 16 bit AD sample chips of model AD32680.Described energy-storage units are included balance controller 3 and are controlled with this balance
The simultaneously interlink that device 3 is connected.
The function of master controller 1 includes：Reading is main to make whether contact input, energy-storage units voltage equalize judgement, temperature inspection
Survey, total voltage and total current detection, state and protection contact export, read bus data, biography equalization instruction, energy-storage units are put down
The fan control of electric control and integrating cabinet, in real time display monitoring voltage Monitoring Data and carry out telecommunication etc..
Specific embodiment two：In conjunction with Fig. 3 and Fig. 4, present embodiment is described, present embodiment is to embodiment one institute
The restriction further of the ultracapacitor voltage balancer stated, in present embodiment, described balance controller 3 includes n
And interlink balancing unit 3-1, m simulation switching circuit 3-2, AD process circuit 3-3, Balance route processor 3-4, temperature signal
Process circuit 3-5, light-coupled isolation communicating circuit 3-6 and insulating power supply, m is less than n；
It is one that each and interlink balancing unit 3-1 are used for and interlink charges, and the control signal of interlink balancing unit 3-1
Input connects the charging control signal outfan of Balance route processor 3-4；
Each simulation switching circuit 3-2 is used for measuring multiple and interlink terminal voltage, and m simulation switching circuit 3-2 is surveyed altogether
Amount n the terminal voltage of interlink, and measurement result is sent to Balance route processor 3-4 by AD process circuit 3-3；
The outfan of processes temperature signal circuit 3-5 connects the temperature signal input of Balance route processor 3-4, temperature
The input of signal processing circuit 3-5 is used for connecting temperature sensor 3-7
Temperature sensor 3-7 is used for measuring the temperature of energy-storage units, and measurement result is passed through processes temperature signal circuit
3-5 sends to Balance route processor 3-4, and described energy-storage units are included balance controller 3 and are connected with this balance controller 3
And interlink；
Balance route processor 3-4 refrigeration control signal output part is used for the control signal input of connecting fan 3-8；
Balance route processor 3-4 is carried out data transmission with master controller 1 by CAN signal transmission line.
As shown in figure 3, when using, Balance route processor 3-4 is connected with blower fan 3-8, by processes temperature signal circuit
3-5 is connected with temperature sensor 3-7, and temperature sensor 3-7 is used for measuring the temperature of energy-storage units.Multiple temperature signals can be set
Process circuit 3-5 and multiple temperature sensor 3-7, for measuring the temperature of energy-storage units diverse location.Each simulation switching electricity
Road 3-2 carries out differential sample to the voltage of one and interlink, by and the voltage difference at interlink two ends is changed into absolute voltage over the ground,
Send in AD sampling A/D chip after proportional component, filtering link and limited amplitude protection link, analog quantity is changed by AD sampling A/D chip
For digital quantity, control for voltage dynamic equalization and related exception and fault detect.As shown in figure 4, Balance route processor
3-4 adopts DSPIC30F5011 cake core to realize, and its major function is related and interlink to be made with charging judge, sends correlation
And interlink charge command.And interlink balancing unit 3-1 receives startup after order, is charged to corresponding and interlink.When simultaneously
After interlink voltage rises to predetermined value, Balance route processor 3-4 sends stopping charge command, and interlink balancing unit 3-1 is stopped
Only work.Balance route processor 3-4 also has the function that the temperature to energy-storage units is monitored, and described energy-storage units include
Balance controller 3 and the simultaneously interlink being connected with this balance controller 3.Temperature sensor 3-7 output represents the voltage letter of temperature
Number, through processes temperature signal circuit 3-5 ratio adjustment, filtering and limited amplitude protection link after send into Balance route processor 3-
4, temperature analog signal is changed into digital signal by Balance route processor 3-4, when temperature exceedes predetermined value, at Balance route
Reason device 3-4 sends the order starting blower fan.For insulating power supply and and interlink balancing unit 3-1 provides work to DC-DC power module 4
Power supply, insulating power supply export two electric pressures, including for m simulation switching circuit 3-2 and AD process circuit 3-3 offer
24V voltage, and provide for Balance route processor 3-4, processes temperature signal circuit 3-5 and light-coupled isolation communicating circuit 3-6
5V voltage.
The function of Balance route processor 3-4 includes：Section voltage detecting in parallel, the detection of energy-storage units internal temperature, parallel connection
Section capacitance and internal resistance identification, the condition monitoring of economize on electricity appearance in parallel, energy-storage units temperature control, energy-storage units internal balance list
Unit controls and the information and between master controller 1 exchanges etc..Its functional block diagram is as shown in figure 4, the control of Balance route processor 3-4
Coremaking piece selects high-performance 16 position digital signal single-chip microcomputer, model DSPIC30F5011.This chip has 12,16 tunnel ADC,
Other functions include：DSPIC30F5011 chip adopts high-performance modified model RISC CPU, and 8 interrupt priority levels, including I2C etc.
Data converter interface, two CAN modules compatible with CAN2.0B standard.
N section voltage signal in parallel, after m multi-channel analog switching circuit 3-2 selects, switchs to through AD process circuit 3-3
Sent into by the SPI serial signal of light-coupled isolation communicating circuit 3-6 after digital quantity in the single-chip microcomputer of Balance route processor 3-4.
2 temperature sensor 3-7 and 2 processes temperature signal circuit 3-5, the temperature of 2 road energy-storage units are set in present embodiment
Signal is directly sent in single-chip microcomputer, measures the conversion of digital quantity using AD simulation in piece.Multi-channel analog switching circuit 3-2
Gating is controlled by four road I/O ports of single-chip microcomputer, and the 16 road I/O ports that 16 tunnels interlink balancing unit start and stop have single-chip microcomputer control, blower fan
The break-make Ye You mono- road I/O port of 3-8 controls.External memory space is to be extended by parallel data mouth.
Specific embodiment three：In conjunction with Fig. 5 and Fig. 6, present embodiment is described, present embodiment is to embodiment two institute
The restriction further of the ultracapacitor voltage balancer stated, in present embodiment, described AD process circuit 3-3 includes mould
Intend process circuit 3-3-1, analog-to-digital converting module 3-3-2 and digital isolation module 3-3-3；
The m signal input part of analog processing circuit 3-3-1 connects the signal output of m simulation switching circuit 3-2 respectively
End, the signal output part of analog processing circuit 3-3-1 connects the input end of analog signal of analog-to-digital converting module 3-3-2, mould
The digital signal output end of plan/data-converting block 3-3-2 passes through digital isolation module 3-3-3 and connects Balance route processor 3-
4 section voltage signal inputs in parallel, the channel selecting control signal outfan of digital isolation module 3-3-3 connects m simulation
The channel selecting control signal input of switching circuit 3-2.
As shown in fig. 6, ground, then the energy storage list of 60V are elected as in the centre position of the connection in series-parallel section in energy-storage units
Unit is changed into ± 30V, then passes through each and voltage is reduced by divider resistance by interlink further, be changed into ± 15V, this voltage
Within the running voltage of amplifier, divider resistance is 32 in Fig. 6 between four simulation switching circuits 3-2 and electric capacity module to scope
Individual resistance.16 section voltage signals in parallel, after the transformation of divider resistance, (are schemed through 4 multi-channel analog switching circuits 3-2
Analog switch chip in 6) channel selecting, enter analog processing circuit 3-3-1.It is poor that the economize on electricity pressure in parallel on every road all can be passed through
Dynamic amplifier is individually sampled.Analog processing circuit 3-3-1 adopts three operational amplifiers to realize, operational amplifier model
LT1014, dual power supply 15V powers.R1 and C1 composition low-pass first order filter is filtered to voltage signal, and D1 plays amplitude limit and protects
Shield acts on.When voltage is more than 5V, Vi voltage will be clamped 5.7V, so can prevent the overvoltage of voltage signal to simulation process
The damage of circuit 3-3-1.As shown in fig. 6, the follow circuit that in analog processing circuit 3-3-1, two amplifiers on the left side are constituted can use
In impedance isolation, to eliminate the impact to sampled voltage for the conduction impedance of analog switch.
Being particularly advantageous in that of this design：1st, sampling precision is high, directly super-capacitor voltage is sampled, often
The resolution of individual section voltage sample in parallel immobilizes；2nd, error no couples, the error Zhi Yuzhe road sampling channel of voltage sample
Correlation, no coupled relation between neighboring voltage sampling.
Specific embodiment four：In conjunction with Fig. 7, present embodiment is described, present embodiment is to super described in embodiment two
The restriction further of level condenser voltage balancer.Because temperature has appreciable impact to the service life of super capacitor,
Temperature in energy-storage units to be ensured during use is less than the scope of super capacitor operating temperature it is therefore desirable to energy storage list
Temperature within unit is monitored.In this programme, the diverse location in energy-storage units places two temperature sensors, by isolate
5V power supply is powered.Temperature sensor 3-7 adopts PT100, processes temperature signal circuit 3- shown in through Fig. 7 for the output voltage signal
It is input to Balance route processor 3-4 after 5.Operational amplification circuit in processes temperature signal circuit 3-5 is realized to temperature sensing
Scaling, R2 the and C2 composition first-order low-pass ripple link of device output signal, filters the High-frequency Interference in signal.VD can prevent
Temperature signal overvoltage causes the damage of Balance route processor 3-4.
Specific embodiment five：In conjunction with Fig. 8, present embodiment is described, present embodiment is to super described in embodiment two
Level condenser voltage balancer restriction further, in present embodiment, described Balance route processor 3-4 be embedded in by
The Balance route interrupting submodule that software is realized, this module is included with lower unit：
Economize on electricity pressure reading unit in parallel：Constantly read and store the n economize on electricity in parallel that m simulation switching circuit 3-2 is sent
Pressure value；And start economize on electricity pressure sequencing unit in parallel after this unit end of run；
Economize on electricity pressure sequencing unit in parallel：Described n section magnitude of voltage in parallel is ranked up according to by high order on earth；
And start overall charging instruction judging unit after this unit end of run；
Overall charging instruction judging unit：Judge whether to receive the overall charging instruction that master controller 1 is sent, and sentencing
Disconnected result is to start overall charging instruction transmitting element when being, judged result for no when start the first maximum voltage difference judge single
Unit；
Overall charging instruction transmitting element：Send charging instruction to individual simultaneously interlink balancing unit 3-1 of n；And in this unit fortune
Row starts overall charging END instruction judging unit after terminating；
Overall charging END instruction judging unit：Judge whether to receive the entirety charging END instruction that master controller 1 is sent,
And stop overall charging instruction transmitting element in judged result for starting when being；Judged result for no when restart overall filling
Electric END instruction judging unit；
Stop overall charging instruction transmitting element：Send to individual simultaneously interlink balancing unit 3-1 of n and stop charging instruction；And
Start the first maximum voltage difference judging unit after this unit end of run；
First maximum voltage difference judging unit：Whether judge the difference of maxima and minima in n section magnitude of voltage in parallel
More than Δ U, and judged result be when start selective charge instruction sending unit, judged result for no when start identification
Unit；
Selective charge instruction sending unit：To magnitude of voltage minimum three and corresponding to interlink and interlink balancing unit
3-1 sends charging instruction；And start the second maximum voltage difference judging unit after this unit end of run；
Second maximum voltage difference judging unit：Whether judge the difference of maxima and minima in n section magnitude of voltage in parallel
More than Δ U, and judged result be when restart the second maximum voltage difference judging unit, judged result for no when start
Stop selective charge instruction forwarding step；
Stop selective charge instruction forwarding step：Corresponding to three and interlink and interlink balancing unit 3-1 sends
Stop charging instruction；And start identification unit after this unit end of run；
Identification unit：Calculate capacity and the internal resistance of super capacitor；And start identification result after this unit end of run
Transmitting element；
Identification result transmitting element：Calculated for identification unit and interlink capacity and internal resistance are sent to master controller 1；
And start temperature conditioning unit after this unit end of run；
Temperature conditioning unit：The temperature controlling energy-storage units is within the temperature range of its normal work；And run knot in this unit
Start overall charging instruction judging unit after bundle.
The software flow of Balance route processor 3-4 is as shown in figure 8, Balance route interrupting submodule is carried out and interlink first
The reading of voltage.The section magnitude of voltage in parallel reading every time is stored, and covers the last economize on electricity pressure in parallel reading
Value, only stores the last section magnitude of voltage in parallel reading.The voltage signal reading is carried out simultaneously after digital filtering
Interlink voltage sorts from high to low.Then judge whether master controller 1 sends energy-storage units entirety charging instruction, if there are entirety
Charging instruction, then all into this energy-storage units and interlink balancing unit 3-1 transmission charging instruction, until overall charging instruction is removed
Pin.Without overall charging instruction, then carry out the electric voltage equalization within energy-storage units, judge that highest economize on electricity in parallel is pressed and minimum
Whether the difference of parallel connection economize on electricity pressure exceedes Δ U, if it exceeds Δ U, then gives 3 and the transmission of interlink balancing unit that magnitude of voltage is low
Charging instruction, until internal balance terminates, if the difference of highest economize on electricity in parallel pressure and minimum economize on electricity pressure in parallel is not above Δ
U, then exit energy-storage units internal balance.In present embodiment, Δ U takes 25mV.Then carry out and interlink super capacitor capacity and
The identification of internal resistance, and identification result is sent to master controller 1.Finally read the temperature of energy-storage units and judge whether overtemperature,
If overtemperature, start cooling system, i.e. blower fan 3-8.
Specific embodiment six：In conjunction with Fig. 9, present embodiment is described, present embodiment is to super described in embodiment five
The restriction further of level condenser voltage balancer, in present embodiment, described temperature conditioning unit is included with lower unit：
Temperature signal reading unit：Read the temperature value that simultaneously storage temperature signal processing circuit 3-5 is sent；And in this unit
Start-up temperature judging unit after end of run；
First temperature judging unit：Judge whether described temperature value is higher than T0, and be to start wind when being in judged result
Machine start unit, judged result for no when stop Balance route interrupting submodule operation；
Described Δ U and T0It is pre-set value, T0It is capable of the temperature upper limit of normal work for energy-storage units；
Blower fan start unit：Send enabled instruction to blower fan 3-8；And start second temperature after this unit end of run
Judging unit；
Second temperature judging unit：Judge whether described temperature value is higher than T0, and again open when judged result is and is
Dynamic second temperature judging unit, judged result for no when start blower fan stop element；
Blower fan stop element：Send instruction out of service to blower fan 3-8, and terminate to equalize after this unit end of run
Control the operation of interrupting submodule.
Specific embodiment seven：In conjunction with Figure 10 to Figure 12, present embodiment is described, present embodiment is to embodiment five
The restriction further of described ultracapacitor voltage balancer, in present embodiment, described identification unit includes following
Unit：
Super capacitor terminal voltage and input current reading unit：Constantly read and store the super electricity that master controller 1 is sent
The terminal voltage held and input current；And start terminal voltage and input current average value calculating list after this unit end of run
Unit；
Terminal voltage and input current average value computing unit：Calculate up-to-date average voltage u3And up-to-date input current
Meansigma methodss i3, u3For the meansigma methodss of the terminal voltage of the super capacitor of nearest p time reading, i3Super capacitor for nearest p time reading
The meansigma methodss of input current；P is the integer more than or equal to 3；And after this unit end of run start-up capacitance and internal resistance meter
Calculate unit；
Electric capacity and internal resistance computing unit：Calculate the electric capacity C and internal resistance r of super capacitor according to the following equation；And in this unit
Start result of calculation judging unit after end of run；
u2For the meansigma methodss of the terminal voltage of the second recently super capacitor to+1 reading of pth, i2For recently for the second time extremely
The meansigma methodss of the input current of super capacitor of+1 reading of pth；
u1For the meansigma methodss of the terminal voltage of the super capacitor to+2 readings of pth for the nearest third time, i1For nearest third time extremely
The meansigma methodss of the input current of super capacitor of+2 readings of pth；
Result of calculation judging unit：Whether the value judging calculated C and r is within the scope of correct, and judging knot
Fruit is to start result of calculation transmitting element when being；Judged result for no when start-up capacitance and internal resistance updating block；
Result of calculation transmitting element：The value of calculated C and r is sent to master controller 1；And run knot in this unit
Start-up capacitance and internal resistance updating block after bundle；
Electric capacity and internal resistance updating block：u1=u2,i1=i2,u2=u3,i2=i3；And tie after this unit end of run
Bundle identification unit end of run.
The capacity of online real-time identification super capacitor and internal resistance have weight for super capacitor life estimation and fault detect
Want meaning, the method that present embodiment is taken is by obtaining to continuous 3 groups of average voltages and calculating of average current value, making
Super capacitor the equivalent capacity of interlink and equivalent series resistance, principle such as Figure 10 and Figure 11 institute can be calculated in this way
Show.In Figure 10, u is the terminal voltage of super capacitor, and i is the input current of super capacitor, and r is the internal resistance of super capacitor, and C is super
The capacitance of electric capacity, before subscript 1 and 2 representative not in the same time, T1For i1The corresponding moment, T2For i2The corresponding moment.
Understand that voltage and current in the same time does not have following relation by Figure 10 and Figure 11：
Wherein,Can be with a top, below respectively i1、i2, highly for △ T=T2-T1Ladder approximation table
Show, take not three groups of data in the same time can obtain：
Then the identification formula that super capacitor capacity and internal resistance can be obtained is arranged by (2) formula：
The algorithm flow of super capacitor capacity and internal resistance identification as shown in figure 12, saves continuous the 5 of voltage and current in parallel
Secondary sampling carries out average filter, and the result drawing is as up-to-date magnitude of voltage u3With current value i3, substitute in formula (3) and counted
Calculate, result of calculation is judged, if calculating correct, updating the value of capacitance and internal resistance and uploading meter to master controller 1
Calculate result；If incorrect, give up this result of calculation.Update mode is to give up u1And i1, by u2And i2Value be assigned to u respectively1
And i1, by u3And i3Value be assigned to u respectively2And i2, then terminate the operation of identification unit.Result of calculation judges in step, can root
The meansigma methodss of front multiple result of calculation to be determining correct scope accordingly, for example, take multiple result of calculation meansigma methodss upper and lower
10% is correct scope.
Specific embodiment eight：In conjunction with Figure 13, present embodiment is described, present embodiment is to described in embodiment one
The restriction further of ultracapacitor voltage balancer, in present embodiment, described DC-DC power module 4 is used for as whole
Individual voltage balancing device provides energy.Its index request is：Disclosure satisfy that and a quarter of interlink sum interlink balance
The power demand that unit 3-1 charges simultaneously.
All and interlink balancing unit 3-1 a quarter is pressed 120 tunnels and is calculated, and every road peak power is 50W, then DC-DC
The rated power of power conversion is 120 × 50W=6kW.The principle of DC-DC power module 4 is as shown in figure 13, in order to improve conversion
Efficiency, reduces harmonic wave interference, using LLC resonant half-bridge converter structure, can be in full voltage range, make under full load condition
Obtain primary side MOSFET and realize ZVS (ZVT), ZCS (Zero Current Switch) realized by secondary commutation diode, reduces out
Close loss, substantially increase efficiency.And in input voltage and loading range change ratio in the case of larger, its switching frequency becomes
Change less, be conducive to the design of principal parameter.In present embodiment, the efficiency of DC-DC power module 4 is 94%, and interlink balance
The efficiency of unit 3-1 is 90%, and balanced pressure system aggregate efficiency is 85%.
Specific embodiment nine：Present embodiment is to the ultracapacitor voltage balancer described in embodiment one
Limit further, in present embodiment, described ultracapacitor voltage balancer also includes display device, this display device
It is connected with master controller 1.
Display device adopts touch screen to realize, for carrying out function selecting and arrange parameter etc..
Specific embodiment ten：In conjunction with Fig. 8, present embodiment is described, present embodiment is super described in embodiment two
The control method of condenser voltage balancer, the method comprises the following steps：
Economize on electricity pressure read step in parallel：Constantly read and store the n economize on electricity in parallel that m simulation switching circuit 3-2 is sent
Pressure value；And execute economize on electricity pressure sequence step in parallel after this step terminates；
Economize on electricity pressure sequence step in parallel：Described n section magnitude of voltage in parallel is ranked up according to by high order on earth；
And execute overall charging instruction after this step terminates and judge step；
Overall charging instruction judges step：Judge whether to receive the overall charging instruction that master controller 1 is sent, and sentencing
Disconnected result is execution overall charging instruction forwarding step when being, judged result for no when execute the first maximum voltage difference and judge step
Suddenly；
Overall charging instruction forwarding step：Send charging instruction to individual simultaneously interlink balancing unit 3-1 of n；And in this step knot
Execute overall charging END instruction after bundle and judge step；
Overall charging END instruction judges step：Judge whether to receive the entirety charging END instruction that master controller 1 is sent,
And stop overall charging instruction forwarding step in judged result for execution when being；Judged result for no when re-execute overall filling
Electric END instruction judges step；
Stop overall charging instruction forwarding step：Send to individual simultaneously interlink balancing unit 3-1 of n and stop charging instruction；And
This step executes the first maximum voltage difference after terminating and judges step；
First maximum voltage difference judges step：Whether judge the difference of maxima and minima in n section magnitude of voltage in parallel
More than Δ U, and judged result be when execution selective charge instruction forwarding step, judged result for no when execute identification
Step；
Selective charge instructs forwarding step：To magnitude of voltage minimum three and corresponding to interlink and interlink balancing unit
3-1 sends charging instruction；And execute the second maximum voltage difference after this step terminates and judge step；
Second maximum voltage difference judges step：Whether judge the difference of maxima and minima in n section magnitude of voltage in parallel
More than Δ U, and re-execute the second maximum voltage difference and judge step when judged result is and is, judged result for no when execute
Stop selective charge instruction forwarding step；
Stop selective charge instruction forwarding step：Corresponding to three and interlink and interlink balancing unit 3-1 sends
Stop charging instruction；And execute identification step after this step terminates；
Identification step：Calculate capacity and the internal resistance of super capacitor；And execute identification result transmission after this step terminates
Step；
Identification result forwarding step：To recognize that step is calculated and interlink capacity and internal resistance send to master controller 1；
And execute temperature control step after this step terminates；
Temperature control step：The temperature controlling energy-storage units is within the temperature range of its normal work；And terminate in this step row
Return the overall charging instruction of execution afterwards and judge step.
In present embodiment, when overall charging instruction sent by master controller 1, Balance route processor 3-4 controls and it
The all and interlink being connected carries out overall charging.When not carrying out overall charging, Balance route processor 3-4 can monitor respectively simultaneously
The voltage of interlink, when the maximum of each economize on electricity pressure reduction in parallel exceedes pre-set a certain numerical value, starts relatively low to voltage
3 and interlink charge, to balance the voltage of each and interlink, until the maximum of each economize on electricity pressure reduction in parallel be less than pre-set
Numerical value.In addition it is also necessary to constantly detection temperature in charging process, when temperature is too high, Balance route processor 3-4 controls wind
Machine is started working, and is lowered the temperature, until temperature drops in the range of normal working temperature.Additionally, Balance route processor 3-4 also needs
The capacitance of super capacitor to be calculated and internal resistance, and result of calculation is sent to master controller 1 to be shown in real time.
Specific embodiment 11：In conjunction with Fig. 9, present embodiment is described, present embodiment is to described in embodiment ten
The restriction further of the control method of ultracapacitor voltage balancer, in present embodiment, described temperature control step includes
Following steps：
Temperature signal read step：Read the temperature value that simultaneously storage temperature signal processing circuit 3-5 is sent；And in this step
Execute the first temperature after end and judge step；
First temperature judges step：Judge whether described temperature value is higher than T0, and be to execute wind when being in judged result
Machine starting step, judged result for no when terminate temperature control step；
Described Δ U and T0It is pre-set value, T0It is capable of in the temperature of normal work for energy-storage units step
Limit；
Blower fan starting step：Send enabled instruction to blower fan 3-8；And execute second temperature after this step end of run
Judge step；
Second temperature judges step：Judge whether described temperature value is higher than T0, and be to execute wind when being in judged result
Machine stop step, judged result for no when return execution second temperature judge step；
Blower fan stops step：Send instruction out of service to blower fan 3-8；And terminate temperature control after this step end of run
Step.
Specific embodiment 12：In conjunction with Figure 10 to 12, present embodiment is described, present embodiment is to embodiment ten
The restriction further of the described control method of ultracapacitor voltage balancer, in present embodiment, described identification walks
Suddenly comprise the following steps：
Super capacitor terminal voltage and input current read step：Constantly read and store the super electricity that master controller 1 is sent
The terminal voltage held and input current；And execute terminal voltage and input current average value calculation procedure after this step terminates；
Terminal voltage and input current average value calculation procedure：Calculate up-to-date average voltage u3And up-to-date input current
Meansigma methodss i3, u3For the meansigma methodss of the terminal voltage of the super capacitor of nearest p time reading, i3Super capacitor for nearest p time reading
The meansigma methodss of input current；P is the integer more than or equal to 3；And execute electric capacity and internal resistance calculating step after this step terminates
Suddenly；
Electric capacity and internal resistance calculation procedure：Calculate the electric capacity C and internal resistance r of super capacitor according to the following equation；And in this step
After end, execution result of calculation judges step；
u2For the meansigma methodss of the terminal voltage of the second recently super capacitor to+1 reading of pth, i2For recently for the second time extremely
The meansigma methodss of the input current of super capacitor of+1 reading of pth；
u1For the meansigma methodss of the terminal voltage of the super capacitor to+2 readings of pth for the nearest third time, i1For nearest third time extremely
The meansigma methodss of the input current of super capacitor of+2 readings of pth；
Result of calculation judges step：Whether the value judging calculated C and r is within the scope of correct, and judging knot
Fruit is to execute result of calculation forwarding step when being；Judged result for no when execution electric capacity and internal resistance update step；
Result of calculation forwarding step：The value of calculated C and r is sent to master controller 1；And terminate it in this step
Execution electric capacity and internal resistance update step afterwards；
Electric capacity and internal resistance update step：u1=u2,i1=i2,u2=u3,i2=i3, so far, identification step terminates.
Identification steps flow chart is as shown in figure 12.Online real-time identification section in parallel capacitance and internal resistance are for the super capacitor longevity
Life is estimated and fault detect is significant, and the method that present embodiment is taken is by continuous 3 groups of average voltages peace
The calculating of all current values obtains, and makes to calculate super capacitor the equivalent capacity of interlink and equivalent series in this way
Resistance, principle is as shown in Figure 10 and Figure 11.In Figure 10, u is the terminal voltage of super capacitor, and i is the input current of super capacitor, and r is
The internal resistance of super capacitor, C is the capacitance of super capacitor, before subscript 1 and 2 representative not in the same time, T1For i1The corresponding moment,
T2For i2The corresponding moment.Result of calculation judges in step, can determine correct model according to the meansigma methodss of multiple result of calculation before this
Enclose, for example, take multiple result of calculation meansigma methodss up and down 10% be correct scope.
Claims (7)
1. ultracapacitor voltage balancer it is characterised in that：It includes master controller (1), total current/voltage detection unit
(2), multiple balance controllers (3) and DC-DC power module (4)；
DC-DC power module (4) is master controller (1), total current/voltage detection unit (2) and multiple balance controller (3)
Working power is provided；
Master controller (1) connects described multiple balance controllers (3) and total current/voltage detection unit (2)；
Each balance controller (3) is used for measuring the n of ultracapacitor and the terminal voltage of interlink be described n and interlink fills
Electricity；
Total current/voltage detection unit (2) is used for detecting total voltage and the total current of ultracapacitor output port；
Described balance controller (3) includes n and interlink balancing unit (3-1), m simulation switching circuit (3-2), AD process
Circuit (3-3), Balance route processor (3-4), processes temperature signal circuit (3-5), light-coupled isolation communicating circuit (3-6) and every
From power supply, m is less than n；
It is one that each and interlink balancing unit (3-1) are used for and interlink charges, and the control signal of interlink balancing unit (3-1)
Input connects the charging control signal outfan of Balance route processor (3-4)；
Each simulation switching circuit (3-2) is used for measuring multiple and interlink terminal voltage, and m simulation switching circuit (3-2) is surveyed altogether
Amount n the terminal voltage of interlink, and measurement result is sent to Balance route processor (3-4) by AD process circuit (3-3)；
The outfan of processes temperature signal circuit (3-5) connects the temperature signal input of Balance route processor (3-4), temperature
The input of signal processing circuit (3-5) is used for connecting temperature sensor (3-7)；
Temperature sensor (3-7) is used for measuring the temperature of energy-storage units, and measurement result is passed through processes temperature signal circuit (3-
5) send to Balance route processor (3-4), described energy-storage units include balance controller (3) and with this balance controller (3)
The simultaneously interlink being connected；
Balance route processor (3-4) refrigeration control signal output part is used for the control signal input of connecting fan (3-8)；
Balance route processor (3-4) is carried out data transmission with master controller (1) by CAN signal transmission line；
Described Balance route processor (3-4) is embedded in the Balance route interrupting submodule realized by software, and this module includes
With lower unit：
Economize on electricity pressure reading unit in parallel：Constantly read and store the n economize on electricity pressure in parallel that m simulation switching circuit (3-2) is sent
Value；And start economize on electricity pressure sequencing unit in parallel after this unit end of run；
Economize on electricity pressure sequencing unit in parallel：Described n section magnitude of voltage in parallel is ranked up according to by high order on earth；And
Start overall charging instruction judging unit after this unit end of run；
Overall charging instruction judging unit：Judge whether to receive the overall charging instruction that master controller (1) is sent, and judging
Result is to start overall charging instruction transmitting element when being, judged result for no when start the first maximum voltage difference judge single
Unit；
Overall charging instruction transmitting element：Send charging instruction to the individual simultaneously interlink balancing unit (3-1) of n；And run in this unit
Start overall charging END instruction judging unit after end；
Overall charging END instruction judging unit：Judge whether to receive the entirety charging END instruction that master controller (1) is sent, and
It is to start when being to stop overall charging instruction transmitting element in judged result；Judged result for no when restart overall charging
END instruction judging unit；
Stop overall charging instruction transmitting element：Send to the individual simultaneously interlink balancing unit (3-1) of n and stop charging instruction；And at this
Start the first maximum voltage difference judging unit after unit end of run；
First maximum voltage difference judging unit：Judge whether the difference of the maxima and minima in n section magnitude of voltage in parallel is more than
Δ U, and be to start selective charge instruction sending unit when being in judged result, judged result for no when to start identification single
Unit；
Selective charge instruction sending unit：To magnitude of voltage minimum three and corresponding to interlink and interlink balancing unit (3-
1) send charging instruction；And start the second maximum voltage difference judging unit after this unit end of run；
Second maximum voltage difference judging unit：Judge whether the difference of the maxima and minima in n section magnitude of voltage in parallel is more than
Δ U, and judged result be when restart the second maximum voltage difference judging unit, judged result for no when start stop
Selective charge instruction sending unit；Described Δ U is pre-set value；
Stop selective charge instruction sending unit：Corresponding to three and interlink and interlink balancing unit (3-1) sends stops
Only charging instruction；And start identification unit after this unit end of run；
Identification unit：Calculate capacity and the internal resistance of super capacitor；And start identification result transmission after this unit end of run
Unit；
Identification result transmitting element：Calculated for identification unit and interlink capacity and internal resistance are sent to master controller (1)；And
Start temperature conditioning unit after this unit end of run；
Temperature conditioning unit：The temperature controlling energy-storage units is within the temperature range of its normal work；And this unit end of run it
Start overall charging instruction judging unit afterwards.
2. ultracapacitor voltage balancer according to claim 1 it is characterised in that：Described AD process circuit
(3-3) analog processing circuit (3-3-1), analog-to-digital converting module (3-3-2) and digital isolation module (3-3-3) are included；
M signal input part of analog processing circuit (3-3-1) connects the signal output of m simulation switching circuit (3-2) respectively
End, the signal output part of analog processing circuit (3-3-1) connects the analogue signal input of analog-to-digital converting module (3-3-2)
End, the digital signal output end of analog-to-digital converting module (3-3-2) passes through digital isolation module (3-3-3) and connects equilibrium control
The section voltage signal inputs in parallel of processor (3-4) processed, the channel selecting control signal output of digital isolation module (3-3-3)
End connects the channel selecting control signal input of m simulation switching circuit (3-2).
3. ultracapacitor voltage balancer according to claim 1 it is characterised in that：Described temperature conditioning unit includes
With lower unit：
Temperature signal reading unit：Read the temperature value that simultaneously storage temperature signal processing circuit (3-5) is sent；And in this unit fortune
Row starts the first temperature judging unit after terminating；
First temperature judging unit：Judge whether described temperature value is higher than T0, and be to start blower fan when being to start in judged result
Unit, judged result for no when stop Balance route interrupting submodule operation；
Described Δ U and T0It is pre-set value, T0It is capable of the temperature upper limit of normal work for energy-storage units；
Blower fan start unit：Send enabled instruction to blower fan (3-8)；And startup second temperature is sentenced after this unit end of run
Disconnected unit；
Second temperature judging unit：Judge whether described temperature value is higher than T0, and restart second when judged result is and is
Temperature judging unit, judged result for no when start blower fan stop element；
Blower fan stop element：Send instruction out of service to blower fan (3-8), and terminate equilibrium control after this unit end of run
The operation of interrupting submodule processed.
4. ultracapacitor voltage balancer according to claim 1 it is characterised in that：Described identification unit includes
With lower unit：
Super capacitor terminal voltage and input current reading unit：Constantly read and store the super capacitor that master controller (1) is sent
Terminal voltage and input current；And start terminal voltage and input current average value computing unit after this unit end of run；
Terminal voltage and input current average value computing unit：Calculate up-to-date average voltage u3And up-to-date input current is average
Value i3, u3For the meansigma methodss of the terminal voltage of the super capacitor of nearest p time reading, i3Input for the super capacitor of nearest p time reading
The meansigma methodss of electric current；P is the integer more than or equal to 3；And start-up capacitance and internal resistance calculate list after this unit end of run
Unit；
Electric capacity and internal resistance computing unit：Calculate the electric capacity C and internal resistance r of super capacitor according to the following equation；And run in this unit
Start result of calculation judging unit after end；
u2For the meansigma methodss of the terminal voltage of the second recently super capacitor to+1 reading of pth, i2For second recently to pth+
The meansigma methodss of the input current of super capacitor of 1 reading；
u1For the meansigma methodss of the terminal voltage of the super capacitor to+2 readings of pth for the nearest third time, i1For nearest third time to pth+
The meansigma methodss of the input current of super capacitor of 2 readings；
△ T=T2-T1, T1For i1The corresponding moment, T2For i2The corresponding moment；
Result of calculation judging unit：Whether the value judging calculated C and r is within the scope of correct, and in judged result is
Start result of calculation transmitting element when being；Judged result for no when start-up capacitance and internal resistance updating block；
Result of calculation transmitting element：The value of calculated C and r is sent to master controller (1)；And in this unit end of run
Start-up capacitance and internal resistance updating block afterwards；
Electric capacity and internal resistance updating block：u1=u2,i1=i2,u2=u3,i2=i3；And terminate to distinguish after this unit end of run
Know unit end of run.
5. the ultracapacitor voltage balancer described in claim 1 control method it is characterised in that：The method include with
Lower step：
Economize on electricity pressure read step in parallel：Constantly read and store the n economize on electricity pressure in parallel that m simulation switching circuit (3-2) is sent
Value；And execute economize on electricity pressure sequence step in parallel after this step terminates；
Economize on electricity pressure sequence step in parallel：Described n section magnitude of voltage in parallel is ranked up according to by high order on earth；And
This step executes overall charging instruction after terminating and judges step；
Overall charging instruction judges step：Judge whether to receive the overall charging instruction that master controller (1) is sent, and judging
Result is execution overall charging instruction forwarding step when being, judged result for no when execute the first maximum voltage difference and judge step
Suddenly；
Overall charging instruction forwarding step：Send charging instruction to the individual simultaneously interlink balancing unit (3-1) of n；And terminate in this step
Execute overall charging END instruction afterwards and judge step；
Overall charging END instruction judges step：Judge whether to receive the entirety charging END instruction that master controller (1) is sent, and
It is that when being, execution stops overall charging instruction forwarding step in judged result；Judged result for no when re-execute overall charging
END instruction judges step；
Stop overall charging instruction forwarding step：Send to the individual simultaneously interlink balancing unit (3-1) of n and stop charging instruction；And at this
Step executes the first maximum voltage difference after terminating and judges step；
First maximum voltage difference judges step：Judge whether the difference of the maxima and minima in n section magnitude of voltage in parallel is more than
Δ U, and judged result be when execution selective charge instruction forwarding step, judged result for no when execution identification step
Suddenly；
Selective charge instructs forwarding step：To magnitude of voltage minimum three and corresponding to interlink and interlink balancing unit (3-
1) send charging instruction；And execute the second maximum voltage difference after this step terminates and judge step；
Second maximum voltage difference judges step：Judge whether the difference of the maxima and minima in n section magnitude of voltage in parallel is more than
Δ U, and re-execute the second maximum voltage difference and judge step when judged result is and is, judged result for no when execute stopping
Selective charge instructs forwarding step；
Stop selective charge instruction forwarding step：Corresponding to three and interlink and interlink balancing unit (3-1) sends stops
Only charging instruction；And execute identification step after this step terminates；
Identification step：Calculate capacity and the internal resistance of super capacitor；And execute identification result forwarding step after this step terminates；
Identification result forwarding step：To recognize that step is calculated and interlink capacity and internal resistance send to master controller (1)；And
Temperature control step is executed after this step terminates；
Temperature control step：The temperature controlling energy-storage units is within the temperature range of its normal work；And after this step row terminates
Return the overall charging instruction of execution and judge step.
6. ultracapacitor voltage balancer according to claim 5 control method it is characterised in that：Described temperature
Control step comprises the following steps：
Temperature signal read step：Read the temperature value that simultaneously storage temperature signal processing circuit (3-5) is sent；And in this step knot
Execute the first temperature after bundle and judge step；
First temperature judges step：Judge whether described temperature value is higher than T0, and be that when being, execution blower fan starts in judged result
Step, judged result for no when terminate temperature control step；
Described Δ U and T0It is pre-set value, T0It is capable of the temperature upper limit of normal work for energy-storage units；
Blower fan starting step：Send enabled instruction to blower fan (3-8)；And execution second temperature is sentenced after this step end of run
Disconnected step；
Second temperature judges step：Judge whether described temperature value is higher than T0, and be that when being, execution blower fan stops in judged result
Step, judged result for no when return execution second temperature judge step；
Blower fan stops step：Send instruction out of service to blower fan (3-8)；And terminate temperature control step after this step end of run
Suddenly.
7. ultracapacitor voltage balancer according to claim 5 control method it is characterised in that：Described distinguishes
Know step to comprise the following steps：
Super capacitor terminal voltage and input current read step：Constantly read and store the super capacitor that master controller (1) is sent
Terminal voltage and input current；And execute terminal voltage and input current average value calculation procedure after this step terminates；
Terminal voltage and input current average value calculation procedure：Calculate up-to-date average voltage u3And up-to-date input current is average
Value i3, u3For the meansigma methodss of the terminal voltage of the super capacitor of nearest p time reading, i3Input for the super capacitor of nearest p time reading
The meansigma methodss of electric current；P is the integer more than or equal to 3；And execute electric capacity and internal resistance calculation procedure after this step terminates；
Electric capacity and internal resistance calculation procedure：Calculate the electric capacity C and internal resistance r of super capacitor according to the following equation；And terminate in this step
Execution result of calculation judges step afterwards；
u2For the meansigma methodss of the terminal voltage of the second recently super capacitor to+1 reading of pth, i2For second recently to pth+
The meansigma methodss of the input current of super capacitor of 1 reading；
u1For the meansigma methodss of the terminal voltage of the super capacitor to+2 readings of pth for the nearest third time, i1For nearest third time to pth+
The meansigma methodss of the input current of super capacitor of 2 readings；
△ T=T2-T1, T1For i1In the corresponding moment, T2 is the i2 corresponding moment；
Result of calculation judges step：Whether the value judging calculated C and r is within the scope of correct, and in judged result is
Result of calculation forwarding step is executed when being；Judged result for no when execution electric capacity and internal resistance update step；
Result of calculation forwarding step：The value of calculated C and r is sent to master controller (1)；And after this step terminates
Execution electric capacity and internal resistance update step；
Electric capacity and internal resistance update step：u1=u2,i1=i2,u2=u3,i2=i3, so far, identification step terminates.
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| CN106127609B (en) * | 2016-06-30 | 2019-10-18 | 温州大学 | Parallel operation system module number controlling method |
| CN106160016B (en) * | 2016-06-30 | 2018-11-27 | 温州大学 | Based on efficiency and current sharing energy area and maximum parallel operation system module number controlling method |
| CN106094523B (en) * | 2016-06-30 | 2018-11-06 | 温州大学 | Based on efficiency and flow index area and maximum parallel operation system optimization method |
| CN106054614B (en) * | 2016-06-30 | 2018-11-06 | 温州大学 | Take into account the system ambiguous control method of parallel operation of efficiency and current sharing energy |
| CN106972561A (en) * | 2017-03-31 | 2017-07-21 | 广州电力机车有限公司 | A kind of electric transmission vehicle-mounted power management system |
| CN107861002A (en) * | 2017-11-03 | 2018-03-30 | 中国科学院电工研究所无锡分所 | A kind of super-capacitor voltage detecting system |
| CN107800292B (en) * | 2017-11-16 | 2019-08-23 | 哈尔滨工业大学 | Connect energy storage device equalizer circuit and balanced pressure system containing the circuit |
| US10637271B2 (en) * | 2018-09-30 | 2020-04-28 | AGIGA Tech | Adaptive charge voltage management for lithium ion and hybrid capacitors |
| CN111308177A (en) * | 2020-05-11 | 2020-06-19 | 广东志高暖通设备股份有限公司 | Super capacitor measuring circuit |
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