CN104425348B - A kind of manufacture method of semiconductor devices - Google Patents
A kind of manufacture method of semiconductor devices Download PDFInfo
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- CN104425348B CN104425348B CN201310410802.5A CN201310410802A CN104425348B CN 104425348 B CN104425348 B CN 104425348B CN 201310410802 A CN201310410802 A CN 201310410802A CN 104425348 B CN104425348 B CN 104425348B
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- semiconductor substrate
- fleet plough
- plough groove
- groove isolation
- isolation structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
- H01L21/76229—Concurrent filling of a plurality of trenches having a different trench shape or dimension, e.g. rectangular and V-shaped trenches, wide and narrow trenches, shallow and deep trenches
Abstract
The present invention provides a kind of manufacture method of semiconductor devices, including：Semiconductor substrate is provided, the hard mask layer of the pattern with multiple fleet plough groove isolation structures is formed on the semiconductor substrate；The multiple fleet plough groove isolation structure is formed in the Semiconductor substrate；Implement dry etching and wet etching removes the part that the multiple fleet plough groove isolation structure is higher by the Semiconductor substrate；Remove the hard mask layer.According to the present invention, implement dry etching and wet etching and remove the part that the multiple fleet plough groove isolation structure is higher by the Semiconductor substrate, the height of the fleet plough groove isolation structure of different zones being located in the Semiconductor substrate after the removal can be made consistent.
Description
Technical field
The present invention relates to semiconductor fabrication process, shallow trench isolation is formed in particular to one kind（STI）The side of structure
Method.
Background technology
In semiconductor fabrication process, the performance of the fleet plough groove isolation structure formed is for the semiconductor device that eventually forms
It is most important for the electric property of part.With the continuous reduction of feature sizes of semiconductor devices, in order to ensure being served as a contrast in semiconductor
The zero-clearance filling for the oxide for constituting fleet plough groove isolation structure is realized in the groove formed in bottom, generally implements Multiple depositions technique
Complete the filling of the oxide.Due to restricting for the characteristic size by the groove, cause in the Multiple depositions technique
The sedimentation rate deposited each time have differences, thus, carry out high annealing after, it is every in the Multiple depositions technique
The compactness extent for the oxide that primary depositing is formed has differences., it is necessary to remove shallow after fleet plough groove isolation structure is formed
Groove isolation construction is higher by the part of Semiconductor substrate, and the fleet plough groove isolation structure is generally completed using wet etching is higher by
The removal of the part of Semiconductor substrate, such as corrosive liquid are the hydrofluoric acid of dilution（DHF）Wet etching.Due to constituting shallow trench
The compactness extent of the multilevel oxide of isolation structure has differences, and causes etching of the wet etching to the multilevel oxide
Speed has differences, thus, after the wet etching, positioned at the fleet plough groove isolation structure of the different zones of Semiconductor substrate
The removal effect for being higher by the part of Semiconductor substrate is different, and the complete removal having, some removals are most of, the small portion of some removals one
Point.
As shown in Figure 1A, after the wet etching, the larger area of device density is formed positioned at Semiconductor substrate 100
The height of the fleet plough groove isolation structure 101 in domain is less than forms the shallow of the less region of device density positioned at Semiconductor substrate 100
The height of groove isolation construction 102.The reason for causing this phenomenon is probably, in the formation device density of Semiconductor substrate 100
The characteristic size of the width for the fleet plough groove isolation structure 101 that larger region is formed is less than the shaper in Semiconductor substrate 100
The characteristic size of the width for the fleet plough groove isolation structure 102 that the less region of part density is formed, causes the Multiple depositions technique
The multilevel oxide of the composition fleet plough groove isolation structure 101 formed is compared to the multilayer oxidation for constituting fleet plough groove isolation structure 102
Thing has the difference of small compactness extent；In the wet etch process, relative to composition fleet plough groove isolation structure 102
Multilevel oxide, the corrosive liquid of the wet etching is to constituting the multilevel oxide of fleet plough groove isolation structure 101 with bigger
Etch-rate.
Relative to the wet etching, remove the fleet plough groove isolation structure according to dry etching and be higher by Semiconductor substrate
Part, then the shallow trench for forming the larger region of device density positioned at Semiconductor substrate 100 caused by above-mentioned reason every
Being formed between the fleet plough groove isolation structure 102 in the less region of device density from structure 101 and positioned at Semiconductor substrate 100
Difference in height will be obviously reduced.But, as shown in Figure 1B, after the dry etching, positioned at the formation of Semiconductor substrate 100
The height of the fleet plough groove isolation structure 101 in the larger region of device density is slightly higher than the shaper positioned at Semiconductor substrate 100
The height of the fleet plough groove isolation structure 102 in the less region of part density.
It is inconsistent due to forming height in the fleet plough groove isolation structure of the different zones of Semiconductor substrate, cause subsequently to exist
Formed in Semiconductor substrate after gate dielectric and gate material layers, the grid being made up of gate dielectric and gate material layers
The height of structure is also inconsistent, in turn results in the difference to be formed in the electric property of the device of the different zones of Semiconductor substrate.
It is, therefore, desirable to provide a kind of method, to solve the above problems.
The content of the invention
In view of the shortcomings of the prior art, the present invention provides a kind of manufacture method of semiconductor devices, including：Semiconductor is provided
Substrate, forms the hard mask layer of the pattern with multiple fleet plough groove isolation structures on the semiconductor substrate；Partly led described
The multiple fleet plough groove isolation structure is formed in body substrate；Implement dry etching and wet etching remove the multiple shallow trench every
From the part that structure is higher by the Semiconductor substrate；Remove the hard mask layer.
Further, having for the Semiconductor substrate is formed in the multiple fleet plough groove isolation structure and is differently formed device
The Partial Height in the region of density is identical and width is different, and the semiconductor lining is formed in the multiple fleet plough groove isolation structure
The Partial Height in the region with same formation device density at bottom is identical and width is identical.
Further, the hard mask layer is silicon nitride layer.
Further, the step of forming the multiple fleet plough groove isolation structure includes：Using the hard mask layer as mask, in institute
State the groove etched in Semiconductor substrate for forming the multiple fleet plough groove isolation structure；It is in the trench and described hard
Depositing isolation material on mask layer；Chemical mechanical milling tech is performed to grind the isolated material, described is covered firmly until exposing
Film layer.
Further, the isolated material is oxide.
Further, the deposition is completed several times, and the isolated material deposited every time is identical.
Further, after the deposition and the grinding, annealing is implemented respectively.
Further, the etching gas of the dry etching is to include NF3And NH3Mixture or include H2And NF3It is mixed
Compound, the corrosive liquid of the wet etching is the hydrofluoric acid of dilution.
Further, the implementation process of the dry etching comprises the steps：By the etching gas in peripheral radio frequency
It is converted under effect comprising F ion, HF ions and NH4The plasma of ion；The plasma is imported and has placed described
The etching cavity of Semiconductor substrate, at 25-30 DEG C, the plasma with constitute the multiple fleet plough groove isolation structure every
Reacted from material and generate volatile complex compound；The temperature of the Semiconductor substrate is brought up to more than 100 DEG C, made described
Complex compound volatilization is discharged from the etching cavity.
Further, the pressure of the dry etching is 2-3Torr, and the power of the radio frequency is 15-50W.
Further, the removal of the hard mask layer is implemented using wet-etching technology.
Further, after the removal of the hard mask layer, in addition to the Semiconductor substrate and the multiple shallow ridges
The step of recess isolating structure implements wet-cleaning.
Further, after the wet-cleaning, the step of forming grid structure in the Semiconductor substrate is additionally included in,
The grid structure includes gate dielectric, gate material layers and the grid hard masking layer stacked gradually from bottom to top
According to the present invention, implement dry etching and wet etching removes the multiple fleet plough groove isolation structure and is higher by described in half
The part of conductor substrate, can make the shallow trench isolation of the different zones being located in the Semiconductor substrate after the removal
The height of structure is consistent.
Brief description of the drawings
The drawings below of the present invention is used to understand the present invention in this as the part of the present invention.Shown in the drawings of this hair
Bright embodiment and its description, for explaining the principle of the present invention.
In accompanying drawing：
Figure 1A is to remove fleet plough groove isolation structure using wet etching when forming fleet plough groove isolation structure to be higher by semiconductor
There is inconsistent signal in the height formed behind the part of substrate in the fleet plough groove isolation structure of the different zones of Semiconductor substrate
Property profile；
Figure 1B is to remove fleet plough groove isolation structure using dry etching when forming fleet plough groove isolation structure to be higher by semiconductor
There is inconsistent signal in the height formed behind the part of substrate in the fleet plough groove isolation structure of the different zones of Semiconductor substrate
Property profile；
Fig. 2A-Fig. 2 C are the device that is obtained respectively the step of implementation successively according to the method for exemplary embodiment of the present
Schematic cross sectional view；
Fig. 3 is the flow chart that fleet plough groove isolation structure is formed according to the method for exemplary embodiment of the present.
Embodiment
In the following description, a large amount of concrete details are given to provide more thorough understanding of the invention.So
And, it is obvious to the skilled person that the present invention can be able to without one or more of these details
Implement.In other examples, in order to avoid obscuring with the present invention, do not enter for some technical characteristics well known in the art
Row description.
In order to thoroughly understand the present invention, detailed step will be proposed in following description, to explain proposition of the present invention
Formation fleet plough groove isolation structure method.Obviously, execution of the invention is not limited to the technical staff institute of semiconductor applications
The specific details being familiar with.Presently preferred embodiments of the present invention is described in detail as follows, but in addition to these detailed descriptions, the present invention is also
There can be other embodiment.
It should be appreciated that when using term "comprising" and/or " comprising " in this manual, it is indicated in the presence of described
Feature, entirety, step, operation, element and/or component, but do not preclude the presence or addition of other one or more features, entirety,
Step, operation, element, component and/or combinations thereof.
[exemplary embodiment]
Below, reference picture 2A- Fig. 2 C and Fig. 3 come describe method according to an exemplary embodiment of the present invention formation shallow trench every
From the detailed step of structure.
Reference picture 2A- Fig. 2 C, illustrated therein is method according to an exemplary embodiment of the present invention and implement the step of institute successively
The schematic cross sectional view of the device obtained respectively.
First, as shown in Figure 2 A there is provided Semiconductor substrate 200, the constituent material of Semiconductor substrate 200, which can be used, not to be mixed
Miscellaneous monocrystalline silicon, the monocrystalline silicon doped with impurity, silicon-on-insulator（SOI）, be laminated silicon on insulator（SSOI）, insulator upper strata
Folded SiGe（S-SiGeOI）, germanium on insulator SiClx（SiGeOI）And germanium on insulator（GeOI）Deng.As an example, at this
In embodiment, the constituent material of Semiconductor substrate 200 selects monocrystalline silicon.
For Semiconductor substrate 200, the larger region of the device density that will be formed is formed with shallow trench isolation junction
Structure 201, the less region of device density that will be formed is formed with fleet plough groove isolation structure 202.Those skilled in the art should
Know, the region that will form device of Semiconductor substrate 200 is not limited to above-mentioned two region, herein to put it more simply, figure
What 2A illustrate only Semiconductor substrate 200 will form two different regions of device.Fleet plough groove isolation structure 201 and 202
It is synchronous formation, the characteristic size of the width of fleet plough groove isolation structure 201 is less than the spy of the width of fleet plough groove isolation structure 202
Levy size, the characteristic size of the height of fleet plough groove isolation structure 201 and the characteristic size phase of the height of fleet plough groove isolation structure 202
Together.Various traps (well) structure is also formed with Semiconductor substrate 200, to put it more simply, being omitted in diagram.
In the one exemplary embodiment of the present invention, the processing step bag of fleet plough groove isolation structure 201 and 202 is formed
Include：Hard mask layer 203, the various suitable techniques being familiar with using those skilled in the art are formed on semiconductor substrate 200
Technology formation hard mask layer 203, such as chemical vapor deposition method, the preferred silicon nitride of material of hard mask layer 203；Patterning is hard
Mask layer 203, to form the opening for the pattern for being constituted fleet plough groove isolation structure 201 and 202, the process in hard mask layer 203
Including：The photoresist layer of the pattern with fleet plough groove isolation structure 201 and 202 is formed on hard mask layer 203, with the photoetching
Glue-line is mask, and etching hard mask layer 203 is until expose Semiconductor substrate 200, using the cineration technics removal photoresist layer；
It is mask with the hard mask layer 203 of patterning, is etched in Semiconductor substrate 200 for forming fleet plough groove isolation structure 201
With 202 groove；Depositing isolation material in the trench and on hard mask layer 203, the isolated material is usually oxidation
Thing, preferably HARP；Chemical mechanical milling tech is performed to grind the isolated material, until exposing hard mask layer 203.Above-mentioned
During, in order to ensure realizing that the zero-clearance of isolated material is filled in the trench, the deposition of the isolated material is several times（It is logical
Chang Weisan times）Complete, the composition of the isolated material formed each time is identical.After said deposition, annealing is performed, with
The isolated material to be formed is densified, its mechanical strength is lifted.After the grinding, another annealing is performed, it is above-mentioned to repair
Damage of the process to Semiconductor substrate 200, improves the interface between fleet plough groove isolation structure 201 and 202 and Semiconductor substrate 200
Characteristic.
It should be noted that in above-mentioned one exemplary embodiment, being formed before hard mask layer 203, one layer can be initially formed
Oxide thin layer thing is as cushion, to discharge the stress between hard mask layer 203 and Semiconductor substrate 200；Depositing isolation material
Before, the side wall of the groove on hard mask layer 203 and for forming fleet plough groove isolation structure 201 and 202 and bottom are formed
Another oxide thin layer thing constitutes backing layer；To put it more simply, the cushion and backing layer are not shown.
Then, as shown in Figure 2 B, implement dry etching and wet etching removes fleet plough groove isolation structure 201 and 202 and is higher by
The part of Semiconductor substrate 200.
In the present embodiment, the etching gas of dry etching is to include NF3And NH3Mixture or include H2And NF3's
Mixture.The dry etching is different from conventional plasma dry etching, first, by above-mentioned etching gas penetrating in periphery
Frequency is converted into comprising F ion, HF ions and NH under acting on4The plasma of ion；Then, above-mentioned plasma is imported and put
The etching cavity of Semiconductor substrate 200 is put, in normal temperature（25-30℃）Under, above-mentioned plasma is with constituting fleet plough groove isolation structure
201 and 202 isolated material, which reacts, generates volatile complex compound；Then, the temperature of Semiconductor substrate 200 is brought up to
More than 100 DEG C, the complex compound volatilization is set to be discharged from etching cavity.The pressure of the dry etching is 2-3Torr（Millimeter mercury
Post）, the power of the radio frequency is 15-50W.It should be noted that under the action of radio of periphery, other can be converted into can be with
The etching gas for reacting the plasma of the volatile complex compound of generation with the isolated material each falls within the protection model of the present invention
Within enclosing.
In the present embodiment, the hydrofluoric acid that the corrosive liquid of wet etching preferably dilutes.It should be noted that the dry method erosion
Carve and the wet etching implementation in no particular order order.
Wet etching is used alone compared to existing process or dry etching removal fleet plough groove isolation structure 201 and 202 is high
Go out the part of Semiconductor substrate 200, the present invention implements the removal by the way of joint dry etching and wet etching, to structure
Into the difference very little of the etch-rate of the multilevel oxide of fleet plough groove isolation structure 201 and 202, therefore, described in Joint Implementation
After dry etching and the wet etching, the height of fleet plough groove isolation structure 201 and 202 is almost identical.
Then, as shown in Figure 2 C, hard mask layer 203 is removed.In the present embodiment, hard mask layer is implemented using wet etching
203 removal, the preferred hot phosphoric acid of corrosive liquid of the wet etching.Then, wet cleaning processes are implemented, to remove semiconductor lining
Bottom 200 and the residue on the surface of fleet plough groove isolation structure 201 and 202（Essentially from foregoing etching process）And impurity.It is described
The cleaning fluid of wet-cleaning is the hydrofluoric acid of dilution.
So far, the processing step that method according to an exemplary embodiment of the present invention is implemented is completed.Next, it is possible to implement
Conventional semiconductor devices front end fabrication process：
In an exemplary embodiment, first, grid structure is formed on semiconductor substrate 200, as an example, grid
Structure includes gate dielectric, gate material layers and the grid hard masking layer stacked gradually from bottom to top.
Specifically, the constituent material of gate dielectric includes oxide, such as silica（SiO2）.From SiO2As
During the constituent material of gate dielectric, pass through rapid thermal oxidation process（RTO）To form gate dielectric, its thickness is 8-50
Angstrom, but it is not limited thereto thickness.
The constituent material of gate material layers includes polysilicon, metal, conductive metal nitride, conductive metal oxide
With the one or more in metal silicide, wherein, metal can be tungsten（W）, nickel（Ni）Or titanium（Ti）；Conductive metal nitride
Thing includes titanium nitride（TiN）；Conductive metal oxide includes yttrium oxide（IrO2）；Metal silicide includes titanium silicide
（TiSi）.From polysilicon as gate material layers constituent material when, can select low-pressure chemical vapor phase deposition (LPCVD) technique
Gate material layers are formed, its process conditions includes：Reacting gas is silane (SiH4), its flow is 100~200sccm, preferably
150sccm；Temperature in reaction chamber is 700~750 DEG C；Pressure in reaction chamber is 250~350mTorr, preferably
300mTorr；The reacting gas can also include buffer gas, and the buffer gas is helium (He) or nitrogen（N2）, it flows
Measure as 5~20 liters/min (slm), preferably 8slm, 10slm or 15slm.
The constituent material of grid hard masking layer include oxide, nitride, nitrogen oxides and amorphous carbon in one kind or
It is a variety of, wherein, oxide includes boron-phosphorosilicate glass（BPSG）, phosphorosilicate glass（PSG）, tetraethyl orthosilicate（TEOS）, undoped silicon
Glass（USG）, spin-coating glass（SOG）, high-density plasma（HDP）Or spin-on dielectric（SOD）；Nitride includes silicon nitride
（SiN）；Nitrogen oxides includes silicon oxynitride（SiON）.The forming method of grid hard masking layer can use those skilled in the art
Any prior art being familiar with, preferably chemical vapour deposition technique (CVD), such as low temperature chemical vapor deposition (LTCVD), low pressure
Learn vapour deposition (LPCVD), fast thermal chemical vapor deposition (RTCVD), plasma enhanced chemical vapor deposition (PECVD).
Then, the side wall construction against grid structure is formed in grid structure both sides, its constituent material is SiO2、SiN、
One kind or combinations thereof in SiON.Then, using side wall construction as mask, LDD injections are performed, in side wall construction both sides
LDD injection regions are formed in Semiconductor substrate 200.Next, the offset side wall against side wall construction is formed in grid structure both sides,
As an example, offset side wall includes at least one layer of oxide skin(coating) and/or nitride layer.Then, using offset side wall as mask, perform
Source/drain region is injected, and source/drain region is formed in the Semiconductor substrate 200 of offset side wall both sides.
Then, self-alignment silicide technology is implemented, on the source/drain region of the top of grid structure and grid structure both sides
Form self-aligned silicide.Then, sequentially form to have on semiconductor substrate 200 and can produce the contact etch of stress characteristics
Stop-layer and interlayer dielectric layer, form connection positioned at the top and grid structure both sides of grid structure in interlayer dielectric layer
The contact hole of self-aligned silicide on source/drain region, fills metal（Usually tungsten）Connection interconnection metal is formed in contact hole
The contact plug of layer and the self-aligned silicide.
Next, it is possible to implement conventional semiconductor devices back end fabrication, including：The shape of multiple interconnecting metal layers
Into generally being completed using dual damascene process；The formation of metal pad, for implementing wire bonding during device encapsulation.
Reference picture 3, illustrated therein is the stream of method formation fleet plough groove isolation structure according to an exemplary embodiment of the present invention
Cheng Tu, the flow for schematically illustrating whole manufacturing process.
In step 301 there is provided Semiconductor substrate, formed on a semiconductor substrate with multiple fleet plough groove isolation structures
The hard mask layer of pattern；
In step 302, multiple fleet plough groove isolation structures are formed in the semiconductor substrate；
In step 303, implement dry etching and wet etching removes multiple fleet plough groove isolation structures and is higher by semiconductor lining
The part at bottom；
In step 304, hard mask layer is removed.
According to the present invention, implement dry etching and wet etching removes fleet plough groove isolation structure 201 and 202 and is higher by semiconductor
The part of substrate 200, can make the shallow trench isolation junction of the different zones being located in Semiconductor substrate 200 after the removal
The height of structure is consistent.
The present invention is illustrated by above-described embodiment, but it is to be understood that, above-described embodiment is only intended to
Citing and the purpose of explanation, and be not intended to limit the invention in described scope of embodiments.In addition people in the art
Member according to the teachings of the present invention it is understood that the invention is not limited in above-described embodiment, can also make more kinds of
Variants and modifications, these variants and modifications are all fallen within scope of the present invention.Protection scope of the present invention by
The appended claims and its equivalent scope are defined.
Claims (13)
1. a kind of manufacture method of semiconductor devices, including：
Semiconductor substrate is provided, the hard mask of the pattern with multiple fleet plough groove isolation structures is formed on the semiconductor substrate
Layer；
The multiple fleet plough groove isolation structure, the upper table of the multiple fleet plough groove isolation structure are formed in the Semiconductor substrate
Face is concordant with the upper surface of the hard mask layer；
Implement dry etching and wet etching removes the part that the multiple fleet plough groove isolation structure is higher by the Semiconductor substrate；
Remove the hard mask layer.
2. according to the method described in claim 1, it is characterised in that described half is formed in the multiple fleet plough groove isolation structure
The Partial Height with the region for being differently formed device density of conductor substrate is identical and width is different, the multiple shallow trench every
And width identical from the Partial Height in the region with same formation device density that the Semiconductor substrate is formed in structure
It is identical.
3. according to the method described in claim 1, it is characterised in that the hard mask layer is silicon nitride layer.
4. according to the method described in claim 1, it is characterised in that the step of forming the multiple fleet plough groove isolation structure is wrapped
Include：Using the hard mask layer as mask, etched in the Semiconductor substrate for forming the multiple shallow trench isolation junction
The groove of structure；Depositing isolation material in the trench and on the hard mask layer；Chemical mechanical milling tech is performed to grind
The isolated material, until exposing the hard mask layer.
5. method according to claim 4, it is characterised in that the isolated material is oxide.
6. method according to claim 4, it is characterised in that the deposition is completed several times, and the isolation deposited every time
Material is identical.
7. method according to claim 4, it is characterised in that after the deposition and the grinding, implements to move back respectively
Fire.
8. according to the method described in claim 1, it is characterised in that the etching gas of the dry etching is to include NF3And NH3
Mixture or include H2And NF3Mixture, the corrosive liquid of the wet etching for dilution hydrofluoric acid.
9. method according to claim 8, it is characterised in that the implementation process of the dry etching comprises the steps：
The etching gas is converted into comprising F ion, HF ions and NH under the action of radio of periphery4The plasma of ion；Will
The plasma imports the etching cavity for having placed the Semiconductor substrate, at 25-30 DEG C, and the plasma is with constituting
The isolated material of the multiple fleet plough groove isolation structure, which reacts, generates volatile complex compound；By the Semiconductor substrate
Temperature brings up to more than 100 DEG C, the complex compound volatilization is discharged from the etching cavity.
10. method according to claim 9, it is characterised in that the pressure of the dry etching is 2-3Torr, described to penetrate
The power of frequency is 15-50W.
11. according to the method described in claim 1, it is characterised in that the hard mask layer is implemented using wet-etching technology
Remove.
12. according to the method described in claim 1, it is characterised in that after the removal of the hard mask layer, in addition to institute
The step of stating Semiconductor substrate and the multiple fleet plough groove isolation structure implementation wet-cleaning.
13. method according to claim 12, it is characterised in that after the wet-cleaning, is additionally included in described half
The step of forming grid structure on conductor substrate, the grid structure includes gate dielectric, the grid stacked gradually from bottom to top
Pole material layer and grid hard masking layer.
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|---|---|---|---|
| CN201310410802.5A CN104425348B (en) | 2013-09-10 | 2013-09-10 | A kind of manufacture method of semiconductor devices |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5945724A (en) * | 1998-04-09 | 1999-08-31 | Micron Technology, Inc. | Trench isolation region for semiconductor device |
| US6372605B1 (en) * | 2000-06-26 | 2002-04-16 | Agere Systems Guardian Corp. | Additional etching to decrease polishing time for shallow-trench isolation in semiconductor processing |
| CN103236416A (en) * | 2013-04-09 | 2013-08-07 | 上海华力微电子有限公司 | Method for manufacturing shallow trench isolation structure |
-
2013
- 2013-09-10 CN CN201310410802.5A patent/CN104425348B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5945724A (en) * | 1998-04-09 | 1999-08-31 | Micron Technology, Inc. | Trench isolation region for semiconductor device |
| US6372605B1 (en) * | 2000-06-26 | 2002-04-16 | Agere Systems Guardian Corp. | Additional etching to decrease polishing time for shallow-trench isolation in semiconductor processing |
| CN103236416A (en) * | 2013-04-09 | 2013-08-07 | 上海华力微电子有限公司 | Method for manufacturing shallow trench isolation structure |
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