CN104465376A - Transistor and forming method thereof - Google Patents

Transistor and forming method thereof Download PDF

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Publication number
CN104465376A
CN104465376A CN201310425291.4A CN201310425291A CN104465376A CN 104465376 A CN104465376 A CN 104465376A CN 201310425291 A CN201310425291 A CN 201310425291A CN 104465376 A CN104465376 A CN 104465376A
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Prior art keywords
side wall
layer
grid structure
semiconductor substrate
drain area
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CN104465376B (en
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刘金华
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Corp
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Semiconductor Manufacturing International Shanghai Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41733—Source or drain electrodes for field effect devices for thin film transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41775—Source or drain electrodes for field effect devices characterised by the proximity or the relative position of the source or drain electrode and the gate electrode, e.g. the source or drain electrode separated from the gate electrode by side-walls or spreading around or above the gate electrode
    • H01L29/41783—Raised source or drain electrodes self aligned with the gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/6653—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using the removal of at least part of spacer, e.g. disposable spacer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/6656—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using multiple spacer layers, e.g. multiple sidewall spacers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Thin Film Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

A transistor and a forming method thereof are provided; the method comprises the following steps: providing a semiconductor substrate; forming a grid electrode structure on a semiconductor substrate surface, and a top of the grid electrode structure is provided with a mask layer; forming a first side wall and a second side wall on two side wall surfaces of the grid electrode structure and the mask layer; forming a semiconductor material layer on the semiconductor substrate surface on two sides of the grid electrode structure, and a surface of the semiconductor material layer is lower than that of the grid electrode structure; carrying out ion injection to the semiconductor material layer so as to form a source drain zone; removing the second side wall, and forming a groove between the source drain zone and the grid electrode first side wall; carrying out light dope ion injection on the semiconductor substrate of the bottom of the groove so as to form a light dope zone; removing the mask layer on the top of the grid electrode structure so as to expose a top surface of the grid electrode structure; forming a metal silicide layer on a surface of the source drain zone and the light dope zone. The method can reduce source drain zone resistance of the transistor, thus improving performance of the transistor.

Description

Transistor and forming method thereof
Technical field
The present invention relates to technical field of semiconductors, particularly a kind of transistor and forming method thereof.
Background technology
Along with the development of semiconductor technology, integrated circuit integration degree is more and more higher, and the size of device also constantly reduces.But the continuous reduction of device size causes the performance of device to be also greatly affected.Such as, short-channel effect, the problem such as power consumption is large, parasitic capacitance is large.
Prior art to insulate silicon on the end at SOI() substrate forms semiconductor device, form transistor on soi substrates, the parasitic capacitance in transistor can be reduced, improve the speed of service, and described transistor has lower power consumption.
But the thinner thickness of the top silicon layer due to SOI substrate, the thinner thickness of the source-drain area of the transistor that described SOI substrate is directly formed, there is higher series resistance, so, prior art generally on the substrate of the grid structure both sides of transistor extension form certain thickness silicon layer, then in described silicon layer, form the source-drain area raised, and form metal silicide layer on described source-drain area surface, thus improve the thickness of source-drain area, reduce the resistance of source-drain area.
But the series resistance of the source-drain area of described transistor also needs further reduction.
Summary of the invention
The problem that the present invention solves be to provide a kind of transistor and formation method, reduce the series resistance of source-drain area of transistor.
For solving the problem, the invention provides a kind of formation method of transistor, comprising: Semiconductor substrate is provided; Form grid structure at described semiconductor substrate surface, described grid structure top has mask layer; Form sidewall structure at described grid structure and mask layer both sides sidewall surfaces, described sidewall structure comprises the first side wall being positioned at described grid structure and mask layer both sides sidewall surfaces and the second side wall being positioned at described first side wall surface; Semiconductor substrate surface in described grid structure both sides forms semiconductor material layer, and the surface of described semiconductor material layer is lower than the surface of grid structure; Ion implantation is carried out to described semiconductor material layer, forms source-drain area; Remove described second side wall, between described source-drain area and grid first side wall, form groove; Light dope ion implantation is carried out to the Semiconductor substrate of described bottom portion of groove, forms light doping section; Remove the mask layer at grid structure top, expose the top surface of grid structure; Metal silicide layer is formed on the surface, light doping section of described source-drain area surface, bottom portion of groove.
Optionally, described Semiconductor substrate is silicon-on-insulator.
Optionally, the material of described mask layer is silica.
Optionally, described first side wall is not identical with the material of the second side wall.
Optionally, the material of described first side wall is silica, and the thickness of described first side wall is greater than
Optionally, the material of described second side wall is silicon nitride or silicon oxynitride
Optionally, the material of described semiconductor material layer is silicon, germanium or SiGe.
Optionally, adopt selective epitaxial process, form described semiconductor material layer.
Optionally, described grid structure comprises the gate dielectric layer being positioned at semiconductor substrate surface and the grid being positioned at described gate dielectric layer surface, and the material of described gate dielectric layer is silica, the material of described grid is polysilicon.
Optionally, be also included in grid structure top and also form metal silicide layer.
Optionally, the method forming described metal silicide comprises: in the light doping section of described source-drain area, bottom portion of groove, the forming metal layer on surface at the first side wall and grid structure top; Carry out annealing in process, form metal silicide layer on the surface, light doping section of described source-drain area surface, bottom portion of groove and grid structure top surface; Remove remaining metal level.
Optionally, the material of metal level at least comprises a kind of metallic element in Ni, Ta, Ti, W, Co, Pt or Pd.
Optionally, the light doping section of described bottom portion of groove is converted into metal silicide completely.
Optionally, also comprise:, first side wall surface surperficial at described metal silicide layer forms dielectric layer.
Optionally, the material of described dielectric layer is low-K dielectric material.
Optionally, the material of described dielectric layer at least comprises: the one in carborundum, silicon oxide carbide, organic siloxane polymer, fluorocarbons.
Technical scheme of the present invention also provides a kind of transistor adopting said method to be formed, and comprising: Semiconductor substrate; Be positioned at the grid structure of semiconductor substrate surface, described gate structure sidewall surface has the first chamber, side; Be positioned at the source-drain area of the Semiconductor substrate of described grid structure and the first side wall both sides, have groove between described source-drain area and the first side wall, the surface of described source-drain area is higher than semiconductor substrate surface and lower than grid structure surface; Light doping section in the Semiconductor substrate of the bottom portion of groove between described source-drain area and the first side wall; Be positioned at the metal silicide layer on surface, light doping section of described source-drain area surface, bottom portion of groove.
Optionally, the material of the light doping section of described bottom portion of groove is metal silicide.
Optionally, the metal silicide layer being positioned at grid structure top is also comprised.
Optionally, described metal silicide layer surface, the surperficial dielectric layer of also filling full described groove of the first side wall is positioned at.
Compared with prior art, technical scheme of the present invention has the following advantages:
Technical scheme of the present invention, forms the first side wall and the second side wall in described grid structure both sides; Then with described grid structure, the first side wall, the second side wall for mask, form the source-drain area raised in described grid structure both sides; Then remove described second side wall, between the described source-drain area raised and the first side wall, form groove, expose the surface of part semiconductor substrate; Light dope ion implantation is carried out to the Semiconductor substrate of described bottom portion of groove, forms light doping section; Form metal silicide layer at described source-drain area and surface, light doping section simultaneously, is only formed compared with metal silicide layer on source-drain area surface with prior art, the resistance of light doping section can be reduced further, the performance of raising transistor.
Further, after the described metal silicide layer of formation, in described metal silicide layer surface and groove, form dielectric layer.The material of described dielectric layer is low-K dielectric material, can reduce the parasitic capacitance between source-drain area and grid, improves the performance of transistor.
Accompanying drawing explanation
Fig. 1 is the structural representation of the transistor of prior art of the present invention.
Fig. 2 to Figure 15 is the structural representation of the forming process of the transistor of embodiments of the invention.
Embodiment
As described in the background art, in prior art, the series resistance of the source-drain area of transistor need further reduction.
Please refer to Fig. 1, is the structural representation of transistor formed on soi substrates.
Described transistor comprises: bottom silicon layer 10, be positioned at the insulating barrier 11 of bottom silicon surface, be positioned at the source-drain area 12 raised of the top silicon layer of described surface of insulating layer; Be positioned at the gate dielectric layer 21 on described top silicon layer surface, be positioned at the grid 22 on described gate dielectric layer surface, be positioned at the first side wall 23 of described gate dielectric layer 21 and grid 22 both sides sidewall surfaces and second side wall 24 on described first side wall 23 surface.Described transistor also comprises the metal silicide layer 25 being positioned at described grid 22 top and source-drain area 12 surface.
Because the top silicon layer of described SOI substrate is thinner, the top silicon layer surface in described grid structure both sides forms silicon layer, thus forms the source-drain area 12 raised, and can improve the thickness of source-drain area 12, reduce the series resistance of source-drain area 12; The series resistance that metal silicide layer 25 can reduce described source-drain area 12 is equally formed on described source-drain area 12 surface.
But, because described some extended area of source-drain area 12 (light doping section) is positioned at below described first side wall 23, second side wall 24, gate dielectric layer 21, the thinner thickness of described extended area, and surface cannot form metal silicide layer, thus described extended area still has higher resistance, the performance of transistor can be affected.
Embodiments of the invention, also form metal silicide layer at the part surface of the extended area (light doping section) of described source-drain area, reduce the series resistance of the source-drain area of transistor further.
For enabling above-mentioned purpose of the present invention, feature and advantage more become apparent, and are described in detail specific embodiments of the invention below in conjunction with accompanying drawing.
Please refer to Fig. 2, Semiconductor substrate 100 is provided.
The material of described Semiconductor substrate 100 comprises the semi-conducting materials such as silicon, germanium, SiGe, GaAs, and described Semiconductor substrate 100 can be body material also can be that composite construction is as silicon-on-insulator.Those skilled in the art can select the type of described Semiconductor substrate 100 according to the semiconductor device that Semiconductor substrate 100 is formed, therefore the type of described Semiconductor substrate should not limit the scope of the invention.
In the present embodiment, described Semiconductor substrate 100 be silicon-on-insulator (SOI) substrate, the top silicon layer 103 that described Semiconductor substrate 100 comprises bottom silicon layer 101, is positioned at the insulating barrier 102 of bottom silicon surface, is positioned at insulating barrier 102 surface.
Described silicon-on-insulator (SOI) substrate forms transistor, the parasitic capacitance of transistor can be reduced, improve the switching rate of transistor, reduce the power consumption of transistor.
Please refer to Fig. 3, form gate dielectric material layer 201 on described Semiconductor substrate 100 surface, be positioned at the gate material layers 202 on described gate dielectric layer material layer 201 surface, and be positioned at the mask layer 300 on described gate material layers 202 surface.
Adopt depositing operation to form described gate dielectric material layer 201, described depositing operation is chemical vapour deposition (CVD) or atom layer deposition process, and the thickness of described gate dielectric material layer 201 is 1nm to 100nm.
Adopt depositing operation to form described gate material layers 202, the thickness of described gate material layers is 10nm ~ 200nm.
In the present embodiment, the material of described gate dielectric material layer 201 is silica or silicon oxynitride, and the material of described gate material layers 202 is polysilicon.
The material of described mask layer 300 is silica or silicon nitride, and the thickness of described mask layer 300 is 1nm ~ 200nm, follow-uply carries out graphically to described mask layer 300, forms the mask of etching grid material layer 202 and gate dielectric material layer 201.
Please refer to Fig. 4, etch described mask layer 300(and please refer to Fig. 3) form mask layer 301; With described mask layer 301 for gate material layers 202(described in mask etching please refer to Fig. 3) and gate dielectric material layer 201(please refer to Fig. 3), form grid 212 and gate dielectric layer 211.
The method forming described mask layer 301 comprises: form photoresist layer on above-mentioned mask layer 300 surface; Carry out development exposure to above-mentioned photoresist layer, form graphical photoresist layer, described graphical photoresist layer defines position and the size of the grid structure of follow-up formation; With described graphical photoresist layer for mask, etch described mask layer 300(and please refer to Fig. 3), form mask layer 301.Described mask layer 301 please refer to Fig. 3 as subsequent etching gate material layers 202() and gate dielectric material layer 201(please refer to Fig. 3) mask.
Adopt dry etch process to etch described gate material layers 202(and please refer to Fig. 3) and gate dielectric material layer 201(please refer to Fig. 3), formation grid 212 and gate dielectric layer 211 respectively, the grid structure of described grid 212 and gate dielectric layer 211 transistor formed.
Please refer to Fig. 5, form the first spacer material layer 302 on described gate dielectric layer 211, grid 212, mask layer 301 sidewall surfaces and top silicon layer 103 surface.
Oxidation technology or depositing operation can be adopted to form described first spacer material layer 302.In the present embodiment, the material of described first spacer material layer 302 is silica, and adopt thermal oxidation technology to form described first spacer material layer 302, the thickness of described first spacer material layer 302 is greater than
Described first spacer material layer 302 is follow-up for the formation of the first side wall, and described first side wall as the isolation structure of grid structure both sides, can also repair the damage that described grid 212 is subject in etching process on the one hand.
In other embodiments of the invention, the material of described first spacer material layer 302 can also be silicon nitride or silicon oxynitride.
Please refer to Fig. 6, form the second spacer material layer 303 on described first spacer material layer 302, mask layer 301 surface.
Described second spacer material layer 303 can adopt chemical vapor deposition method to be formed, and described in the present embodiment, the material of the second spacer material layer 303 is silicon nitride.
Described in subsequent etching, the second spacer material layer 303 forms the second side wall, and described second side wall forms the mask of source-drain area as forming ion implantation.
The thickness of described second side wall is 1nm ~ 200nm.
Please refer to Fig. 7, etch described second spacer material layer 302(and please refer to Fig. 6) and the first spacer material layer 301, form the second side wall 313 and the first side wall 312 respectively.
Adopt and remove without mask etching technique the first spacer material layer 302 and the second spacer material layer 303 being positioned at mask layer 301 top and Portions of top layer silicon layer 103 surface, form the second side wall 313 and the first side wall 312.
The sidewall surfaces of described first side wall 312 mask film covering layer 301, grid 212, gate dielectric layer 211 and Portions of top layer silicon layer 103, described second side wall 313 is positioned at described first side wall 312 surface.
Described first side wall 313 injects the mask forming source-drain area as subsequent ion, for limiting the distance between source-drain area and grid.
Please refer to Fig. 8, form semiconductor material layer 400 on top silicon layer 103 surface of described grid 212, first side wall 312 and the second side wall 313 both sides.
Adopt selective epitaxial process, form described semiconductor material layer 400.In the present embodiment, the material of described semiconductor material layer 400 is silicon, and in example described in other of the present invention, the material of described semiconductor material layer 400 can also be the semi-conducting materials such as SiGe, Ge.Adopt selective epitaxial process can control growth rate and the thickness of described semi-conducting material preferably, make the surface of surface lower than grid 212 of the final described semiconductor material layer 400 formed.
Described semiconductor material layer 400, for improving the thickness of the semiconductor layer of grid 212 both sides, follow-uply forms source-drain area in the top silicon layer 103 of described semiconductor material layer 400 and below thereof.Described semiconductor material layer 400 improves the thickness of source-drain area, thus can reduce the series resistance of the source-drain area of formation.
Please refer to Fig. 9, heavy doping ion injection is carried out to the top silicon layer 103 of described semiconductor material layer 400 and below thereof, form source-drain area 401.
With described mask layer 301, first side wall 312, second side wall 313 for mask, Fig. 8 be please refer to described semiconductor material layer 400() and be positioned at described semiconductor material layer 400(and please refer to Fig. 8) immediately below Portions of top layer silicon layer 103 carry out heavy doping ion and inject and form source-drain area 401.
The type that described heavy doping ion is injected is identical with the type of transistor to be formed.
Please refer to Figure 10, remove described second side wall 313(and please refer to Fig. 9), form groove 314.
In the present embodiment, adopt wet-etching technology to remove the second side wall 313(and please refer to Fig. 9), the etching solution of described wet etching is phosphoric acid solution.In other embodiments of the invention, dry etch process also can be adopted to remove described second side wall 313.
The part second that described groove 314 exposes top silicon layer 103 surface of part between source-drain area 401 and grid 212 surveys wall 312.
Please refer to Figure 11, carry out light dope ion implantation in the Portions of top layer silicon layer 103 of described groove 314 bottom portion of groove, form light doping section 402.
The ionic type of described light dope ion implantation is identical with the type of transistor to be formed.Due to ion diffuse effect, part light doping section 402 is positioned at the below of gate dielectric layer 211.
Form the short-channel effect that transistor can be improved in described light doping section 402.
Please refer to Figure 12, the mask layer 301(removing part first side wall 312 bottom described groove 314 and grid 212 top please refer to Figure 11), expose the part surface of light doping section 402 and the top surface of grid 212.
After part first side wall 312 removing surface, described light doping section 402 and mask layer 301, expose the surface of light doping section 402 and grid 212, be convenient to follow-up at surface, described light doping section 402 and grid 212 top surface formation metal silicide layer.
Please refer to Figure 13, at described source-drain area 401, part light doping section 402, first side wall 312 and grid 212 forming metal layer on surface 500.
The material of metal level 500 at least comprises a kind of metallic element in Ni, Ta, Ti, W, Co, Pt or Pd.In the present embodiment, the material of described metal level 500 is Ni.
Evaporation or sputtering technology can be adopted to form described metal level 500.
Please refer to Figure 14, form metal silicide layer 501 on described source-drain area 401 surface, surface, part light doping section 402 and grid 212 surface.
In the present embodiment, adopt two step silicification technics to adopt boiler tube or short annealing equipment, in high-purity nitrogen environment, low temperature short annealing, such as reaction temperature 260 DEG C, 30 seconds duration, form rich nickel phase silicide; Subsequently, adopt the method for wet etching, remove unnecessary Ni metal level; Finally, adopt high temperature rapid thermal annealing, such as reaction temperature 500 DEG C, 30 seconds duration, rich nickel phase silicide is undergone phase transition, form metal silicide layer 501 on described source-drain area 401 surface, surface, part light doping section 402 and grid 212 surface.
In other embodiments of the invention, a step silicification technics can also be adopted: adopt boiler tube or short annealing equipment, high temperature rapid thermal annealing under highly purified nitrogen environment, directly forms nickel silicide.
Because metal can only to react formation metal silicide layer with silicon, described metal silicide layer 501 can only be formed in described source-drain area 401 surface, surface, part light doping section 402 and grid 212 surface.
After forming described metal silicide layer 501, adopt wet etching method, remove unnecessary metal layer material.
In the present embodiment, due to the thinner thickness of described light doping section 402, silicon and the metal of described light doping section 402 fully react, and change the resistance that metal silicide reduces described light doping section 402 completely into.
Compared with prior art, in the present embodiment, not only form metal silicide layer on source-drain area 401 surface, also form metal silicide layer on surface, light doping section 402, reduce further resistance, avoid the thinner thickness due to light doping section, cause the problem that resistance is larger, thus the performance of transistor can be improved.
Please refer to Figure 15, first side wall 312 surface surperficial at described metal silicide layer 501 forms dielectric layer 600.
Described dielectric layer 600 is filled full groove 314(and be please refer to Figure 14) and cover the metal silicide layer 501 on described source-drain area 401, part light doping section 402, grid 212 surface.Described dielectric layer 600, as the interlayer dielectric layer of transistor surface, follow-uply can form metal plug in described dielectric layer 600, connects source-drain area 401 and the grid 212 of transistor.
The material of described dielectric layer 600 is low-K dielectric material, at least comprises the one in carborundum, silicon oxide carbide, organic siloxane polymer, fluorocarbons.The K value of described low-K dielectric material is lower, effectively can reduce the parasitic capacitance between grid 211 and source-drain area 401, improves the operating rate of transistor, improves the performance of transistor.In the present embodiment, the material of described dielectric layer 600 is carborundum, adopts chemical vapor deposition method to form described dielectric layer 600.
The present embodiment also provides a kind of transistor adopting said method to be formed.
Please refer to Figure 15, is the structural representation of described transistor.
Described transistor comprises: Semiconductor substrate, in the present embodiment, described Semiconductor substrate is silicon-on-insulator (SOI) substrate, the top silicon layer 103 that described Semiconductor substrate comprises bottom silicon layer 101, is positioned at the insulating barrier 102 of bottom silicon surface, is positioned at insulating barrier 102 surface;
Be positioned at the grid structure on top silicon layer 103 surface of Semiconductor substrate, described grid structure comprises gate dielectric layer 211 and grid 212, and described gate structure sidewall surface has the first side wall 312;
Be positioned at the source-drain area 401 of the Semiconductor substrate of described grid structure and the first side wall 312 both sides, between described source-drain area 401 and the first side wall 312, there is groove, the surface of described source-drain area 401 higher than Semiconductor substrate surface and lower than grid structure surface;
Light doping section 402 in the Semiconductor substrate of the bottom portion of groove between described source-drain area 401 and the first side wall 312;
Be positioned at the metal silicide layer 501 on surface, light doping section 402 of described source-drain area 401 surface, bottom portion of groove.
In the present embodiment, the material of the light doping section 402 of described bottom portion of groove is metal silicide, and described grid structure top also has metal silicide layer 501.
In the present embodiment, described transistor also comprises the dielectric layer 600 being positioned at described metal silicide layer 501 surface, the full described groove of the surperficial also filling of the first side wall 312, the material of described dielectric layer is low-K dielectric material, at least comprises: the one in carborundum, silicon oxide carbide, organic siloxane polymer, fluorocarbons.
Source-drain area 401 and the surface, light doping section 402 of the transistor that the present embodiment provides all are formed with metal silicide layer, can reduce the resistance of source-drain area and light doping section simultaneously, improve the performance of transistor.Further, between described grid structure and source-drain area, be filled with low K dielectric layer, the parasitic capacitance between described grid and source-drain area can be reduced, improve the operating rate of transistor, improve the performance of transistor.
Although the present invention discloses as above, the present invention is not defined in this.Any those skilled in the art, without departing from the spirit and scope of the present invention, all can make various changes or modifications, and therefore protection scope of the present invention should be as the criterion with claim limited range.

Claims (20)

1. a formation method for transistor, is characterized in that, comprising:
Semiconductor substrate is provided;
Form grid structure at described semiconductor substrate surface, described grid structure top has mask layer;
Form the first side wall at described grid structure and mask layer both sides sidewall surfaces and be positioned at second side wall on described first side wall surface;
Semiconductor substrate surface in described grid structure both sides forms semiconductor material layer, and the surface of described semiconductor material layer is lower than the surface of grid structure;
Ion implantation is carried out to described semiconductor material layer, forms source-drain area;
Remove described second side wall, between described source-drain area and the first side wall, form groove;
Light dope ion implantation is carried out to the Semiconductor substrate of described bottom portion of groove, forms light doping section;
Remove the mask layer at grid structure top, expose the top surface of grid structure;
Metal silicide layer is formed on the surface, light doping section of described source-drain area surface, bottom portion of groove.
2. the formation method of transistor according to claim 1, is characterized in that, described Semiconductor substrate is silicon-on-insulator.
3. the formation method of transistor according to claim 1, is characterized in that, the material of described mask layer is silica.
4. the formation method of transistor according to claim 1, is characterized in that, described first side wall is not identical with the material of the second side wall.
5. the formation method of transistor according to claim 4, is characterized in that, the material of described first side wall is silica, and the thickness of described first side wall is greater than
6. the formation method of transistor according to claim 5, is characterized in that, the material of described second side wall is silicon nitride or silicon oxynitride.
7. the formation method of transistor according to claim 1, is characterized in that, the material of described semiconductor material layer is silicon, germanium or SiGe.
8. the formation method of transistor according to claim 7, is characterized in that, adopts selective epitaxial process, forms described semiconductor material layer.
9. the formation method of transistor according to claim 1, it is characterized in that, described grid structure comprises the gate dielectric layer being positioned at semiconductor substrate surface and the grid being positioned at described gate dielectric layer surface, and the material of described gate dielectric layer is silica, the material of described grid is polysilicon.
10. the formation method of transistor according to claim 9, is characterized in that, is also included in grid structure top and also forms metal silicide layer.
The formation method of 11. transistors according to claim 10, is characterized in that, the method forming described metal silicide comprises: in the light doping section of described source-drain area, bottom portion of groove, the forming metal layer on surface at the first side wall and grid structure top; Carry out annealing in process, form metal silicide layer on the surface, light doping section of described source-drain area surface, bottom portion of groove and grid structure top surface; Remove remaining metal level.
The formation method of 12. transistors according to claim 11, is characterized in that, the material of metal level at least comprises a kind of metallic element in Ni, Ta, Ti, W, Co, Pt or Pd.
The formation method of 13. transistors according to claim 12, is characterized in that, the light doping section of described bottom portion of groove is converted into metal silicide completely.
The formation method of 14. transistors according to claim 1, is characterized in that, also comprise:, first side wall surface surperficial at described metal silicide layer forms dielectric layer.
The formation method of 15. transistors according to claim 14, is characterized in that, the material of described dielectric layer is low-K dielectric material.
The formation method of 16. transistors according to claim 15, is characterized in that, the material of described dielectric layer at least comprises: the one in carborundum, silicon oxide carbide, organic siloxane polymer, fluorocarbons.
17. 1 kinds of transistors, is characterized in that, comprising:
Semiconductor substrate;
Be positioned at the grid structure of semiconductor substrate surface, described gate structure sidewall surface has the first side wall;
Be positioned at the source-drain area of the Semiconductor substrate of described grid structure and the first side wall both sides, have groove between described source-drain area and the first side wall, the surface of described source-drain area is higher than semiconductor substrate surface and lower than grid structure surface;
Light doping section in the Semiconductor substrate of the bottom portion of groove between described source-drain area and the first side wall;
Be positioned at the metal silicide layer on surface, light doping section of described source-drain area surface, bottom portion of groove.
18. transistors according to claim 17, is characterized in that, the material of the light doping section of described bottom portion of groove is metal silicide.
19. transistors according to claim 17, is characterized in that, also comprise the metal silicide layer being positioned at grid structure top.
20. transistors according to claim 17, is characterized in that, also comprise: be positioned at described metal silicide layer surface, the surperficial dielectric layer of also filling full described groove of the first side wall.
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