CN104517889A - Isolation structure forming method - Google Patents
Isolation structure forming method Download PDFInfo
- Publication number
- CN104517889A CN104517889A CN201310462446.1A CN201310462446A CN104517889A CN 104517889 A CN104517889 A CN 104517889A CN 201310462446 A CN201310462446 A CN 201310462446A CN 104517889 A CN104517889 A CN 104517889A
- Authority
- CN
- China
- Prior art keywords
- substrate
- formation method
- layer
- oxide layer
- isolation structure
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
Abstract
An isolation structure forming method includes: providing a substrate; performing oxygen ion implantation to form a doping region at a position, a certain depth away from the surface of the substrate, of the substrate; forming trenches in the substrate after oxygen ion implantation; after trench forming, performing a thermal process to form a buried oxide layer at the doping area position, wherein the buried oxide layer is exposed in the trenches; forming insulation layers covering the bottoms and the sidewalls of the trenches. The isolation structure forming method has the advantages that since the buried oxide layer is formed at the position, a certain depth away from the surface of the substrate, of the substrate by means of oxygen ion implantation, the isolation structure forming method is simpler than existing isolation structure forming methods; additionally, the buried oxide layer in an isolation structure is formed by means of oxygen ion implantation rather than that an insulation layer in a silicon-on-insulation substrate serves as the buried oxide layer, and accordingly, manufacturing cost of the isolation structure can be reduced.
Description
Technical field
The present invention relates to technical field of semiconductors, particularly relate to a kind of formation method of isolation structure.
Background technology
Isolation structure is for by adjacent two the active area electric isolution on substrate.When forming analog circuit (Analog Circuit) in the active area of substrate, good interference free performance is obtained in order to make analog circuit, described isolation structure is except comprising groove isolation construction, also comprise: bury oxide layer (Buried Oxide) with a certain distance from substrate surface, this buries oxide layer and groove isolation construction forms the isolation structure closed.
The formation method of existing a kind of isolation structure comprises: as shown in Figure 1, substrate 1 is provided, substrate 1 adopts silicon-on-insulator substrate (Silicon On Insulation), comprise bottom silicon layer 11, top silicon layer 13 and the insulating barrier between bottom silicon layer 11 and top silicon layer 13 12, insulating barrier 12 is as burying oxide layer; The groove isolation construction 2 that bottom extends to insulating barrier 12 is formed in top silicon layer 13.
In above-mentioned isolation structure formation method, burying oxide layer is served as by the insulating barrier in silicon-on-insulator substrate, because the cost of silicon-on-insulator substrate is higher, causes the manufacturing cost adding isolation structure.
The formation method of existing another kind of isolation structure comprises: first formed in substrate and bury oxide layer, then form groove isolation construction in substrate.Wherein, the formation method of burying oxide layer described in comprises:
As shown in Figure 2, monocrystalline substrate 3 is provided, utilize the polysilicon Seed Layer that thermal oxidation technology forms silicon oxide layer on monocrystalline substrate 3 surface and is positioned on silicon oxide layer, carry out graphically to this polysilicon Seed Layer and silicon oxide layer, to form island stacked structure 4 on monocrystalline substrate 3 surface, island stacked structure 4 comprises silicon oxide layer 41 and polysilicon Seed Layer 42, and silicon oxide layer 41 buries oxide layer as described.
As shown in Figure 3, carry out epitaxial growth, to form epitaxial loayer in monocrystalline substrate 3 and island stacked structure 4, wherein, the epitaxial loayer covering monocrystalline substrate 3 surface is single-crystal Si epitaxial layers 5, and the epitaxial loayer covering island stacked structure 4 surface is polysilicon epitaxial layer 6.Then, single-crystal Si epitaxial layers 5 and polysilicon epitaxial layer 6 form cap 7.
As shown in Figure 4, carry out rapid thermal treatment (Rapid Thermal Process, be called for short RTP), make polysilicon Seed Layer 42 and polysilicon epitaxial layer 6(as shown in Figure 3) fusing (now monocrystalline substrate 3 and single-crystal Si epitaxial layers 5 are still in solid-state), along with temperature declines gradually after rapid thermal treatment, polysilicon Seed Layer 42 and polysilicon epitaxial layer 6(are as shown in Figure 3) there is recrystallization, make its material become monocrystalline silicon from polysilicon, to form monocrystalline silicon layer 8.Therefore, single-crystal Si epitaxial layers 5, monocrystalline silicon layer 8 are identical with the material of monocrystalline substrate 3, and three forms substrate jointly, have with a certain distance from this substrate surface as the silicon oxide layer 41 burying oxide layer.
As shown in Figure 5, carry out cmp, to remove cap 7(as shown in Figure 4).
In above-mentioned isolation structure formation method, the formation method of burying oxide layer is comparatively complicated.
Summary of the invention
The problem to be solved in the present invention is: existing formation in substrate in the method closing isolation structure forms that the method for burying oxide layer is comparatively complicated, cost is higher.
For solving the problem, the invention provides a kind of formation method of isolation structure, comprising:
Substrate is provided;
Carry out O +ion implanted, with the formation doped region, position at described substrate distance substrate surface certain depth;
After carrying out described O +ion implanted, in described substrate, form groove;
After forming described groove, heat-treat and bury oxide layer to be formed in position, described doped region, described in described groove exposes, bury oxide layer.
Optionally, the technological parameter of described O +ion implanted comprises: O +ion implanted dosage is 1 × 10
17atom/cm
3to 5 × 10
18atom/cm
3, O +ion implanted energy is 100Kev to 2.5Mev.
Optionally, described heat treatment carries out in oxygenous atmosphere, and with while burying oxide layer described in formation, formation covers described channel bottom and sidewall, material are the insulating barrier of silica.
Optionally, described oxygenous atmosphere also comprises hydrogen.
Optionally, described oxygenous gas also comprises inert gas.
Optionally, described inert gas is the mist of nitrogen and argon gas.
Optionally, described process of thermal treatment parameter comprises: temperature is 900 DEG C to 1300 DEG C, and the time is 30min to 800min, the flow of oxygen is 1slm to 20slm, the flow of hydrogen is 0.1slm to 10slm, and the flow of nitrogen is 0.1slm to 20slm, and the flow of argon gas is 0.1slm to 20slm.
Optionally, also comprise: form the packed layer be positioned on described insulating barrier, described packed layer is full by described trench fill.
Optionally, the material of described packed layer is silica, silicon nitride or polysilicon.
Optionally, also comprise: formed insulating barrier full for described trench fill.
Optionally, the formation method of described doped region comprises:
Form mask layer over the substrate, described mask layer has the opening exposing substrate;
With described mask layer for mask carries out O +ion implanted, to form described doped region in the substrate below described opening;
After forming described doped region, remove described mask layer.
Compared with prior art, technical scheme of the present invention has the following advantages:
Bury oxide layer by O +ion implanted method in the position formation of substrate distance surface certain depth, compared with the formation method of existing isolation structure, the method is more simple.In addition, because the oxide layer of burying in isolation structure utilizes O +ion implanted method to be formed, instead of utilize the insulating barrier in silicon-on-insulator substrate to serve as, thus can reduce the manufacturing cost of isolation structure.
Further, carry out described heat treatment with formed bury in the step of oxide layer, the groove in substrate can be released in the stress produced in heat treatment step.
Accompanying drawing explanation
Fig. 1 is the cross-sectional view of existing a kind of isolation structure;
Fig. 2 to Fig. 5 be in a kind of existing isolation structure formation method isolation structure in the cross-sectional view of different production phase;
Fig. 6 to Figure 11 be in the first embodiment of the present invention substrate in the cross-sectional view of different production phase;
Figure 12 to Figure 13 be in the third embodiment of the present invention substrate in the cross-sectional view of different production phase;
Figure 14 is the cross-sectional view of substrate production phase wherein in the fourth embodiment of the present invention.
Embodiment
For enabling above-mentioned purpose of the present invention, feature and advantage more become apparent, and are described in detail specific embodiments of the invention below in conjunction with accompanying drawing.
As shown in Figure 6, substrate 100 is provided.
In the present embodiment, substrate 100 is silicon substrate.In other embodiments, substrate 100 also can contain the substrate of silicon for other.
Continue, with reference to shown in Fig. 6, to carry out O +ion implanted, with in the position formation doped region 110 of substrate 100 apart from surperficial certain depth.
In the present embodiment, the formation method of doped region 110 comprises: form mask layer 120 on the substrate 100, mask layer 120 has the opening 121 exposing substrate 100; With mask layer 120 for mask carries out O +ion implanted, to form doped region 110 in the substrate 100 below opening 121; As shown in Figure 7, form doped region 110 and remove mask layer 120(afterwards as shown in Figure 6).
In a particular embodiment, mask layer 120 is photoresist layer.In other embodiments, mask layer 120 also can be the laminated construction of silicon oxide layer and photoresist layer, and photoresist layer is positioned at above silicon oxide layer; Or mask layer 120 also can be the laminated construction of silicon nitride layer and photoresist layer, and photoresist layer is positioned at above silicon nitride layer; Or mask layer 120 also can be the laminated construction of silicon nitride layer, silicon oxide layer and photoresist layer, and silicon oxide layer is positioned at above silicon nitride layer, and photoresist layer is positioned at above silicon oxide layer.Certainly, mask layer 120 can not be confined to given embodiment, also can be suitable for use as the material of mask for other.
In a particular embodiment, the technological parameter of described O +ion implanted comprises: O +ion implanted dosage is 1 × 10
17atom/cm
3to 5 × 10
18atom/cm
3, O +ion implanted energy is 100Kev to 2.5Mev.
Carrying out in described O +ion implanted step, to heat substrate 100, to increase the activity of oxonium ion.In a particular embodiment, when carrying out described O +ion implanted, the temperature of substrate 100 is 400 DEG C to 600 DEG C.
As shown in Figure 8, in substrate 100, groove 130 is formed.
In the present embodiment, the formation method of groove 130 comprises: form mask layer 140 on the substrate 100, mask layer 140 has the opening (mark) exposing substrate 100; With mask layer 140 for mask etches, to form groove 130 in substrate 100, described lithographic method can be dry etching.In a particular embodiment, mask layer 140 is oxide-nitride-oxide laminated construction.
In the present embodiment, groove 130 is positioned at doped region 110 around, and in other words, groove 130 projection on the surface of a substrate, is surrounded doped region 110 projection on the surface of a substrate; The bottom of groove 130 is positioned at below doped region 110, and the sidewall of groove 130 exposes and buries oxide layer 110.
In a particular embodiment, the degree of depth of groove 130 is 1000A to 4um.
As shown in Figure 9, heat-treat with at doped region 110(as shown in Figure 8) position forms and buries oxide layer 150.In the present embodiment, the sidewall of groove 130 exposes and buries oxide layer 150.
Described heat treatment has following effect: 1) impel the oxonium ion of doped region 110 and substrate 100 that chemical reaction occurs, and oxide layer 150 is buried in generation uniformly; 2) to being formed in groove 130 process in etching, the damage that substrate 100 causes is repaired.
Carrying out in described heat treatment process, larger stress can formed in substrate 100, owing to being formed with groove 130 in substrate 100, the stress produced in described heat treatment process can be discharged.
In the present embodiment, described heat treatment carries out, so that more uniformly heat substrate 100 in containing the atmosphere of inert gas.Described inert gas is containing one or both in nitrogen, argon gas.
In the present embodiment, described atmosphere also comprises oxygen.So, while heat treatment step, can there is chemical reaction with substrate 100 in oxygen, with formed to cover bottom groove 130 and on sidewall, the material insulating barrier 160 that is silica, insulating barrier 160 is not filled expires groove 130.Sidewall due to groove 130 has to expose and buries oxide layer 150, therefore the insulating barrier 160 covered on groove 130 sidewall can realize " seamless link " with burying oxide layer 150, namely insulating barrier 160 with bury oxide layer 150 and be linked to be an entirety.
In a particular embodiment, described heat treatment carries out in the atmosphere of oxygenous, nitrogen and argon gas, described process of thermal treatment parameter comprises: temperature is 900 DEG C to 1300 DEG C, time is 30min to 800min, the flow of oxygen is 1slm to 20slm, the flow of nitrogen is 0.1slm to 20slm, and the flow of argon gas is 0.1slm to 20slm.
In other embodiments, described atmosphere, except comprising oxygen, nitrogen and argon gas, can also comprise hydrogen, to improve the formation speed of insulating barrier 160.In this case, the flow of hydrogen is 0.1slm to 10slm.
Form the packed layer be positioned on insulating barrier, groove fills up by packed layer.
In the present embodiment, the formation method of described packed layer comprises: as shown in Figure 10, and formation covers on mask layer 140, the encapsulant layer 171 be filled in groove 130; As shown in figure 11, carry out planarization, to remove encapsulant layer 171(unnecessary outside mask layer 140 and groove 130 as shown in Figure 10), form the packed layer 170 be positioned on insulating barrier 160, groove 130 is filled full by packed layer 170, in a particular embodiment, described planarization can be cmp.
Groove 130 is filled full insulating barrier 160 and packed layer 170 forms groove isolation construction.Due to insulating barrier 160 with bury oxide layer 150 and be linked to be an entirety, make described groove isolation construction and bury oxide layer 150 to form a U-shaped closed isolation structure.Described U-shaped closed isolation structure can define the active area for the formation of semiconductor device in substrate 100.Under the effect of this U-shaped closed isolation structure, be positioned at this active area semiconductor device can with the semiconductor device of adjacent active regions electric isolution effectively.
In the present embodiment, the material of packed layer 170 is silica, silicon nitride or polysilicon.In other embodiments, packed layer 170 also can be suitable for being filled in material in groove (this material can for electric conducting material, also can be insulating material) for other, is not limited to the present embodiment.
Insulating barrier 160 has following effect: as transition of stress layer, and dislocation occurs the stress excessive substrate 100 that causes preventing packed layer 170 pairs of substrates 100 from applying, so that the device be formed in substrate 100 can produce leakage current under non-operating state.
From the above, to be formed in the position of substrate distance surface certain depth by O +ion implanted method and bury oxide layer, then formed in substrate and be linked to be an overall groove isolation construction with buried oxide layer, closed isolation structure can be formed.Compared with the formation method of existing isolation structure, the method is more simple.In addition, because the oxide layer of burying in isolation structure utilizes O +ion implanted method to be formed, instead of utilize the insulating barrier in silicon-on-insulator substrate to serve as, thus can reduce the manufacturing cost of isolation structure.
Second embodiment
Difference between second embodiment and the first embodiment is: in a second embodiment, and described heat treatment step does not carry out in oxygenous atmosphere, while making to be formed in substrate and burying oxide layer, does not form insulating barrier at the sidewall of groove and bottom.In this case, formed after burying oxide layer, first at sidewall and the bottom formation insulating barrier of groove, then can form packed layer on the insulating layer, by trench fill completely, the material of packed layer can be electric conducting material or insulating material for this insulating barrier and packed layer; Or, formed after burying oxide layer, directly can form the insulating barrier of filling full groove.
3rd embodiment
Difference between 3rd embodiment and the first embodiment is: in the third embodiment, as shown in figure 12, formed after doped region 110 in substrate 100, the groove 130 that formation is positioned at above doped region 110 substrate 100 in, the bottom of groove 130 is exposed and is buried oxide layer 110; Then, as shown in figure 13, carry out described heat treatment, with at doped region 110(as shown in figure 12) position forms and buries oxide layer 150, and form insulating barrier 160 at the sidewall of groove 130 and bottom, the bottom of groove 130 is exposed and is buried oxide layer 150, insulating barrier 160 with bury oxide layer 150 and be linked to be an entirety.
4th embodiment
Difference between 4th embodiment and the first embodiment is: in the fourth embodiment, as shown in figure 14, doped region 110 projection on the surface of a substrate, groove 130 projection is on the surface of a substrate surrounded, the doped region 110 of respective grooves 130 position is removed, the bottom of groove 130 is positioned at below doped region 110, and the sidewall of groove 130 exposes doped region 110.
It should be noted that, the formation method of insulating barrier is not limited to above-described embodiment, in other embodiments, chemical gaseous phase depositing process also can be utilized to form described insulating barrier.
Need it is emphasized that in above-described embodiment and accompanying drawing, before carrying out described heat treatment, groove all has and exposes doped region, makes heat treatment with after being formed and burying oxide layer, and groove can expose and buries oxide layer.In other embodiments, before carrying out described heat treatment, groove also can not expose doped region, but should ensure that the backing material (oxygen-free ion) between groove and doped region is less, so, in heat treatment process, oxonium ion in doped region can diffuse in the backing material between groove and doped region, after making heat treatment, the backing material between groove and doped region also can be formed and bury oxide layer, and then groove can be exposed bury oxide layer.
In the present invention, each embodiment adopts laddering literary style, and emphasis describes the difference with previous embodiment, and the same section in each embodiment can with reference to previous embodiment.
Although the present invention discloses as above, the present invention is not defined in this.Any those skilled in the art, without departing from the spirit and scope of the present invention, all can make various changes or modifications, and therefore protection scope of the present invention should be as the criterion with claim limited range.
Claims (11)
1. a formation method for isolation structure, is characterized in that, comprising:
Substrate is provided;
Carry out O +ion implanted, with the formation doped region, position at described substrate distance substrate surface certain depth;
After carrying out described O +ion implanted, in described substrate, form groove;
After forming described groove, heat-treat and bury oxide layer to be formed in position, described doped region, described in described groove exposes, bury oxide layer.
2. formation method according to claim 1, is characterized in that, the technological parameter of described O +ion implanted comprises: O +ion implanted dosage is 1 × 10
17atom/cm
3to 5 × 10
18atom/cm
3, O +ion implanted energy is 100Kev to 2.5Mev.
3. formation method according to claim 1, is characterized in that, described heat treatment carries out in oxygenous atmosphere, and with while burying oxide layer described in formation, formation covers described channel bottom and sidewall, material are the insulating barrier of silica.
4. formation method according to claim 3, is characterized in that, described oxygenous atmosphere also comprises hydrogen.
5. formation method according to claim 4, is characterized in that, described oxygenous atmosphere also comprises inert gas.
6. formation method according to claim 5, is characterized in that, described inert gas is the mist of nitrogen and argon gas.
7. formation method according to claim 6, it is characterized in that, described process of thermal treatment parameter comprises: temperature is 900 DEG C to 1300 DEG C, time is 30min to 800min, the flow of oxygen is 1slm to 20slm, the flow of hydrogen is 0.1slm to 10slm, and the flow of nitrogen is 0.1slm to 20slm, and the flow of argon gas is 0.1slm to 20slm.
8. formation method according to claim 3, is characterized in that, also comprise: form the packed layer be positioned on described insulating barrier, and described packed layer is full by described trench fill.
9. formation method according to claim 8, is characterized in that, the material of described packed layer is silica, silicon nitride or polysilicon.
10. formation method according to claim 1, is characterized in that, also comprise: formed insulating barrier full for described trench fill.
11. formation methods according to claim 1, is characterized in that, the formation method of described doped region comprises:
Form mask layer over the substrate, described mask layer has the opening exposing substrate;
With described mask layer for mask carries out O +ion implanted, to form described doped region in the substrate below described opening;
After forming described doped region, remove described mask layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310462446.1A CN104517889B (en) | 2013-09-30 | 2013-09-30 | The forming method of isolation structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310462446.1A CN104517889B (en) | 2013-09-30 | 2013-09-30 | The forming method of isolation structure |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN104517889A true CN104517889A (en) | 2015-04-15 |
| CN104517889B CN104517889B (en) | 2018-07-10 |
Family
ID=52792997
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201310462446.1A Active CN104517889B (en) | 2013-09-30 | 2013-09-30 | The forming method of isolation structure |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN104517889B (en) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6521947B1 (en) * | 1999-01-28 | 2003-02-18 | International Business Machines Corporation | Method of integrating substrate contact on SOI wafers with STI process |
| CN1431701A (en) * | 2003-02-14 | 2003-07-23 | 中国科学院上海微系统与信息技术研究所 | Method for forming graphical oxygen injection and separator with shallow grooves at same time |
| CN101258590A (en) * | 2005-09-06 | 2008-09-03 | Nxp股份有限公司 | Method of manufacturing a semiconductor device with an isolation region and a device manufactured by the method |
| CN101692435A (en) * | 2009-10-15 | 2010-04-07 | 苏州博创集成电路设计有限公司 | Etching and filling method of deep groove isolation structure of silicon-on-insulator |
-
2013
- 2013-09-30 CN CN201310462446.1A patent/CN104517889B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6521947B1 (en) * | 1999-01-28 | 2003-02-18 | International Business Machines Corporation | Method of integrating substrate contact on SOI wafers with STI process |
| CN1431701A (en) * | 2003-02-14 | 2003-07-23 | 中国科学院上海微系统与信息技术研究所 | Method for forming graphical oxygen injection and separator with shallow grooves at same time |
| CN101258590A (en) * | 2005-09-06 | 2008-09-03 | Nxp股份有限公司 | Method of manufacturing a semiconductor device with an isolation region and a device manufactured by the method |
| CN101692435A (en) * | 2009-10-15 | 2010-04-07 | 苏州博创集成电路设计有限公司 | Etching and filling method of deep groove isolation structure of silicon-on-insulator |
Also Published As
| Publication number | Publication date |
|---|---|
| CN104517889B (en) | 2018-07-10 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN104733531B (en) | Use the double oxide Trench-gate power MOSFET of oxide filling groove | |
| US9773892B2 (en) | Isolation structure of fin field effect transistor | |
| CN106206676B (en) | The structure and forming method of FinFET | |
| CN104103516B (en) | Fleet plough groove isolation structure and forming method thereof | |
| JP2007299951A (en) | Semiconductor device and its manufacturing method | |
| KR20040046056A (en) | Semiconductor device having isolation structure of preventing leakage current and method of fabricating the same | |
| TWI694544B (en) | Semiconductor device and method of preparing the same | |
| CN104425520B (en) | Semiconductor devices and forming method | |
| US6566680B1 (en) | Semiconductor-on-insulator (SOI) tunneling junction transistor | |
| CN103854987B (en) | The forming method of the forming methods of pseudo- grid, the method for selective deposition silicon and connector | |
| JP5875334B2 (en) | Silicon carbide semiconductor device | |
| CN104517889A (en) | Isolation structure forming method | |
| CN106298526B (en) | The production method of silicon field-effect transistor device on quasi-insulator | |
| CN103681505A (en) | Source-drain double epitaxial layer forming method | |
| CN113113347B (en) | Shallow trench isolation structure and preparation method thereof | |
| CN103633027A (en) | Method for forming double epitaxial layers of source-drain area | |
| TWI517393B (en) | Semiconductor device and method of fabricating the same | |
| CN109755172B (en) | Shallow trench isolation structure, semiconductor device and manufacturing method thereof | |
| CN109148370B (en) | Semiconductor structure and forming method thereof | |
| US7972921B2 (en) | Integrated circuit isolation system | |
| US8685830B2 (en) | Method of filling shallow trenches | |
| CN103632929A (en) | Method for forming double epitaxial layers of semiconductor device | |
| CN103426761B (en) | A kind of MOSFET element and preparation method | |
| CN110571148B (en) | Processing method of power semiconductor device and power semiconductor device | |
| CN108122965A (en) | Semiconductor structure and forming method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |