CN104576737A - 半导体器件 - Google Patents

半导体器件 Download PDF

Info

Publication number
CN104576737A
CN104576737A CN201410543952.8A CN201410543952A CN104576737A CN 104576737 A CN104576737 A CN 104576737A CN 201410543952 A CN201410543952 A CN 201410543952A CN 104576737 A CN104576737 A CN 104576737A
Authority
CN
China
Prior art keywords
semiconductor device
groove
channel region
separated
raceway groove
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201410543952.8A
Other languages
English (en)
Other versions
CN104576737B (zh
Inventor
F.希尔勒
A.迈泽尔
T.施勒泽尔
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies AG
Original Assignee
Infineon Technologies AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies AG filed Critical Infineon Technologies AG
Publication of CN104576737A publication Critical patent/CN104576737A/zh
Application granted granted Critical
Publication of CN104576737B publication Critical patent/CN104576737B/zh
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402—Field plates
    • H01L29/407—Recessed field plates, e.g. trench field plates, buried field plates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
    • H01L29/0653—Dielectric regions, e.g. SiO2 regions, air gaps adjoining the input or output region of a field-effect device, e.g. the source or drain region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
    • H01L29/0856—Source regions
    • H01L29/0865—Disposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
    • H01L29/0873—Drain regions
    • H01L29/0882—Disposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7811—Vertical DMOS transistors, i.e. VDMOS transistors with an edge termination structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
    • H01L29/7825—Lateral DMOS transistors, i.e. LDMOS transistors with trench gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
    • H01L29/7835—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7838—Field effect transistors with field effect produced by an insulated gate without inversion channel, e.g. buried channel lateral MISFETs, normally-on lateral MISFETs, depletion-mode lateral MISFETs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
    • H01L29/808—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier with a PN junction gate, e.g. PN homojunction gate
    • H01L29/8083—Vertical transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H01L29/0692—Surface layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H01L29/0692—Surface layout
    • H01L29/0696—Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41766—Source or drain electrodes for field effect devices with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
    • H01L29/42368—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity the thickness being non-uniform

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Thin Film Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

本发明涉及半导体器件。半导体器件包含在包含主要表面的半导体衬底中形成的晶体管。晶体管包含源极区、漏极区、沟道区、和栅极电极。源极区和漏极区沿着第一方向被安置，第一方向与主要表面平行。沟道区具有沿着第一方向延伸的脊的形状，脊包含顶侧和第一侧壁和第二侧壁。栅极电极被安置在沟道区的第一侧壁处，并且栅极电极不在沟道区的第二侧壁处。

Description

半导体器件
背景技术
通常在汽车电子和工业电子中使用的功率晶体管要求低开启状态电阻（Ron）同时确保高电压阻断能力。比如MOS（“金属氧化物半导体”）功率晶体管取决于应用要求应该能够阻断几十到几百或几千伏的漏极到源极电压Vds。MOS功率晶体管典型地传导非常大的电流，所述电流在典型的大约2到20V的栅极-源极电压下可以高达几百安培。
横向功率器件（在其中电流流动主要平行于半导体衬底的主要表面而发生）对于在其中集成诸如开关、桥和控制电路的进一步组件的半导体器件是有用的。
比如，功率晶体管可以被用在DC/DC或AC/DC转换器中以开关通过电感器的电流。在这些转换器中采用在从若干kHz高达若干MHz的范围内的频率。为了减少开关损耗，正在进行尝试以最小化在功率晶体管中的电容。从而可以加速开关操作。
发明内容
依据实施例，半导体器件包括在包含主要表面的半导体衬底中的晶体管。晶体管包括源极区、漏极区、沟道区、以及栅极电极。源极区和漏极区沿着第一方向被安置，所述第一方向与主要表面平行。沟道区被安置在源极区和漏极区之间。沟道区具有沿着第一方向延伸的脊的形状，所述脊包含顶侧以及第一侧壁和第二侧壁。栅极电极被安置在沟道区的第一侧壁处，并且栅极电极不在沟道区的第二侧壁处。
依据进一步实施例，半导体器件包括形成在包括主要表面的半导体衬底中的晶体管。晶体管包括源极区、漏极区、沟道区、与沟道区的第一侧壁相邻的栅极沟槽、被安置在栅极沟槽中的栅极导电材料（所述栅极导电材料被连接到栅极端子）、以及与沟道区的第二侧壁相邻的沟道分离沟槽。沟道分离沟槽用绝缘分离沟槽填充物填充或具有与栅极端子断开的导电填充物。源极区和漏极区沿着第一方向被安置，所述第一方向与主要表面平行。
依据进一步实施例，半导体器件包括形成在包括主要表面的半导体衬底中的晶体管阵列。晶体管阵列包括源极区、漏极区、多个沟道区、以及分别与沟道区中的每一个相邻的多个沟槽，从而两个沟槽与沟道区中的一个相邻。多个沟槽包含栅极沟槽和沟道分离沟槽。半导体器件进一步包括连接到栅极端子的栅极导电材料，所述栅极导电材料被安置在栅极沟槽中。源极区和漏极区沿着第一方向被安置，所述第一方向与主要表面平行。沟槽中的至少一个是沟道分离沟槽，所述沟道分离沟槽要么用电介质材料填充要么具有与栅极端子断开的导电填充物。
通过阅读下面详细的描述并且审视附图，本领域的技术人员将意识到额外的特征和优势。
附图说明
附图被包含以提供实施例的进一步理解，并且附图被结合在该说明书中且组成该说明书的一部分。附图图解主要的实施例并且与描述一起用来解释原理。其它实施例以及许多预期优势将被容易地意识到，因为通过参考下面详细的描述它们变得更好理解。附图的元件不必相对彼此成比例。相似的参考数字指示对应的类似部分。
图1A示出依据实施例的半导体器件在与半导体衬底的主要表面平行的平面中的横截面视图；
图1B示出图1A中所示出的半导体器件的第一横截面视图；
图1C示出图1A中所示出的半导体器件在与图1B的横截面视图的方向垂直的方向中的横截面视图；
图2A示出依据进一步实施例的半导体器件的横截面视图；
图2B示出图2A中所示出的半导体器件的横截面视图；
图2C示出进一步半导体器件的横截面视图；
图3A示出依据实施例的半导体器件的横截面视图；
图3B示出依据进一步实施例的半导体器件的横截面视图；并且
图3C示出依据又一实施例的半导体器件的横截面视图。
具体实施方式
在下面的详细描述中对附图进行参考，附图形成其一部分并且在其中通过图解的方法图解在其中可以实践本发明的特定实施例。在这点上，方向性的术语诸如“顶”、“底”、“前”、“后”、“首”、“尾”等关于正描述的附图的定向被使用。由于本发明的实施例的组件能够被定位在多个不同的定向上，方向性的术语为了图解的目的被使用并且绝不是限制的。要被理解的是可以利用其它实施例并且可以进行结构或逻辑变化而没有脱离由权利要求定义的范围。
实施例的描述不是限制的。特别地，在下文中描述的实施例的元件可以与不同实施例的元件组合。
在下面描述中使用的术语“晶片”、“衬底”或“半导体衬底”可以包含任何具有半导体表面的半导体基的结构。晶片和结构要被理解为包含硅、绝缘体上硅（SOI）、蓝宝石上硅（SOS）、掺杂和不掺杂的半导体、由基底半导体底座支撑的硅的外延层、以及其它半导体结构。半导体不必是硅基的。半导体也能够是硅锗、锗、或砷化镓。依据其它实施例，碳化硅（SiC）或氮化镓（GaN）可以形成半导体衬底材料。
如在该说明书中使用的术语“横向的”和“水平的”意图描述与半导体衬底或半导体本体的第一表面平行的定向。这能够比如是晶片或管芯的表面。
如在该说明书中使用的术语“垂直的”意图描述被布置成与半导体衬底或半导体本体的第一表面垂直的定向。
附图和描述通过紧挨掺杂类型“n”或“p”指示“-”或“+”图解相对掺杂浓度。比如，“n-”表示比“n”掺杂区的掺杂浓度更低的掺杂浓度而“n+”掺杂区具有比“n”掺杂区更高的掺杂浓度。相同的相对掺杂浓度的掺杂区不必具有相同的绝对掺杂浓度。比如，两个不同“n”掺杂区可以具有相同或不同的绝对掺杂浓度。在附图和描述中，为了更好的理解，掺杂的部分经常被指示为是“p”或“n”掺杂的。如要被清楚地理解，该指示绝不是意图进行限制。掺杂类型能够是任意的，只要实现描述的功能。进一步地，在所有的实施例中，掺杂类型能够被颠倒。
如本文所使用，术语“具有”、“含有”、“包含”、“包括”等等是开放型的术语，其指示所陈述的元件或特征的出现但是没有排除额外的元件或特征。冠词“一（a）”、“一个（an）”和“该（the）”意图包含复数以及单数，除非上下文另外清楚地指示。
如在该说明书所采用，术语“耦合的”和/或“电耦合的”不意在表示元件必须直接耦合在一起，居间元件可以被提供在“耦合的”或“电耦合的”元件之间。术语“电连接的”意图描述在电连接在一起的元件之间的低欧姆电连接。
本说明书提及“第一”和“第二”导电类型掺杂剂，半导体部分用其被掺杂。第一导电类型可以是p型并且第二导电类型可以是n型，或反之亦然。如通常所知，取决于源极区和漏极区的掺杂类型或极性，MOSFET可以是n沟道或p沟道MOSFET。比如，在n沟道MOSFET中，源极区和漏极区用n型掺杂剂被掺杂，并且电流方向是从漏极区到源极区。在p沟道MOSFET中，源极区和漏极区用p型掺杂剂被掺杂，并且电流方向是从源极区到漏极区。如要被清楚地理解，在本说明书的上下文之内，掺杂类型可以颠倒。如果使用方向性的语言描述特定的电流路径，该描述要仅被理解成指示电流流动的路径而不是极性，即不论晶体管是p沟道晶体管还是n沟道晶体管。附图可以包含极性敏感的组件，例如二极管。如要被清楚地理解，这些极性敏感的组件的特定布置被给出作为示例并且可以被倒置以实现描述的功能，这取决于第一导电类型表示n型还是p型。
实施例是在特定地提及所谓的常关晶体管（即当没有栅极电压或0V的栅极电压被施加时处于关闭状态的晶体管）时描述的。如要被清楚地理解，本教导能够被等同地施加到常开晶体管，即当没有栅极电压或0V的栅极电压被施加时处于导通状态的晶体管。
图1A示出在与半导体衬底的主要表面平行的平面中取得的半导体器件1或集成电路的横截面视图。半导体器件1包含晶体管200。图1A中所示出的晶体管200包括源极区201、漏极区205、沟道区220、以及漂移区带260。源极区201、漏极区205、以及漂移区带260可以用第一导电类型的掺杂剂（比如n型掺杂剂）掺杂。源极区201和漏极区205的掺杂浓度可以高于漂移区带260的掺杂浓度。沟道区220被布置在源极区201和漂移区带260之间。沟道区220用第二导电类型的掺杂剂（比如用p型掺杂剂）掺杂。漂移区带260可以被布置在沟道区220和漏极区205之间。源极区201、沟道区220、漂移区带260以及漏极区205沿着与半导体衬底的主要表面平行的第一方向被安置。源极区201被连接到源极电极202。漏极区205被连接到漏极电极206。半导体器件1进一步包括栅极电极210。栅极电极210借助于诸如氧化硅的绝缘栅极电介质材料211与沟道区220绝缘。依据实施例，晶体管可以进一步包括与漂移区带260相邻被布置的场板250。场板250借助于诸如氧化硅的绝缘场电介质层251与漂移区带260绝缘。晶体管200是横向晶体管。相应地，从源极区201到漏极区205的电流流动主要在与半导体衬底的主要表面平行的第一方向完成。
当合适的电压被施加到栅极电极210时，反型层在沟道区220和绝缘栅极电介质材料211之间的边界处形成。相应地，晶体管从源极区201经由漂移区带260到漏极区205处于导通状态。在沟道区220中形成的沟道的导电性受栅极电极控制。通过控制在沟道区中形成的沟道的导电性，可以控制从源极区201经由在沟道区220中形成的沟道和漂移区带260到漏极区205的电流流动。
当晶体管被切断时，没有导电沟道在沟道区220和绝缘栅极电介质材料211之间的边界处被形成，从而亚阈值电流流动。
依据实施例，晶体管可以被实施为常关晶体管。依据进一步实施例，晶体管可以被实施为常开晶体管。在这种情形下，沟道区220可以用第一导电类型的掺杂剂（比如用n型掺杂剂）掺杂。
在关闭状态中适当的电压可以被施加到场板。比如，场板250可以被电连接到源极端子，场板250也被电连接到源极电极202。在关闭状态，场板250耗尽来自漂移区带260的电荷载流子从而改进晶体管200的击穿电压特性。与没有场板的器件相比，在包括场板250的晶体管200中可以增加漂移区带260的掺杂浓度而没有恶化击穿电压特性。由于漂移区带更高的掺杂浓度，开启电阻RDSon被进一步减小从而导致改进的器件特性。
半导体器件1进一步包括沟道分离沟槽270。由于沟道分离沟槽270的出现，沟道区220的宽度被减小。从而实施全耗尽的晶体管是可能的。在具有相对高的击穿电压的晶体管中，由于开启状态电阻主要由漂移区的属性确定，有源沟道的宽度的减少不降低开启状态电阻（Ron×A）。分离沟槽可以用绝缘材料填充或可以包含与栅极电位断开的导电填充物。相应地，包含栅极电极的有源沟槽的数量在半导体器件1中被减少。
图1B图解沿着第一方向在I和I?（如也在图1A中所指示）之间的半导体器件1的横截面视图。取得图1B的横截面视图以横截沟道区220和漂移区带260。如由点线指示，栅极沟槽212在附图描绘的平面前面和后面的平面中被安置成与沟道区220相邻。进一步地，场板沟槽252可以在附图描绘的平面前面和后面的平面中被安置成与漂移区带260相邻。栅极沟槽212和场板沟槽252从主要表面110在衬底100的深度方向中延伸。因此，栅极电极与沟道区220的至少两侧相邻。进一步地，沟道区220具有第一脊的形状。由于场板沟槽252的出现，依据实施例，漂移区带260可以具有第二脊的形状。
源极区201从主要表面110延伸进入衬底100的深度方向，即关于主要表面110垂直延伸。漏极区205同样地从主要表面110在衬底100的深度方向中延伸。图1B进一步示出被安置在沟道区220的下方以及在漂移区带260的一部分的下方的本体连接注入区225。本体连接注入部分225将沟道区电连接到源极电极202并且进一步抑制或恶化寄生双极型晶体管。而且，本体连接注入部分225可以在漂移区带260的下方延伸，从而在晶体管的关闭状态中漂移区带260可以被更容易地耗尽。本体连接注入部分225可以用第二导电类型的掺杂剂以比沟道区更高的浓度被掺杂。
图1C图解在II和II?（如也在图1A中所图解）之间取得的半导体器件的横截面视图。在II和II?之间的方向与第一方向垂直。如在图1C中所示出，沟道区220具有脊的形状，所述脊具有宽度d1。比如，脊可以具有顶侧、第一侧壁220b和第二侧壁220a。侧壁220b、220a可以关于主要表面110垂直延伸或以大于75°的角度延伸。
依据图1C的实施例，半导体器件包括晶体管200。晶体管200包括源极区201、漏极区205、沟道区220和栅极电极210。沟道区220沿着第一方向被安置在源极区201和漏极区205之间，所述第一方向与主要表面平行。沟道区220具有沿着第一方向延伸的脊的形状，所述脊包含顶侧220c、第一侧壁220b和第二侧壁220a。栅极电极210与沟道区的第一侧壁220b相邻，并且栅极电极不在沟道区220的第二侧壁220a处。
当半导体器件1被操作在开启状态时，导电反型层沿着第一侧壁220b被形成。由于在沟道区220的第二侧壁220a处缺失栅极电极，没有导电反型层在第二侧壁220a处形成。
半导体器件1可以包括与沟道区220的第二侧壁220b相邻的沟道分离元件。
比如，沟道分离元件可以包括用分离沟槽填充物填充的沟道分离沟槽270。
依据进一步实施例，沟道分离沟槽270可以包含导电填充物274和被安置在导电填充物274和沟道区220之间的分离电介质275。分离电介质275的厚度可以大于在栅极电极210和沟道区220之间的栅极电介质211的厚度。
依据实施例，源极区201和沟道分离沟槽270的导电填充物274可以被连接到源极端子280。
若干栅极沟槽212的宽度和若干沟道分离沟槽270的宽度可以彼此不同。
依据实施例，沟道区220的宽度d1满足下面的关系：d1≤ld，其中ld指代在栅极电介质层211和沟道区220之间的界面处形成的耗尽区带的长度。比如，耗尽区带的宽度可以被确定为：
其中εs指代半导体材料的介电常数（对于硅：11.9×ε0，ε0=8.85×10-14 F/cm），k指代玻尔兹曼（Boltzmann）常数（1.38066×10-23 J/k），T指代温度，ln指代自然对数，NA指代半导体本体的杂质浓度，ni指代本征载流子浓度（对于硅在27℃：1.45×1010 cm-3），并且q指代基本电荷（1.6×10-19 C）。
通常，耗尽区带的长度取决于栅极电压而变化。假定：在晶体管中，在对应于阈值电压的栅极电压处耗尽区带的长度对应于耗尽区带的最大宽度。比如，沿着半导体衬底100的主要表面110，第一脊的宽度可以近似是10到200nm，比如20到60nm。
而且，长度和宽度的比例可以满足下面的关系：s1/d1>2.0，其中s1指代与栅极电极210交叠的第一脊的长度，或换句话说，沿着第一方向测量的沟道区的长度，如也在图1中所图解。依据进一步实施例，s1/d1>2.5。
依据在其中宽度d1≤ld的实施例，晶体管200是所谓的“全耗尽的”晶体管，在其中当栅极电极210被设置到开启电压时沟道区220被全部耗尽。在这样的晶体管中，可以实现最优的亚阈值电压并且可以高效地抑制短沟道效应，从而导致改进的器件特性。
由于栅极电极不在沟道区的第二侧壁的特征，栅极电容可以被减小从而导致减少的开关损耗。依据实施例，沟道分离沟槽包含导电填充物以及安置在导电填充物274和沟道区220之间的分离电介质275。分离电介质275的厚度可以大于在栅极电极210和沟道区220之间的栅极电介质211的厚度。如已经被发现，由于该特征，施加到栅极电极的电压在栅极电极处变得几乎完全有效。更具体地，由于分离电介质275相比于栅极电介质211增加的厚度，在沟道分离沟槽270中的导电填充物274被阻止充当占用部分施加的栅极电压的分压器。因此，可以进一步增加晶体管的电流-电压特性的亚阈值斜率的陡峭度。
依据进一步实施例，沟道分离沟槽270可以用绝缘材料填充。由于对称性的原因，这样的分离沟槽表现得像具有无限厚度的绝缘体的SOI（绝缘体上硅）衬底。
依据实施例，漂移区带260可以包括平表面，所述平表面不被图案化以形成脊。依据进一步实施例，场板250可以被布置在沟槽252中从而漂移区带260包括脊。在包含场板250的晶体管中，可以期望的是使用具有宽度d2的漂移区带260（所述宽度d2大于沟道区的宽度d1）以限制例如输出电容Coss。所以场板沟槽252可以以更大距离被安置，从而被安置在相邻的场板沟槽252之间的漂移区带260的部分具有更大的宽度。依据另一实施例，d2可以被选择为小于d1。典型地，在场板和漂移区带之间的场电介质层的厚度厚于栅极电介质层的厚度以增加漏极-源极击穿电压。与栅极沟槽和分离沟槽相比，这可以导致场板沟槽的更大的间距。
为了改进在沟道区中半导体器件的特性并且进一步改进在漂移区带中的器件特性，可以使用适当的刻蚀掩膜以提供第一脊和第二脊的不同宽度来完成图案化栅极电极和场板。
如将会在本文以下被进一步解释，这可以通过形成一组具有更小间距的栅极沟槽212并且通过形成一组具有更大间距的场板沟槽252来完成。依据实施例，栅极沟槽212和场板沟槽252可以彼此分离。依据进一步实施例，栅极沟槽212和场板沟槽252可以被合并以形成一个具有不同宽度的单个沟槽。
在图1A到1C图解的半导体器件实施横向功率晶体管。由于它们可以以简单的方式被集成，它们可以在DC/DC或AC/DC转换器中被采用。进一步地，它们可以实现高电流密度从而它们可以被用于小功率以及在10V和几百伏之间的电压。
图2A示出依据实施例的半导体器件或集成电路在与半导体衬底的主要表面平行的平面中的横截面视图。半导体器件包含沟道分离沟槽270。在图2A的实施例中，沟道分离沟槽270包含导电填充物274。分离电介质层275被安置在导电填充物274和相邻的沟道区220之间。导电填充物274被连接到端子290，所述端子290被连接到与栅极电位不同的电位。比如，导电填充物274可以被连接到源极端子或可以被接地。从而可以进一步减小栅极-漏极电容。分离电介质层275可以具有比栅极电介质层211更大的厚度。依据进一步实施例，分离电介质层275的厚度可以等于栅极电介质层211的厚度。依据实施例，在与漏极区205相邻的部分211d处的栅极电介质层211的厚度可以大于在与沟道区220相邻的部分处的栅极电介质层211的厚度。在图2A中所示出的实施例的进一步组件与图1A的那些类似。
图2B示出图2A中示出的半导体器件在II和II'（如也在图2A中所指示）之间的横截面视图。如所示出，栅极电极210被安置成与沟道区220的第一侧壁220b相邻。进一步地，沟道分离沟槽270与沟道区220中的每一个的第二侧壁220a相邻。导电填充物274被安置在沟道分离沟槽270中。
栅极电极210被连接到栅极端子285。进一步地，沟道分离沟槽270的导电填充物274被连接到不同于栅极端子285的端子290。因此，可以减小栅极漏极电容。而且，分离电介质层275的厚度可以大于栅极电介质层211的厚度。从而可以进一步增加晶体管的电流-电压特性的亚阈值斜率的陡峭度。
以上解释的概念可以以各种方法被修改。比如，漂移区带260可以以不同的方式被实施。进一步地，半导体器件可以被实施为没有包含导电填充物的场板。比如，半导体器件可以比如包括如传统的在第一方向延伸的交替的p掺杂和n掺杂的补偿区域的堆叠。从而补偿器件或超结器件可以被实施。依据更进一步实施例，漂移区可以被省掉。
图2C示出实施例的横截面视图，依据其漏极区205直接与沟道区220相邻而没有安置在沟道区和漏极区205之间的漂移区带260。依据图2C中所示出的实施，可以增加栅极电介质层211在与漏极区205相邻的部分211d处的厚度以进一步减少栅极-漏极电容。
图3A示出半导体器件或集成电路的进一步实施例的横截面视图。图3A的横截面视图平行于衬底的主要表面被取得。依据图3A的实施例，包含导电填充物274的沟道分离沟槽270被连接到场板沟槽以形成延伸的场板沟槽273。因而，依据图3A的实施例的半导体器件包含栅极沟槽212，所述栅极沟槽212包含借助于栅极电介质211与相邻的沟道区绝缘的栅极电极210。半导体器件进一步包括延伸到沟道区220的延伸的场板沟槽273。延伸的场板沟槽用可以被连接到源极端子280的导电填充物274填充。延伸的场板沟槽273的导电填充物274借助于场电介质层251与沟道区绝缘。场电介质层251的厚度可以大于栅极电介质层211的厚度。沟道区220包含第一侧壁220b和第二侧壁220a，栅极电极210与第一侧壁相邻。进一步地，导电填充物274与脊的第二侧壁220a相邻。由于导电填充物274不连接到栅极端子，当合适的栅极电压被施加到栅极端子285时耗尽区只在第一侧壁220b与栅极电介质211的界面处形成。在图3A所示出的半导体器件中，可以减小有效的栅极区域，从而导致减少的栅极电容。
图3B示出依据进一步实施例的半导体器件或集成电路的横截面视图。以如图3A中所示出的类似的方式，栅极沟槽212和沟道分离沟槽270以交替的方式被安置，从而一个栅极沟槽212与沟道区220中的每一个的第一侧壁220b相邻并且一个沟道分离沟槽270a、270b与沟道区中的每一个的第二侧壁220a相邻。如在图3B中进一步示出，沟道分离沟槽270包含用绝缘材料填充的第一沟道分离沟槽270a和用导电填充物273和在导电填充物273与沟道区220之间的场电介质层251填充的第二沟道分离沟槽270b。如在图3B中进一步图解，第二沟道分离沟槽270b被实施为延伸的场板沟槽273，所述延伸的场板沟槽273延伸到漂移区带260以形成场板沟槽。场电介质层251的厚度可以大于栅极电介质层211的厚度。
图3C示出依据进一步实施例的半导体器件或集成电路的横截面视图。如所图解，与沟道区220相邻的分离电介质层275可以具有近似等于栅极电介质层211厚度的厚度。而且，第二沟道分离沟槽被实施为延伸的场板沟槽273，在其中分离沟槽的导电填充物274延伸到漂移区带260以形成场板。分离电介质层275在与漂移区带260相邻的区中比在与沟道区220相邻的区中具有更大的厚度。如已在上文中所讨论，半导体器件1包括形成在包括主要表面110的半导体衬底100中的晶体管200的阵列。晶体管200的阵列包括源极区201、漏极区205、多个沟道区220、以及与沟道区220中的每一个相邻的多个沟槽212、270，从而两个沟槽与沟道区中的一个相邻。多个沟槽包含栅极沟槽212和沟道分离沟槽270。半导体器件包括连接到栅极端子285的栅极导电材料210，并且栅极导电材料210被安置在栅极沟槽212中。沟道区220沿着第一方向被安置在源极区201和漏极区205之间，第一方向与主要表面110平行。沟槽中的至少一个是沟道分离沟槽270，沟道分离沟槽270要么用电介质材料272填充要么用电介质材料装衬并且用与栅极端子285断开的导电填充物274填充。
依据实施例，栅极沟槽212和沟道分离沟槽270以交替的方式被安置，从而一个栅极沟槽212和一个沟道分离沟槽270与沟道区220中的每一个的不同的侧壁220b、220a相邻。
依据实施例，沟道分离沟槽270包含用绝缘材料填充的第一沟道分离沟槽270a和用导电填充物274和在导电填充物274与沟道区220之间的分离电介质层275填充的第二沟道分离沟槽270b。
因而，有源栅极沟槽的数量在半导体器件1中被减少。导电的反型层只在沟道区的一个侧壁处形成。在具有更高击穿电压的器件中，有源沟道的密度的减少应该对Ron×A具有小的影响，Ron×A主要由漂移区带260的属性确定。相应地，可以减小栅极电容而没有恶化开启状态电阻（Ron×A）。进一步地，依据实施例，可以减小栅极电容而没有恶化电流-电压特性的亚阈值斜率。
在其它实施例中，晶体管可以被实施为常开器件。在该情形下，沟道区可以与源极区和漏极区具有相同的导电类型。
所描述的晶体管指的是MOSFET（“金属氧化物半导体场效应晶体管”），在其中诸如氧化硅的栅极电介质材料被安置在栅极电极和沟道区之间。依据进一步实施例，晶体管可以是JFET（“结型场效应晶体管”），在其中栅极电极直接与沟道区相邻而没有被安置在栅极电极和沟道区之间的栅极电介质材料。依据该实施例，沟道区可以用n型掺杂剂掺杂。栅极电极可以通过p掺杂的半导体材料（比如p掺杂的多晶硅）实施。半导体器件进一步的组件可以以如以上已经描述的方式实施。
依据进一步实施例，半导体器件可以进一步包括到第二主要表面的接触，所述第二主要表面与半导体衬底100的第一主要表面110相对。依据实施例，电耦合到源极区201的源极电极202可以延伸到第一主要表面110并且电耦合到漏极区205的漏极电极206可以延伸到与第一主要表面110相对的第二主要表面。
虽然以上已描述了本发明的实施例，但是显然的是可以实施进一步实施例。比如，进一步实施例可以包括在权利要求中所列举的特征的任何子组合或在以上给定的示例中所描述的元件的任何子组合。相应地，所附权利要求的这种精神和范围不应该被限制到本文含有的实施例的描述。

Claims (23)

1.一种半导体器件，所述半导体器件包括在包含主要表面的半导体衬底中的晶体管，所述晶体管包括：
源极区；
漏极区；
沟道区；以及
栅极电极，源极区和漏极区沿着第一方向被安置，第一方向与主要表面平行，沟道区被安置在源极区和漏极区之间，沟道区具有沿着第一方向延伸的脊的形状，脊包含顶侧和第一侧壁和第二侧壁，栅极电极被安置在沟道区的第一侧壁处，并且栅极电极不在沟道区的第二侧壁处。
2.依据权利要求1的所述半导体器件，其中导电反型层在开启状态沿着第一侧壁被形成。
3.依据权利要求1的所述半导体器件，进一步包括与沟道区的第二侧壁相邻的沟道分离元件。
4.依据权利要求3的所述半导体器件，其中沟道分离元件包括用分离沟槽填充物填充的沟道分离沟槽。
5.依据权利要求3的所述半导体器件，其中沟道分离元件包括沟道分离沟槽，所述沟道分离沟槽包含导电填充物以及安置在导电填充物和沟道区之间的分离电介质。
6.依据权利要求5的所述半导体器件，其中分离电介质的厚度大于在栅极电极和沟道区之间的栅极电介质的厚度。
7.依据权利要求5的所述半导体器件，其中源极区和沟道分离沟槽的导电填充物被电连接到源极端子。
8.依据权利要求1的所述半导体器件，进一步包括在沟道区和漏极区之间的漂移区带。
9.依据权利要求4的所述半导体器件，进一步包括漂移区带和在漂移区带处的场板，其中场板被连接到沟道分离沟槽。
10.依据权利要求1的所述半导体器件，其中脊的宽度d是：d<ld，其中ld指代在脊和栅极电极之间的界面处形成的耗尽区带的长度。
11.一种集成电路，所述集成电路包括依据权利要求1的所述半导体器件。
12.一种半导体器件，所述半导体器件包括在包括主要表面的半导体衬底中形成的晶体管，所述晶体管包括：
源极区；
漏极区；
沟道区；
栅极沟槽，与沟道区的第一侧壁相邻；
栅极导电材料，安置在栅极沟槽中，栅极导电材料被连接到栅极端子；以及
沟道分离沟槽，与沟道区的第二侧壁相邻，沟道分离沟槽用绝缘分离沟槽填充物填充或具有与栅极端子断开的导电填充物，
其中源极区和漏极区沿着第一方向被安置，第一方向与主要表面平行。
13.依据权利要求12的所述半导体器件，其中导电反型层在开启状态沿着第一侧壁被形成。
14.依据权利要求12的所述半导体器件，其中沟道分离沟槽包含导电填充物以及安置在导电填充物和沟道区之间的分离电介质。
15.依据权利要求14的所述半导体器件，其中分离电介质的厚度大于在栅极电极和沟道区之间的栅极电介质的厚度。
16.依据权利要求14的所述半导体器件，其中源极区和沟道分离沟槽的导电填充物被连接到源极端子。
17.依据权利要求14的所述半导体器件，进一步包括场板，其中场板被连接到沟道分离沟槽的导电填充物。
18.依据权利要求12的所述半导体器件，进一步包括在沟道区和漏极区之间的漂移区带。
19.一种集成电路，所述集成电路包括依据权利要求12的所述半导体器件。
20.一种半导体器件，所述半导体器件包括在包括主要表面的半导体衬底中形成的晶体管阵列，所述晶体管阵列包括：
源极区；
漏极区；
多个沟道区；
多个沟槽，分别与沟道区中的每一个相邻，从而两个沟槽与沟道区中的一个相邻，多个沟槽包含栅极沟槽和沟道分离沟槽；以及
栅极导电材料，连接到栅极端子，栅极导电材料被安置在栅极沟槽中，
其中源极区和漏极区沿着第一方向被安置，第一方向与主要表面平行，
其中沟槽中的至少一个是沟道分离沟槽，所述沟道分离沟槽要么用电介质材料填充要么具有与栅极端子断开的导电填充物。
21.依据权利要求20的所述半导体器件，其中栅极沟槽和沟道分离沟槽以交替的方式被安置，从而一个栅极沟槽和一个沟道分离沟槽与沟道区中的每一个的不同侧壁相邻。
22.依据权利要求21的所述半导体器件，其中沟道分离沟槽包含用绝缘材料填充的第一沟道分离沟槽和用导电填充物和在导电填充物与沟道区之间的分离电介质层填充的第二沟道分离沟槽。
23.一种集成电路，所述集成电路包括依据权利要求20的所述半导体器件。
CN201410543952.8A 2013-10-15 2014-10-15 半导体器件 Expired - Fee Related CN104576737B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US14/053633 2013-10-15
US14/053,633 US9401399B2 (en) 2013-10-15 2013-10-15 Semiconductor device

Publications (2)

Publication Number Publication Date
CN104576737A true CN104576737A (zh) 2015-04-29
CN104576737B CN104576737B (zh) 2018-06-05

Family

ID=52808964

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201410543952.8A Expired - Fee Related CN104576737B (zh) 2013-10-15 2014-10-15 半导体器件

Country Status (3)

Country Link
US (2) US9401399B2 (zh)
CN (1) CN104576737B (zh)
DE (1) DE102014114836B4 (zh)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108010965A (zh) * 2016-10-30 2018-05-08 朱江 一种沟槽mis半导体装置及其制造方法
CN109564876A (zh) * 2016-08-10 2019-04-02 日产自动车株式会社 半导体装置
CN111192923A (zh) * 2018-11-14 2020-05-22 三星电子株式会社 包括源极/漏极区的半导体器件

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102014114184B4 (de) * 2014-09-30 2018-07-05 Infineon Technologies Ag Verfahren zum Herstellen einer Halbleitervorrichtung und Halbleitervorrichtung
DE102016106872A1 (de) 2016-04-13 2017-10-19 Infineon Technologies Ag Verfahren zum herstellen einer integrierten schaltung einschliesslich eines lateralen graben-transistors und eines logikschaltungselements
DE102016110645A1 (de) * 2016-06-09 2017-12-14 Infineon Technologies Ag Halbleitervorrichtung mit einem eine erste feldplatte und eine zweite feldplatte aufweisenden transistor
EP3916810A1 (en) * 2020-05-28 2021-12-01 Infineon Technologies Dresden GmbH & Co . KG Semiconductor device and method of producing the same
EP3916809A1 (en) * 2020-05-28 2021-12-01 Infineon Technologies Dresden GmbH & Co . KG Semiconductor device and method of producing the same

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20010045599A1 (en) * 2000-05-20 2001-11-29 Hueting Raymond J.E. Semiconductor device
US6670673B2 (en) * 2001-04-18 2003-12-30 Denso Corporation Semiconductor device and method for manufacturing semiconductor device
CN101185169A (zh) * 2005-04-06 2008-05-21 飞兆半导体公司 沟栅场效应晶体管及其形成方法
US20090020852A1 (en) * 2007-07-17 2009-01-22 Mitsubishi Electric Corporation Semiconductor device

Family Cites Families (49)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5828101A (en) 1995-03-30 1998-10-27 Kabushiki Kaisha Toshiba Three-terminal semiconductor device and related semiconductor devices
JP3405681B2 (ja) 1997-07-31 2003-05-12 株式会社東芝 半導体装置
DE19818300C1 (de) 1998-04-23 1999-07-22 Siemens Ag Lateraler Hochvolt-Seitenwandtransistor
JP3971062B2 (ja) 1999-07-29 2007-09-05 株式会社東芝 高耐圧半導体装置
JP3356162B2 (ja) 1999-10-19 2002-12-09 株式会社デンソー 半導体装置及びその製造方法
JP4528460B2 (ja) * 2000-06-30 2010-08-18 株式会社東芝 半導体素子
US7786533B2 (en) 2001-09-07 2010-08-31 Power Integrations, Inc. High-voltage vertical transistor with edge termination structure
JP2003203930A (ja) 2002-01-08 2003-07-18 Nec Compound Semiconductor Devices Ltd ショットキーゲート電界効果型トランジスタ
US6589845B1 (en) 2002-07-16 2003-07-08 Semiconductor Components Industries Llc Method of forming a semiconductor device and structure therefor
DE10313712B4 (de) 2003-03-27 2008-04-03 Infineon Technologies Ag Laterales mittels Feldeffekt steuerbares Halbleiterbauelement für HF-Anwendungen
US7714384B2 (en) 2003-09-15 2010-05-11 Seliskar John J Castellated gate MOSFET device capable of fully-depleted operation
US7279744B2 (en) * 2003-11-14 2007-10-09 Agere Systems Inc. Control of hot carrier injection in a metal-oxide semiconductor device
US7368777B2 (en) * 2003-12-30 2008-05-06 Fairchild Semiconductor Corporation Accumulation device with charge balance structure and method of forming the same
US7126166B2 (en) 2004-03-11 2006-10-24 Semiconductor Components Industries, L.L.C. High voltage lateral FET structure with improved on resistance performance
US7573078B2 (en) 2004-05-11 2009-08-11 Cree, Inc. Wide bandgap transistors with multiple field plates
US7132333B2 (en) 2004-09-10 2006-11-07 Infineon Technologies Ag Transistor, memory cell array and method of manufacturing a transistor
DE102004031385B4 (de) 2004-06-29 2010-12-09 Qimonda Ag Verfahren zur Herstellung von Stegfeldeffekttransistoren in einer DRAM-Speicherzellenanordnung, Feldeffekttransistoren mit gekrümmtem Kanal und DRAM-Speicherzellenanordnung
DE102004047772B4 (de) 2004-09-30 2018-12-13 Infineon Technologies Ag Lateraler Halbleitertransistor
DE102004056772B4 (de) 2004-11-24 2007-01-11 Infineon Technologies Austria Ag Laterale Halbleiterbauelemente mit hoher Spannungsfestigkeit und Verfahren zur Herstellung derselben
US11791385B2 (en) 2005-03-11 2023-10-17 Wolfspeed, Inc. Wide bandgap transistors with gate-source field plates
US7382019B2 (en) 2005-04-26 2008-06-03 Fairchild Semiconductor Corporation Trench gate FETs with reduced gate to drain charge
DE102006053145B4 (de) 2005-11-14 2014-07-10 Denso Corporation Halbleitervorrichtung mit Trennungsbereich
JP4304198B2 (ja) 2006-09-15 2009-07-29 株式会社東芝 半導体装置
JP2008124346A (ja) 2006-11-14 2008-05-29 Toshiba Corp 電力用半導体素子
KR20090116702A (ko) * 2007-01-09 2009-11-11 맥스파워 세미컨덕터 인크. 반도체 디바이스
JP2008227474A (ja) * 2007-02-13 2008-09-25 Toshiba Corp 半導体装置
WO2009012536A1 (en) 2007-07-20 2009-01-29 Interuniversitair Microelektronica Centrum Damascene contacts on iii-v cmos devices
US7622354B2 (en) 2007-08-31 2009-11-24 Qimonda Ag Integrated circuit and method of manufacturing an integrated circuit
US20090108343A1 (en) 2007-10-31 2009-04-30 Gennadiy Nemtsev Semiconductor component and method of manufacture
TWI368324B (en) 2007-11-06 2012-07-11 Nanya Technology Corp Recessed-gate transistor device and mehtod of making the same
US8076719B2 (en) 2008-02-14 2011-12-13 Maxpower Semiconductor, Inc. Semiconductor device structures and related processes
US7888732B2 (en) 2008-04-11 2011-02-15 Texas Instruments Incorporated Lateral drain-extended MOSFET having channel along sidewall of drain extension dielectric
US8193565B2 (en) 2008-04-18 2012-06-05 Fairchild Semiconductor Corporation Multi-level lateral floating coupled capacitor transistor structures
JP5385679B2 (ja) * 2008-05-16 2014-01-08 旭化成エレクトロニクス株式会社 横方向半導体デバイスおよびその製造方法
CN101419981A (zh) 2008-12-04 2009-04-29 电子科技大学 一种槽栅soi ligbt器件
US7884394B2 (en) 2009-02-09 2011-02-08 Transphorm Inc. III-nitride devices and circuits
JP2011009595A (ja) 2009-06-29 2011-01-13 Renesas Electronics Corp 半導体装置および半導体装置の製造方法
US8115253B2 (en) 2009-09-10 2012-02-14 United Microelectronics Corp. Ultra high voltage MOS transistor device
US8178922B2 (en) 2010-01-14 2012-05-15 Force Mos Technology Co., Ltd. Trench MOSFET with ultra high cell density and manufacture thereof
CN102157493B (zh) 2010-02-11 2013-07-24 上海华虹Nec电子有限公司 金属塞及其制造方法
WO2011111500A1 (ja) * 2010-03-09 2011-09-15 富士電機システムズ株式会社 半導体装置
JP5580150B2 (ja) * 2010-09-09 2014-08-27 株式会社東芝 半導体装置
CN102412295A (zh) 2010-09-21 2012-04-11 株式会社东芝 半导体装置及其制造方法
US8536648B2 (en) * 2011-02-03 2013-09-17 Infineon Technologies Ag Drain extended field effect transistors and methods of formation thereof
US9941403B2 (en) 2012-09-26 2018-04-10 Infineon Technologies Ag Semiconductor device and method for manufacturing a semiconductor device
US9799762B2 (en) 2012-12-03 2017-10-24 Infineon Technologies Ag Semiconductor device and method of manufacturing a semiconductor device
US9006811B2 (en) 2012-12-03 2015-04-14 Infineon Technologies Austria Ag Semiconductor device including a fin and a drain extension region and manufacturing method
US8847311B2 (en) 2012-12-31 2014-09-30 Infineon Technologies Ag Semiconductor device and method of manufacturing a semiconductor device
US9306058B2 (en) 2013-10-02 2016-04-05 Infineon Technologies Ag Integrated circuit and method of manufacturing an integrated circuit

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20010045599A1 (en) * 2000-05-20 2001-11-29 Hueting Raymond J.E. Semiconductor device
US6670673B2 (en) * 2001-04-18 2003-12-30 Denso Corporation Semiconductor device and method for manufacturing semiconductor device
CN101185169A (zh) * 2005-04-06 2008-05-21 飞兆半导体公司 沟栅场效应晶体管及其形成方法
US20090020852A1 (en) * 2007-07-17 2009-01-22 Mitsubishi Electric Corporation Semiconductor device

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109564876A (zh) * 2016-08-10 2019-04-02 日产自动车株式会社 半导体装置
CN109564876B (zh) * 2016-08-10 2020-02-21 日产自动车株式会社 半导体装置
CN108010965A (zh) * 2016-10-30 2018-05-08 朱江 一种沟槽mis半导体装置及其制造方法
CN111192923A (zh) * 2018-11-14 2020-05-22 三星电子株式会社 包括源极/漏极区的半导体器件

Also Published As

Publication number Publication date
DE102014114836B4 (de) 2018-05-09
US9401399B2 (en) 2016-07-26
US20160300944A1 (en) 2016-10-13
DE102014114836A1 (de) 2015-06-18
CN104576737B (zh) 2018-06-05
US20150102404A1 (en) 2015-04-16
US9893178B2 (en) 2018-02-13

Similar Documents

Publication Publication Date Title
CN107086247B (zh) 包括温度传感器的半导体装置及其制造方法和电路
CN104576737B (zh) 半导体器件
US9799762B2 (en) Semiconductor device and method of manufacturing a semiconductor device
US9419130B2 (en) Semiconductor device and integrated circuit
CN103681864A (zh) 半导体器件和用于制作半导体器件的方法
US9825148B2 (en) Semiconductor device comprising an isolation trench
US9614064B2 (en) Semiconductor device and integrated circuit
US9449968B2 (en) Method for manufacturing a semiconductor device and a semiconductor device
US9324817B2 (en) Method for forming a transistor device having a field electrode
US9985126B2 (en) Semiconductor device comprising a first gate electrode and a second gate electrode
CN106057898B (zh) 包括晶体管的半导体器件
US20190334000A1 (en) Transistor Component
CN106169464A (zh) 包括功率晶体管和电压限制装置的晶体管布置
US10128367B2 (en) Transistor device with increased gate-drain capacitance
CN104600067B (zh) 集成电路和制造集成电路的方法
US20160155802A1 (en) Semiconductor Device Having Ridges Running in Different Directions
US10068975B2 (en) Semiconductor device having field plate structures, source regions and gate electrode structures between the field plate structures

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant
CF01 Termination of patent right due to non-payment of annual fee
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20180605

Termination date: 20191015