CN104617167A - Method for forming photovoltaic device, and photovoltaic device - Google Patents

Method for forming photovoltaic device, and photovoltaic device Download PDF

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CN104617167A
CN104617167A CN201410561798.7A CN201410561798A CN104617167A CN 104617167 A CN104617167 A CN 104617167A CN 201410561798 A CN201410561798 A CN 201410561798A CN 104617167 A CN104617167 A CN 104617167A
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conducting material
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conductivity
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type semi
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C·巴伊拉姆
B·海克麦特朔-塔巴里
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International Business Machines Corp
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02Details
    • H01L31/0236Special surface textures
    • H01L31/02363Special surface textures of the semiconductor body itself, e.g. textured active layers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/0248Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies
    • H01L31/0256Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by the material
    • H01L31/0264Inorganic materials
    • H01L31/0304Inorganic materials including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L31/03046Inorganic materials including, apart from doping materials or other impurities, only AIIIBV compounds including ternary or quaternary compounds, e.g. GaAlAs, InGaAs, InGaAsP
    • H01L31/03048Inorganic materials including, apart from doping materials or other impurities, only AIIIBV compounds including ternary or quaternary compounds, e.g. GaAlAs, InGaAs, InGaAsP comprising a nitride compounds, e.g. InGaN
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/04Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
    • H01L31/06Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier
    • H01L31/072Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the PN heterojunction type
    • H01L31/074Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the PN heterojunction type comprising a heterojunction with an element of Group IV of the Periodic System, e.g. ITO/Si, GaAs/Si or CdTe/Si solar cells
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02EREDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00Energy generation through renewable energy sources
    • Y02E10/50Photovoltaic [PV] energy
    • Y02E10/544Solar cells from Group III-V materials
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02PCLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50Manufacturing or production processes characterised by the final manufactured product

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  • Condensed Matter Physics & Semiconductors (AREA)
  • Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Life Sciences & Earth Sciences (AREA)
  • Sustainable Development (AREA)
  • Sustainable Energy (AREA)
  • Photovoltaic Devices (AREA)

Abstract

The invention relates to a method for forming a photovoltaic device, and the photovoltaic device. The photovoltaic device comprises a single-unit solar cell which comprises an absorption layer made of IV-type semiconductor materials with the first conductivity, and an emitter electrode layer made of III-V type semiconductor materials with the second conductivity. The III-V type semiconductor materials are amorphous bodies, and the thickness of the III-V type semiconductor materials is not greater than 50 nm.

Description

Form method and the photovoltaic device of photovoltaic device
Related application
The application relates to the U. S. application 13/290404 of the jointly co-pending and common transfer submitted on November 7th, 2011, is incorporated herein by its full content by reference.
Technical field
The application relates to photovoltaic device, and more specifically, relates to the photovoltaic device of such as solar cell.
Background technology
Photovoltaic device is the device power conversion of incident photon being become electromotive force (e.m.f.).Typical photovoltaic device comprises solar cell, and solar cell is configured to become electric energy by from the power conversion in the electromagnetic radiation of the sun.Due to its high efficiency and irradiation stability, the power that the multijunction solar cell comprising compound semiconductor can be used in space generates.
Summary of the invention
In one embodiment, a kind of photovoltaic device is provided, described photovoltaic device comprises unijunction solar cell, described unijunction solar cell by having the absorbed layer of IV type semi-conducting material of the first conductivity-type, the emitter layer of III-V type semi-conducting material with the second conductivity-type provides, wherein, described III-V type semi-conducting material is noncrystal and has the thickness being not more than 50nm.
On the other hand, a kind of method forming photovoltaic device is provided, wherein, described photovoltaic device is unijunction solar cell, and described unijunction solar cell is provided by the absorbed layer of the emitter layer of the III-V type semi-conducting material of the first conductivity and the IV type semi-conducting material of the second conductivity.In one embodiment, described method comprises the absorbed layer providing the crystal IV type semi-conducting material with the first conductivity, and on the surface of described absorbed layer, form the emitter layer with the noncrystal III-V type semi-conducting material of the second conductivity.
Accompanying drawing explanation
The following detailed description that mode provides by way of example is not intended to limit the present invention, and following detailed description is best understood with reference to accompanying drawing, wherein, and element and part like similar reference number representation class, wherein:
Fig. 1 is the side cross-sectional views of the unijunction solar cell of an embodiment according to the application, and this unijunction solar cell is provided by the absorbed layer of IV type semi-conducting material and the emitter layer of noncrystal III-V type semi-conducting material.
Fig. 2 is the side cross-sectional views of the initial configuration of an embodiment according to the application, this initial configuration can be utilized to be formed and be similar to unijunction solar cell depicted in figure 1, wherein, this initial configuration comprises the substrate of IV type semi-conducting material, and this substrate provides the absorbed layer of unijunction solar cell.
Fig. 3 is the side cross-sectional views of the substrate of the veining IV type that the depicts semi-conducting material of an embodiment according to the application.
Fig. 4 depicts according to the embodiment of the application the side cross-sectional views forming noncrystal III-V type semi-conducting material on the texturizing surfaces of IV type semiconductive material substrate, wherein, the emitter layer that unijunction solar cell is provided at least partially of noncrystal III-V type semi-conducting material.
Fig. 5 is the side cross-sectional views depicting another embodiment of the application according to the application, and wherein, before the growth of noncrystal III-V emitter layer, the passivation layer on absorbed layer top is patterned.
Fig. 6 forms the side cross-sectional views of back contacts to absorbed layer according to the depicting of an embodiment of the application.
Fig. 7 is the side cross-sectional views depicting the back surface field region forming local in absorbed layer of an embodiment according to the application.
Fig. 8 depicts according to the embodiment of the application the side cross-sectional views forming one or more material layer between the passivation layer of the back surface of absorbed layer and contiguous absorbed layer.
Fig. 9 is the side cross-sectional views depicting unijunction solar cell of an embodiment according to the application, and wherein, the material layer on absorbed layer top is similar to the material layer under absorbed layer.
Figure 10 is the side cross-sectional views depicting the exemplary unijunction solar cell with the emitter layer formed according to the principle of the application.
Figure 11 is the drawing of the characteristic of the experiment measuring of the unijunction solar cell shown in the Figure 10 under the irradiation of 1 sun (sun).
Embodiment
The specific embodiment of structure required for protection and method is disclosed here; However, it should be understood that the disclosed embodiments are only the example of the structure required for protection and method that can embody in a variety of manners.In addition, each example provided about various embodiment is intended to illustrate, and unrestricted.Further, accompanying drawing need not chi in proportion, and some features can be exaggerated the details that particular elements is shown.Thus, concrete structure sum functions details disclosed herein is not interpreted as restrictive, and is merely for instructing those skilled in the art with various the representative basis adopting the method and structure of the application.
Mentioning in the description to " embodiment ", " embodiment ", " example embodiment " etc., comprises specific feature, structure or characteristic, but each embodiment need not comprise this specific feature, structure or characteristic.Moreover such wording need not relate to identical embodiment.Further, when describing about the specific feature of embodiment, structure or characteristic, whether cannot describe clearly, should think that impact is within the ken of those skilled in the art about such feature, structure or the characteristic of other embodiment.
For the object of hereafter surface description, as it is in the accompanying drawings by fixed setting, term " on ", D score, "left", "right" " vertically ", " level ", " top ", " end " and derivative thereof should relate to invention.Term " above covers ", " ... on top ", " be positioned at ... on " or " being positioned at ... on top " mean that the first element of such as the first structure is present in the second key element of such as the second structure, wherein, the intermediate elements of such as interfacial structure can be there is between the first element and the second key element.Term " directly contacts " and means the first element of connection such as the first structure and the second key element of such as the second structure, and in the interface of two key elements without any centre conduction, insulation or semiconductor layer.
In one embodiment, the application provides junction photovoltaic devices and the manufacture method thereof of such as solar cell.As used herein, " photovoltaic device " for when being exposed to the radiation of such as light, the room (vacancy) in generation free electron and/or such as hole and cause the device of the generation of electric current is such as solar cell.Junction photovoltaic devices typically comprises the semiconductor layer of the p-type conductivity sharing interface with the semiconductor layer of n-type conductivity, and wherein, interface provides electricity knot.If N-shaped and p-type area are made up of two kinds of different components and/or crystal structure different semi-conducting materials, knot is called as heterojunction.Junction photovoltaic devices comprises for the emitter layer of non-crystal III-V type semi-conducting material and the absorbed layer that is made up of IV type semi-conducting material.III-V type semi-conducting material is the compound semiconductor be made up of the element of III and the V race being selected from the periodic table of elements.IV type semi-conducting material is the semi-conducting material of the IV race being selected from the periodic table of elements.
Owing to working as the broad-band gap electrical characteristics be formed on IV type semi-conducting material, for photovoltaic device, some III-V type semi-conducting materials are interested, and wherein, IV type semi-conducting material has smaller strip gap value.Such as, silicon (Si) is for having the IV type semi-conducting material of the band gap of 1.1eV, and the III-V type semiconductor of such as gallium nitride (GaN) has the band gap of 3.3eV.Because the existence of two kinds or how different band gap allows more effectively collecting of solar spectrum, namely, the photon with shorter wavelength is efficiently collected in the battery of top, and the photon with longer wavelength is efficiently collected in end battery, for photovoltaic device, III-V type semi-conducting material is interested.So, by appropriate battery design, output voltage and/or the electric current of solar cell can be improved.But the such as poor efficiency of many knots of string folded (binode), the photovoltaic device at least comprising the top battery comprising III-V type semi-conducting material and the end battery comprising IV type semi-conducting material has limited the advantage of III-V type semi-conducting material.Determine, be derived from the poor epitaxial growth of the III-V type semi-conducting material (such as gallium nitride) on the silicon underliing battery from the poor efficiency of the many knots photovoltaic device measurement comprising the top battery be made up of III-V type semi-conducting material.The poor epitaxial growth of III-V semi-conducting material causes the highdensity fault of construction in the battery of the photovoltaic device be made up of III-V type semi-conducting material.Consequently, the carrier lifetime in III-V type semi-conducting material and the efficiency comprising the battery of III-V type semi-conducting material are thus lowered.
In one embodiment, by using junction photovoltaic devices, and non-usage many knots photovoltaic device, the application utilizes the broad-band gap characteristic of III-V type semi-conducting material, wherein, the emitter layer of junction photovoltaic devices by forming for non-crystal III-V type semi-conducting material and there is 50nm or less thickness, such as 10nm or less, and the absorbed layer of junction photovoltaic devices is made up of IV type semi-conducting material.This is because, as the result of thin noncrystal III-VIII-V emitter layer, dominated and non-diffusing by tunnelling by the carrier collection of noncrystal III-V emitter layer.As used herein, term " unijunction " represents that photovoltaic device only comprises a p-n junction." p-n junction " is for have the interface between first material (such as, p-type emitter layer) of p-type conductivity and second material (N-shaped absorbed layer) with n-type conductivity.Contrary with junction photovoltaic devices, many knot photovoltaic devices are made up of multiple p-n junction.
Compared with comprising the solar cell of the emitter layer be made up of IV type semi-conducting material, the III-V type semi-conducting material emitter layer of structure disclosed herein and method, with the one of at least following manner, improve the performance of disclosed unijunction solar cell.For the N-shaped emitter layer of III-V type semi-conducting material, compared with the absorbed layer of IV type semi-conducting material, the lower electron affinity of the III-V type semi-conducting material of emitter layer adds the division (by improving the quasi-Fermi level of electronics) at the electronics at emitter layer place and the quasi-Fermi level in hole, and increases the open circuit voltage of battery thus.Similarly, for the p-type emitter layer of III-V type semi-conducting material, compared with the absorbed layer of IV type semi-conducting material, the higher hole affinity of III-V type semi-conducting material adds the division (by reducing the quasi-Fermi level in hole) at the electronics at emitter layer place and the quasi-Fermi level in hole, and increases the open circuit voltage of battery thus.The hole affinity of material be restricted to the band gap of this material and electron affinity and.
In another embodiment, for the N-shaped emitter layer of III-V type semi-conducting material, compared with the IV type semi-conducting material of absorbed layer, the potential barrier adding the tunneled holes tied by emitter layer compared with macroscopic cavitation affinity of the III-V type semi-conducting material of emitter layer, and reduce the dark current of solar cell thus.Consequently, the open circuit voltage of solar cell is increased.Similarly, for the p-type emitter layer of III-V type semi-conducting material, compared with the absorbed layer of IV type semi-conducting material, the sub-affinity of small electric of III-V type semi-conducting material adds the potential barrier of the electron tunneling tied by emitter layer, and reduce the dark current of sun energy battery thus, cause higher open circuit voltage.
In another embodiment, the electric field of the enhancing at emitter layer place improves the short circuit current of the carrier separation at emitter layer place and solar cell thus, the lower electron affinity of oneself the III-V type semi-conducting material compared with the IV type semi-conducting material of absorbed layer of electric field source of this enhancing.
In a still further embodiment, compared with the emitter layer be made up of IV type semi-conducting material, the absorption loss water that the broad-band gap of the emitter layer of III-V type semi-conducting material reduces within emitter layer (especially shortwave strong point).Thus compared with the emitter layer be made up of IV type semi-conducting material, the broad-band gap of III-V type semi-conducting material adds the short circuit current of solar cell, and this solar cell comprises the emitter layer of III-V type semi-conducting material.
Fig. 1 describes an embodiment of unijunction solar cell, and this unijunction solar cell has the absorbed layer 10 (being also referred to as absorber 10) of IV type semi-conducting material and the emitter layer 20 (being also referred to as emitter 20) for non-crystal III-V type semi-conducting material." absorbed layer " of photovoltaic device is for easy absorb photons is to generate the material in electric charge carrier (that is, free electron or hole).Photovoltaic device front side and and the knot of absorbed layer 10 between a part be called as " emitter layer ", and this knot is called as " emitter layer knot ".Emitter layer 20 is present on the top of absorbed layer 10, and wherein, emitter layer 20 has the conductivity-type contrary with the conductivity-type of absorbed layer 10.As used herein, term " conductivity-type " represents that semi-conducting material is p-type or N-shaped.As used herein, " p-type " refers to the interpolation of impurity to intrinsic semiconductor, and it produces the shortage (that is, hole) of valence electron.As used herein, " N-shaped " refers to the interpolation of impurity, and its contribution free electron is to intrinsic semiconductor.
In an example, when collecting the solar energy of form of photons in battery layers, in the N-shaped within photovoltaic device and p-type conductivity material, generate electron-hole pair.Emitter layer ties the electric field needed for collection in light induced electron and the hole be provided for respectively in the p-type doping and N-shaped doped side of emitter layer knot.Given this reason, and in this example, at least one p-type layer of photovoltaic device provides absorbed layer 10, and at least one contiguous n-layer provides emitter layer 20.
In one embodiment, emitter layer 20 is made up of at least one III-V type semi-conducting material, and this III-V type semi-conducting material is selected from gallium nitride (GaN), phosphorous nitride gallium (GaPN), aluminium antimonide (AlSb), aluminium arsenide (AlAs), aluminium nitride (AlN), aluminum phosphate (AlP), boron nitride (BN), boron phosphide (BP), arsenic boron (BAs), GaAs (GaAs), gallium phosphide (GaP), indium nitride (InN), indium phosphide (InP), aluminum gallium arsenide (AlGaAs), InGaP (InGaP), aluminium arsenide indium (AlInAs), indium aluminium antimonide (AlInSb), arsenic gallium nitride (GaAsN), arsenic gallium antimonide (GaAsSb), aluminium gallium nitride alloy (AlGaN), phosphatization gallium aluminium (AlGaP), InGaN (InGaN), arsenic indium antimonide (InAsSb), indium antimonide gallium (InGaSb), AlGaInP (in AlGaInP), arsenic phosphatization gallium aluminium (AlGaAsP), indium arsenic phosphide gallium (InGaAsP), arsenic antimony indium phosphide (InArSbP), arsenic aluminum phosphate indium (AlInAsP), arsenic aluminium gallium nitride alloy (AlGaAsN), arsenic InGaN (InGaAsN), arsenic indium nitride aluminium (InAlAsN), arsenic antimony gallium nitride (GaAsSbN), nitrogen arsenic indium gallium antimonide (GaInNAsSb), arsenic antimony InGaP (GaInAsSbP) and combination thereof.In an example, emitter layer 20 is made up of at least one III-V type semi-conducting material, and this III-V type semi-conducting material is selected from gallium nitride (GaN), InGaN (InGaN), gallium phosphide (GaP), indium phosphide (InP), nitrogen gallium phosphide (GaPN), nitrogen gallium antimonide (GaSbN), nitrogen gallium arsenide phosphide (GaAsPN) and combination thereof.In another embodiment, emitter layer 20 is made up of GaN, InGaN, GaP, InP and/or GaPN.
It may be noted that, for the above-mentioned III-V type semi-conducting material of emitter layer 20 only for illustration of property object, as long as the electron affinity of III-V type semi-conducting material higher than the hole affinity of IV type semi-conducting material, also can adopt other III-V type semi-conducting material lower than the electron affinity of IV type semi-conducting material and/or the hole affinity of III-V type semi-conducting material.Electronics and the hole affinity of crystalline silicon are approximately 4.05eV and 5.15eV respectively, wherein, hole affinity be restricted to electron affinity and band gap and.Electronics and the hole affinity of germanium crystal are approximately 4.00eV and 4.67eV respectively.For Si xge 1-xalloy, electronics and hole affinity have the linear dependence of ratio of components x.Such as, as x=0.75, electronics and hole affinity are approximately 4.04eV and 5.03eV respectively.In another embodiment, as x=0.50, electronics and hole affinity are approximately 4.03eV and 4.91eV respectively.Ratio of components can be constant or changes across absorbed layer.In the above-described example, x refers to the ratio of components at the top surface place (that is, at emitter layer knot place) at absorbed layer 10.
Each III-V type semi-conducting material of emitter layer 20 is provided to have non-crystal structure.Non-crystal structure refers to amorphous, nanocrystal or microcrystal.Term " amorphous " represents Amorphous solids, wherein, in this semi-conducting material, does not have long range atomic order.Atomic order refers to the order of atom bonding lengths in solids and atom bond angle.Term " nanometer/micro--crystal " refers to the solid material be made up of the crystalline region of the nanometer distributed within amorphous media/micro--size.
Emitter layer 20 is made up of the III-V type semi-conducting material of individual layer or the sandwich construction of III-V type semi-conducting material is formed.Emitter layer 20 typically has the gross thickness T1 being not more than 50nm.In one embodiment, the gross thickness T1 of emitter layer 20 is not more than 10nm.In another embodiment, the gross thickness T1 scope of emitter layer 20 is from 1nm to 8nm.In a further embodiment, select the gross thickness T1 of emitter layer 20, so that the majority of photo-generated charge carriers is tunneled through emitter layer 20 (if present, also by passivation/resilient coating 15 and 25), and is shifted by towards emitter electrode 35.As used herein, term " tunnelling " means that electric charge carrier (that is, electronics and/hole charge carrier) transports across the quantum-mechanical of potential energy barrier (such as, the potential barrier at p-n junction place), and does not change its energy.Thickness due to emitter layer 20 is 50nm or less, such as, be less than 10nm, and electric charge carrier is tunneled through emitter layer 20, significantly reduces the high-quality requirement of the emitter layer 20 to growth.High-quality semiconductor material layer typically has and is less than 10 13defect/cm 3defect concentration.This typical case to require in epitaxial grown material lower than 10 8dislocation/cm 2dislocation density.But in this application, such requirement is relaxed.In one embodiment, can provide the unijunction solar cell formed according to the application, this unijunction solar cell has the emitter layer 20 of 10nm or less thickness, and by there is scope from 10 13defect/cm 3to 10 21defect/cm 3the III-V type semi-conducting material composition of defect concentration.
In order at emitter layer 20 with underlie between absorbed layer 10 and provide knot, there is provided the III-V type semi-conducting material of emitter layer 20 can be doped to p-type or n-type conductivity, and provide the IV semi-conducting material of absorbed layer 10 can be doped to the conductivity contrary with emitter layer 20.Such as, when providing the III-V type semi-conducting material of emitter layer 20 to be doped to p-type conductivity, the IV semi-conducting material of absorbed layer 10 is provided to be doped to n-type conductivity.In another embodiment, when providing the III-V type semi-conducting material of emitter layer 20 to be doped to n-type conductivity, the IV semi-conducting material of absorbed layer 10 is provided to be doped to p-type conductivity.
For the III-V type semi-conducting material providing emitter layer 20, the impact of dopant atom (that is, no matter it is p-type or n-type dopant), depends on the position occupied by the dopant atom on the lattice of basic material.In III-V type semi-conducting material, when occupying the position of III atom, II race atom is as acceptor (that is, p-type), and when it replaces V group atom, the atom in VI race is as alms giver (that is, N-shaped).The such as dopant atom of the IV race of silicon (Si) have depend on its be occupy respectively III or V group atom position and as the character of acceptor or alms giver.Such impurity is known as amphoteric impurity.For the dopant concentration range of dopant from 10 15atom/cm 3to 10 21atom/cm 3, this dopant determines the conductivity-type providing the III-V type semi-conducting material of emitter layer 20.In another embodiment, determine that the dopant concentration range of the conductivity-type of III-V type semi-conducting material is from 10 16atom/cm 3to 10 20atom/cm 3.
With reference to figure 1, and in certain embodiments, between emitter layer 20 and absorbed layer 10, there is the buffering/passivation layer 15 of III-V type semi-conducting material.Buffering/passivation layer 15 is intrinsic or lightly doped semi-conducting material.In one embodiment, due to compared with the doping content in emitter layer 20 cushioning/passivation layer 15 in lower doping, buffering/passivation layer 15 provides the surface passivation of the IV type semi-conducting material of absorbed layer 10 in order to improve.In another embodiment, buffering/passivation layer 15 is made up of such material, compared with the lattice mismatch between the noncrystal III-V type semi-conducting material of emitter layer 20 and the IV type semi-conducting material of absorbed layer 10, this material has the lower lattice mismatch with the IV type semi-conducting material of absorbed layer 10.By being reduced in the lattice mismatch between material layer, buffering/passivation layer 15 is reduced in the generation of the short distance strain gradient of growing period." intrinsic material " (also referred to as non-doped semiconductor) or i type semiconductor, be essentially pure semiconductor, and exist without any obvious dopant species (species).The number of the electric charge carrier in intrinsic semiconductor is determined by the character of material itself, but not the amount of impurity (that is, dopant).Typically, in intrinsic semiconductor, the number of excitation electron and the number in hole are equal (n=p).In certain embodiments, buffering/passivation layer 15 has the maximum concentration of dopant for p-type or n-type dopant, and this maximum concentration of dopant is not more than 10 17atom/cm3.Buffering/passivation layer 15 can deliberately or not inadvertently be adulterated.Unintentional doping result from buffering/passivation layer 15 growing period and/or subsequently (time that is, when emitter layer 20) IV type semi-conducting material atom and/or dopant atom from absorbed layer 10 to the diffusion of buffering/passivation layer 15.Buffering/passivation layer 15 is crystal or noncrystal.During subsequent growth processing step, buffering/passivation layer 15 also can not inadvertently be adulterated.Dopant also can be diffused into buffering/passivation layer 15 from emitter layer 20.In one embodiment, buffering/passivation layer 15 is substantially free of N-shaped or p-type dopant.Buffering/passivation layer 15 is made up of at above-described III-V type semi-conducting material with reference to emitter layer 20 any.In certain embodiments, buffering/passivation layer 15 is made up of the component identical with providing the III-V type semi-conducting material of emitter layer 20.Buffering/passivation layer 15 can directly contact with the surface of the IV type semi-conducting material providing absorbed layer 10.Formed by the growing technology identical with emitter layer 20 and cushion/passivation layer 15.But, can use and comprise other growing technology epitaxially grown to form resilient coating.The thickness of buffering/passivation layer 15 is thinner than 30nm.In another embodiment, the thickness range of buffering/passivation layer 15 is from 3nm to 10nm.Buffering/the passivation layer 15 described in FIG is optional layer and can be left in the basket.In the uncared-for embodiment of buffering/passivation layer 15, provide the III-V type semi-conducting material of emitter layer 20 directly can contact with providing the IV type semi-conducting material of absorbed layer 10.
The IV type semi-conducting material of absorbed layer 10 is provided to comprise silicon (Si), germanium (Ge), germanium silicon (SiGe) and carbon doping silicon (Si:C).In an example, the IV type semi-conducting material providing absorbed layer 10 is silicon.Absorbed layer 10 is generally crystal semiconductor material, such as, and monocrystalline or poly semiconductor.It may be noted that, only be provided for the above-mentioned IV type semi-conducting material of absorbed layer 10 for illustration purposes, as long as the electron affinity of III-V semi-conducting material is lower than the electron affinity of IV semi-conducting material, and/or the hole affinity of III-V material is higher than the hole affinity of IV material, other IV type semi-conducting material can be adopted.
Absorbed layer 10 is typically formed by from Semiconductor substrate, and typically has the conductivity-type contrary with the conductivity-type of emitter layer 20.Such as, when emitter layer 20 is doped to p-type conductivity, absorbed layer 10 is doped to n-type conductivity, and when emitter layer 20 is doped to n-type conductivity, absorbed layer 10 is doped to p-type conductivity.In the absorbed layer 10 be made up of IV type semi-conducting material, the example of p-type dopant (that is, impurity), includes but not limited to boron, aluminium, gallium, indium and combination thereof.Absorbed layer 10 is doped in an embodiment of p-type conductivity wherein, and p-type dopant is with from 1x10 9atom/cm 3to 1x10 20atom/cm 3the concentration of scope exists.Absorbed layer 10 is doped in another embodiment of p-type conductivity wherein, and p-type dopant is with from 1x10 14atom/cm 3to 1x10 18atom/cm 3the concentration of scope exists.In the absorbed layer 10 be made up of IV type semi-conducting material, the example of n-type dopant (that is, impurity), includes but not limited to antimony, arsenic, phosphorus and combination thereof.First conductivity-type of the crystal semiconductor material wherein in absorbed layer 10 is in N-shaped embodiment, and n-type dopant is with from 1x10 9atom/cm 3to 1x10 20atom/cm 3the concentration of scope exists.First conductivity-type is in another embodiment of N-shaped wherein, and n-type dopant is with from 1x10 14atom/cm 3to 1x10 18atom/cm 3the concentration of scope exists.
The surperficial S of absorbed layer 10 1by typically veining, the surface of this absorbed layer 10 directly with optionally cushion/passivation layer 15 contacts, or when optionally buffering/passivation layer 15 is left in the basket, directly contacts with emitter layer 20.The surface of veining (that is, particularly roughening) is used, to increase the efficiency of light absorption in solar cell application.Due to the upper incident photon of slant characteristic (angled feature) by the side being reflected to adjacent inclined feature and thus there is absorbed other chance, relative to the mark of the incident light be transferred in battery, texturizing surfaces reduces the mark being lost to the incident light of reflection.Moreover, the surface of veining increases absorbed inside, because light incident on the surface tilted will typically be reflected, device is propagated through with angle of inclination, thus increase the length in the path of the back surface in order to arrive device, it is more possible for also making following: the photon reflected from the back surface of device clashes into front surface by catch compatible angle with total internal reflection and light.In certain embodiments, the texture of the surperficial S1 of absorbed layer 10 provides (111) crystal orientation.In certain embodiments, absorbed layer 10 is Si (100) and by veining, to provide (111) surface orientation.Absorbed layer 10 has the thickness T3 of scope from 100nm to 1mm.In one embodiment, absorbed layer 10 has the thickness T3 of scope from 500nm to 0.5mm.In another embodiment, absorbed layer 10 has scope from the thickness T3 of 50 microns to 180 microns.
Still with reference to figure 1, photovoltaic device comprises the first passivation layer 25 directly contacted with emitter layer 20 and the second passivation layer 5 directly contacted with absorbed layer 10 further.Each first passivation layer 25 and the second passivation layer 5 form by intrinsic amorphous semiconductor material.First passivation layer 25 can in order to the upper surface of passivation emitter layer 20, and the second passivation layer 5 is in order to the back surface of passivation absorbed layer 10, and wherein, each layer of the first passivation layer 25 and the second passivation layer 5 can reduce electron-hole compound.Although also can adopt comparatively heavy thickness, the thickness T4 of the first passivation layer 25 is typically less than 25nm.In one embodiment, the thickness T4 of passivation layer 25 is in the scope of 3nm to 8nm.In certain embodiments, passivation layer 25 is made up of hydrogenated amorphous Si and comprises C, Ge, O, N, F, D and combination thereof.Although also can adopt comparatively heavy thickness, the thickness T5 of the second passivation layer 5 is typically less than 1 micron.In one embodiment, the thickness T5 of passivation layer 5 is in the scope of 50nm to 150nm.In another embodiment, the thickness T5 of passivation layer 5 is in the scope of 3nm to 15nm.First and second passivation layers 25,5 are optional, and can be left in the basket.
There is transparent conductive material layer 30 in the first passivation layer 25.In whole application, if key element is enough transparent in electromagnetic visible spectrum scope, this key element is " transparent ".In one embodiment, transparent conductive material layer 30 can comprise transparent conductive oxide, and this transparent conductive oxide is such as, but not limited to, fluorine doped tin oxide (SnO 2: F), Al-Doped ZnO (ZnO:Al), tin oxide (SnO) and tin indium oxide (InSnO 2, or referred to as ITO).The thickness of transparent conductive material layer 30 can be depending on the type of adopted transparent conductive material and changes forming the technology that uses in transparent conductive material.Typically, and in one embodiment, the thickness range of transparent conductive material layer 30 is from 20nm to 500nm.Also other thickness comprising and be less than 20nm and/or be greater than 500nm can be adopted.Transparent conductive material layer 30 is optional, and can be left in the basket.
Front contact 35 (being also referred to as emitter contact 35) directly contacts with transparent conductive material layer 30, and back contacts (not shown) and absorbed layer 10 electric connection.In one embodiment, the front contact 35 of solar cell comprises one group of parallel narrow finger-like circuit (finger line) and typically with and that deposit wide collector electrode circuit at a right angle with finger-like circuit.Front contact 35 is typically made up of metal material.Before providing, the metal material of contact 35 can be any conductive paste, such as, and aluminium (Al) cream, silver (Ag) cream, copper (Cu) cream or aluminium silver (AlAg) cream.Although also less or larger thickness can be adopted, the thickness of front contact 35 can scope from 100nm to 10 microns.With front to contact 35 similar, back contacts 40 can be made up of any electric conducting material of such as aluminium, and has scope from 100nm to the thickness of 10 microns, although also can adopt less or larger thickness.
Fig. 2-4 depicts an embodiment of the method forming unijunction solar cell, and the method is provided in photovoltaic device depicted in figure 1.In one embodiment, the application provides the method forming photovoltaic device 100, the method comprises the absorbed layer 10 providing the crystal IV type semi-conducting material with the first conductivity-type, and forms the emitter layer 20 with the noncrystal III-V semi-conducting material of the second conductivity-type be positioned on the surface of absorbed layer 10.Term " the first conductivity-type " and " the second conductivity-type " mean that emitter layer 20 and absorbed layer 10 have contrary conductivity-type.Such as, when emitter layer 20 is doped to p-type conductivity type, absorbed layer 10 is doped to n-type conductivity type, and when emitter layer 20 is doped to n-type conductivity type, absorbed layer 10 is doped to p-type conductivity type.
Fig. 2 depicts an embodiment of initial configuration, this initial configuration can be utilized to be formed and be similar to unijunction solar cell depicted in figure 1, wherein, this initial configuration comprises the substrate of IV type semi-conducting material, and the substrate of this IV type semi-conducting material provides the absorbed layer 10 of unijunction solar cell.Appropriate component and the thickness of the IV type semi-conducting material for substrate that absorbed layer 10 is provided is described above with reference to figure 1.In an example, substrate is made up of monocrystalline silicon.Use ion implantation, gas phase doping, the dopant of the first conductivity-type providing absorbed layer 10 can be guided to substrate, or by original position (in-situ) doping during substrate formation process, this dopant is guided to substrate.In certain embodiments, provide the substrate of absorbed layer 10 to comprise Si and there is (100) crystal orientation.
Fig. 3 depicts an embodiment of the substrate of veining IV type semi-conducting material.In one embodiment, textured substrate provides the texturizing surfaces S1 with (111) crystal orientation.In one embodiment, by with the solution based on potassium hydroxide (KOH), the upper surface of IV type semi-conducting material can be etched, carries out the single crystalline substrate of veining IV type semi-conducting material.In another embodiment, nitric acid (HNO can be used 3)/hydrofluoric acid (HF) solution, the upper surface of etching IV type semi-conducting material, carries out the Polycrystalline substrates of veining IV type semi-conducting material.Other solution being suitable for textured substrate comprises potash (K 2cO 3).In another embodiment, veining can be realized by the combination utilizing reactive ion etching (RIE) and comprise closelypacked self-assembling polymers ball mask.In another embodiment, in maskless situation, use reactive ion etching (RIE), realize veining.In certain embodiments, the both sides of absorbed layer 10 are all by veining.In certain embodiments, the veining dorsal part of absorbed layer 10 improves light and gets back to reflection absorbed layer 10 from the dorsal part of absorbed layer 10.
Fig. 4 depicts to be formed and is located in the embodiment providing the noncrystal III-V type semi-conducting material on the surperficial S1 of the veining of the substrate of the IV type semi-conducting material of absorbed layer 10 as buffering/passivation layer 15, wherein, a part at least noncrystal III-V type semi-conducting material provides the emitter layer 20 of unijunction solar cell.
Many different sources can be used to the growth of noncrystal III-V type semi-conducting material.In certain embodiments, source for the growth of III-V type semi-conducting material comprises solid source and/or gas precursor, solid source comprises indium (In), gallium (Ga), nitrogen (N), phosphorus (P) element and combination thereof, and gas precursor is selected from trimethyl gallium (TMG), trimethyl indium (TMI), tert-butyl group phosphine (tertiary-butylphosphine) (TBP), hydrogen phosphide (PH 3), ammonia (NH 3) and combination.The growing technology of the liquid growth such as adopting fluid supply or the vapor phase growth adopting gas source can be used.Although also lower or higher temperature can be adopted, for the growth of noncrystal III-V type semi-conducting material temperature typically scope from 450 DEG C to 900 DEG C.Growth temperature also depends on growing technology.Such as, in the molecular beam deposition adopting solid source, underlayer temperature can be low to moderate 200 DEG C.In the growth of N or the P sill by molecular beam deposition, low underlayer temperature is by such as NH 3or PH 3the plasmaassisted cracking (cracking) of gas source promote, to provide N-shaped or p-type conductivity respectively.When the growth by metal organic chemical vapor deposition (MOCVD), higher temperature typically causes depositing faster, but deposition can cause crystal defect and film cracking faster.
In certain embodiments, buffering/passivation layer 15 is deposited directly upon on the surperficial S1 of the veining of absorbed layer 10.Component and the thickness of buffering/passivation layer 15 have been depicted above with reference to figure 1.In certain embodiments, the technology identical for the growth of emitter layer 20 described is used to form buffering/passivation layer 15.But, can use and comprise other growing technology epitaxially grown, to form buffering/passivation layer 15.As described above, buffering/passivation layer 15 is intrinsic semiconductor layer or light dope semiconductor layer.When buffering/passivation layer 15 is lightly doped, the maximum N-shaped existed in buffering/passivation layer 15 or p-type dopant concentration can be 10 17atom/cm 3.Buffering/passivation layer 15 is optional, and can be left in the basket.
Still with reference to figure 4, emitter layer 20 can be deposited over or be positioned on absorbed layer 10, and wherein, emitter layer 20 is doped to the conductivity-type contrary with absorbed layer 10.Absorbed layer 10 exists in the embodiment of buffering/passivation layer 15, emitter layer 20 is directly grown contiguously by the top surface with buffering/passivation layer 15, and the surface directly contacted with the surperficial S1 of the veining of absorbed layer 10 of the top surface of buffering/passivation layer 15 and buffering/passivation layer 15 is contrary.In the embodiment that there is buffering/passivation layer 15, emitter layer 20 is made up of the III-V type semi-conducting material with the component different from buffering/passivation layer 15.In the uncared-for embodiment of buffering/passivation layer 15, emitter layer 20 is directly grown contiguously by the surperficial S1 of the veining with absorbed layer 10.
Use the outdiffusion of plasma doping, ion implantation and/or disposable diffuse source (such as, borosilicate glass) at least one, by in-situ doped technique doping emitter layer 20, or the emitter layer 20 that adulterates after the deposition of the material layer of emitter layer 20." original position " means that the dopant of the conductivity-type of the material layer providing such as emitter layer 20 is introduced when material layer is formed or deposit.In one embodiment, wherein, emitter layer 20 is in-situ doped, and to provide p-type or n-type conductivity, dopant gas is selected from bis-cyclopentadienyl magnesium (bis-cyclopentadienyl-magnesium) (Cp 2mg), silane (SiH 4), disilane (Si 2h 6), germane (GeH 4), carbon tetrabromide (CBr 4) and combination.
With reference to figure 1, after the formation of unijunction solar cell, utilize physical vapour deposition (PVD) (PVD), chemical vapour deposition (CVD) (CVD) or heat and/or plasma assisted oxidation/nitriding process, form the first and second passivation layers 25,5.At some, wherein the first and second passivation layers 25,5 are by intrinsic amorphous hydrogenated semiconductor material (such as, silicon) in the embodiment that forms, intrinsic amorphous hydrogenated semiconductor material is deposited in process cavity, and this process cavity comprises semiconductor precursor source gas and comprises the vector gas of hydrogen.Hydrogen atom in hydrogen within vector gas is incorporated in the material of deposition, to form the intrinsic hydrogenated semi-conducting material providing the first and second passivation layers 25,5.In certain embodiments, before the formation of emitter layer 20, form the second passivation layer 5.Before the formation of emitter layer 20 by absorbed layer 10 (namely, start substrate) thermal oxidation formed in the embodiment of the second passivation layer 5, before emitter layer 10 is formed, such as, pass through wet etching, remove the thermal oxide that (partly or fully) formed on the top surface of absorbed layer 10, so that the top surface being provided for the layer 10 of the growth of emitter layer and/or resilient coating at least partially.The depositing operation of such as sputtering or chemical vapour deposition (CVD) (CVD) is used typically to form transparent conductive material layer 30.With contact 35 before screen printing technique deposition.In another embodiment, contact 35 before being provided by the applying of the metallic pattern etching or electroplate.Use and front contact 35 similar methods and form back contacts (description).
Fig. 5 describes another embodiment of the application, wherein, before the emitter layer 20 forming noncrystal III-V type semi-conducting material, the top of absorbed layer 10 forms the passivation layer 40 of composition.In this embodiment, provide transmitting layer by layer 20 noncrystal III-V type semi-conducting material directly contact with absorbed layer, and to be present in the opening by the passivation layer 40 of composition.In the embodiment that some absorbed layers 10 are made up of silicon, the buffering/passivation layer 40 of composition is by silicon dioxide (SiO 2) composition, it is formed by thermal oxidation and uses photoetching or laser ablation process composition.Before the formation of emitter layer 20, the top of absorbed layer 10 forms optional buffering/passivation layer 15a.The embodiment described in Fig. 5 comprises the technological process of the formation prior to the second passivation layer 5.
With reference to figure 6, and in certain embodiments, before the formation of back contacts 50, use technology composition second passivation layer 5 of such as photoetching or laser ablation.In these embodiments, back contacts 50 is typically made up of metal, in passivation layer 5 removed region, directly contacts with absorbed layer 10.In these embodiments, contact 50 and be commonly called local back contact.
With reference to figure 7, and in some embodiments of composition first passivation layer 5, as described by figure 6, in absorbed layer 10, form doped region 45.Doped region 45 is formed in removed region place at the first passivation layer 5.Doped region 45 is formed by ion implantation or gas phase doping.In certain embodiments, doped region 45 typically has the conductivity identical with the dopant existed in the first passivation layer 5, that is, p-type or n-type conductivity.The doped region 45 described in Fig. 7 is called as local back surface field contacts.
With reference to figure 8, and in certain embodiments, between the first passivation layer 5 and back contacts 50, there is one or more dopant material layer 55.This one or more dopant material layer 55 is made up of amorphous silicon hydride, nano-silicon, micron silicon, polycrystalline Si, hydrogenated amorphous germanium (a-Ge:H), Ge, micron germanium, polycrystalline germanium and combination thereof, and comprises the dopant being selected from carbon (C), nitrogen (N), oxygen (O), fluorine (F), deuterium (D) and combining.Still with reference to figure 8, in certain embodiments, between one or more dopant material layer 55 and back contacts 50, there is such as transparent conductive oxide (such as, fluorine doped tin oxide (SnO 2: F)) transparent conductive material 60.
With reference to figure 9, and in certain embodiments, backside contact structure has the configuration identical with front side (emitter) contact structures, but doped layer 20a has the conductivity-type identical with absorbed layer 10.In the front portion of absorbed layer with back, the component of corresponding layer is different.In addition, there is optional layer in side, and there is not corresponding optional layer at another layer.If absorbed layer 10 is p-type, the III-V material of back surface field layer 20a is selected to have the hole affinity being greater than absorbed layer 10.Similarly, if absorbed layer 10 is N-shaped, the III-V material of surface field layer 20a is selected to have the electron affinity being less than absorbed layer 10.The function of optional passivation layer 25a is identical with the function of the first passivation layer 25.Transparent conductive material layer 30a is optional and can be left in the basket.Back contact 35a is metal grate or blanket (blanket) metal level.
With reference to Figure 10, according to the principle of the application, by growing p in the N-shaped single crystalline silicon substrate 10 being used as absorbed layer +doping Amorphous SiC emitter layer 20, forms unijunction solar cell.Crystal Si substrate 10 has at the resistivity of 0.2-0.3ohm.cm scope, the thickness of about 200 μm and (100) crystal orientation.P +doping Amorphous SiC emitter layer 20 has the thickness of 10nm, and is passed through metal organic chemical vapor deposition (MOCVD) from ammonia (NH 3) and trimethyl gallium (TMG) mixture (the V/III ratios of ~ 1500), at the underlayer temperatures of 525 DEG C, at H 2to grow under 100mbar under vector gas.Use dicyclopentadienyl magnesium (Biscyclopentadienylmagnesium) (DCpMg) as Mg source.Amorphous SiC deposition rate is the flow rate of DCpMg is 4nmol/sec.After deposition, at N 2under atmosphere, 1000 DEG C by 30 seconds rapid thermal annealing, Mg is activated.Then, under the underlayer temperature of 150 DEG C, by the sputtering of tin indium oxide (ITO), form the transparency conductive electrode 30 with 90nm thickness.With shadow mask (shadow mask), contact grid 35 before being formed by the thermal evaporation of silver.Aluminium back contacts 5 is formed by thermal evaporation.
Figure 11 is the curve chart of the experiment output characteristic of the unijunction solar cell of the Figure 10 measured under the irradiation of 1 sun.This output characteristic illustrates 18.5mA/cm 2short-circuit current density, the open circuit voltage of 533mV and the fill factor, curve factor of 75.7%, the conversion efficiency corresponding to 7.5%.It may be noted that the unijunction device of Figure 10 lacks the surface of the various key elements, particularly veining of preferred solar cell embodiment, front passivation layer and back surface field, and these will strengthen conversion efficiency significantly.
Illustrate and describe the application especially with regard to preferred embodiment, should be appreciated that those skilled in the art under the spirit and scope not departing from the application, can be made at above-mentioned or other change in formation and details.Thus, the application is not limited to concrete form that is described and that illustrate and details, and within the scope being intended to drop on claims.

Claims (26)

1. a photovoltaic device, comprising:
Unijunction solar cell, is provided with the emitter layer of the III-V type semi-conducting material with the second conductivity by the absorbed layer of the IV type semi-conducting material with the first conductivity;
Wherein, described III-V type semi-conducting material is noncrystal and has the thickness being not more than 50nm.
2. photovoltaic device according to claim 1, wherein, described III-V type semi-conducting material has the thickness being not more than 10nm.
3. photovoltaic device according to claim 1, wherein, described IV type semi-conducting material is selected from silicon (Si), germanium (Ge), germanium silicon (SiGe), carbon doping silicon (Si:C) and combination thereof.
4. photovoltaic device according to claim 1, wherein, the thickness range of described absorbed layer is from 100nm to 1mm.
5. photovoltaic device according to claim 1, wherein, described III-V type semi-conducting material is selected from gallium nitride (GaN), phosphorous nitride gallium (GaPN), aluminium antimonide (AlSb), aluminium arsenide (AlAs), aluminium nitride (AlN), aluminum phosphate (AlP), boron nitride (BN), boron phosphide (BP), arsenic boron (BAs), GaAs (GaAs), gallium phosphide (GaP), indium nitride (InN), indium phosphide (InP), aluminum gallium arsenide (AlGaAs), InGaP (InGaP), aluminium arsenide indium (AlInAs), indium aluminium antimonide (AlInSb), arsenic gallium nitride (GaAsN), antimony gallium nitride (GaSbN), arsenic gallium antimonide (GaAsSb), aluminium gallium nitride alloy (AlGaN), phosphatization gallium aluminium (AlGaP), InGaN (InGaN), arsenic indium antimonide (InAsSb), indium antimonide gallium (InGaSb), AlGaInP (AlGaInP), arsenic phosphatization gallium aluminium (AlGaAsP), indium arsenic phosphide gallium (InGaAsP), arsenic antimony indium phosphide (InArSbP), arsenic aluminum phosphate indium (AlInAsP), arsenic aluminium gallium nitride alloy (AlGaAsN), arsenic InGaN (InGaAsN), arsenic indium nitride aluminium (InAlAsN), arsenic antimony gallium nitride (GaAsSbN), arsenic phosphorous nitride gallium (GaAsPN), nitrogen arsenic indium gallium antimonide (GaInNAsSb), arsenic antimony InGaP (GaInAsSbP) and combination thereof.
6. photovoltaic device according to claim 1, wherein, described IV type semi-conducting material is silicon, described first conductivity is N-shaped, described III-V type semi-conducting material is selected from gallium nitride (GaN), InGaN (InGaN), gallium phosphide (GaP), indium phosphide (InP), nitrogen gallium phosphide (GaPN) and combination thereof, and described second conductivity is p-type.
7. photovoltaic device according to claim 6, wherein, in described IV type semi-conducting material, provide the first dopant of the described N-shaped of described first conductivity to be selected from P, Sb, As and combination thereof, and provide the second dopant of the described p-type of described second conductivity to be selected from Mg, Zn, C, Fe and combination thereof in described III-V type semi-conducting material.
8. photovoltaic device according to claim 7, wherein, provides the concentration range of described first dopant of the described N-shaped of described first conductivity from 10 in described IV type semi-conducting material 9atom/cm 3to 10 20atom/cm 3, and in described III-V type semi-conducting material, provide the concentration range of described second dopant of the described p-type of described second conductivity from 10 15atom/cm 3to 10 21atom/cm 3.
9. photovoltaic device according to claim 7, wherein, described IV type semi-conducting material is silicon, described first conductivity is p-type, described III-V type semi-conducting material is selected from gallium nitride (GaN), InGaN (InGaN), gallium phosphide (GaP), indium phosphide (InP), nitrogen gallium phosphide (GaPN) and combination thereof, and described second conductivity is N-shaped.
10. photovoltaic device according to claim 9, wherein, in described IV type semi-conducting material, provide the first dopant of the described p-type of described first conductivity to be selected from B, Ga, Al and combination thereof, and provide the second dopant of the described N-shaped of described second conductivity to be selected from Si, Ge, O and combination thereof in described III-V type semi-conducting material.
11. photovoltaic devices according to claim 7, wherein, provide the concentration range of described first dopant of the described p-type of described first conductivity from 10 in described IV type semi-conducting material 9atom/cm 3to 10 20atom/cm 3, and in described III-V type semi-conducting material, provide the concentration range of described second dopant of the described N-shaped of described second conductivity from 10 15atom/cm 3to 10 21atom/cm 3.
12. photovoltaic devices according to claim 1, wherein, described emitter layer directly contacts with the resilient coating of described absorbed layer or the III-V type semi-conducting material between described emitter layer and described absorbed layer.
13. photovoltaic devices according to claim 12, wherein, described resilient coating is intrinsic semiconductor.
14. photovoltaic devices according to claim 1, comprise further:
First passivation layer, described first passivation layer be present in described emitter layer formed on the surface of the contrary described emitter layer in the surface of tying with described absorbed layer; And
At least one of transparent conductive oxide or metal level is present on the surface of the exposure of described first passivation layer.
15. photovoltaic devices according to claim 14, comprise the second passivation layer further, and described second passivation layer is present in and being formed on the surface of the contrary described absorbed layer in the surface of tying with described emitter layer of described absorbed layer.
16. 1 kinds of methods forming photovoltaic device, comprising:
The absorbed layer of the crystal IV type semi-conducting material with the first conductivity-type is provided; And
The surface of described absorbed layer is formed the emitter layer with the amorphous III-V type semi-conducting material of the second conductivity-type.
17. methods according to claim 16, wherein, described absorbed layer is provided by the silicon-containing substrate being doped to described first conductivity-type, and wherein, described first conductivity-type comprises n-type conductivity or p-type conductivity.
18. methods according to claim 16, wherein, the surface of described silicon-containing substrate by veining, to provide (111) plane of crystal.
19. methods according to claim 18, wherein, by with by potassium hydroxide (KOH), potash (K 2cO 3), nitric acid (HNO 3), hydrofluoric acid (HF) or its combination at least one form wet etching, process the described surface of described silicon-containing substrate, the veining on the described surface of described silicon-containing substrate is provided, or with the described surface texturizing of reactive ion etching (RIE) by described silicon-containing substrate.
20. methods according to claim 18, wherein, before the described emitter layer of formation, at the resilient coating of the described deposited on silicon III-V type semi-conducting material of the described silicon-containing substrate of veining.
21. methods according to claim 17, wherein, the described resilient coating of described III-V type semi-conducting material is intrinsic material.
22. methods according to claim 18, wherein, form the deposition that the described emitter layer with the described III-V type semi-conducting material of described second conductivity comprises the described III-V type semi-conducting material directly contacted with described resilient coating, wherein, solid source and/or gas precursor is used to grow, described solid source comprises In, Ga, N, P element and combination thereof, and described gas precursor is selected from trimethyl gallium (TMG), trimethyl indium (TMI), tert-butyl group phosphine (TBP), hydrogen phosphide (PH 3), ammonia (NH 3) and combination.
23. methods according to claim 20, wherein, described second conductivity of described emitter layer is the N-shaped contrary with described first conductivity of described absorbed layer or p-type conductivity.
24. methods according to claim 23, wherein, the growing period of described III-V type semi-conducting material of described emitter is being provided, the second dopant of described second conductivity of described emitter layer is provided to be introduced into described III-V type semi-conducting material by original position, wherein, described second dopant is by being selected from bis-cyclopentadienyl magnesium (Cp 2mg), silane (SiH 4), disilane (Si 2h 6), germane (GeH 4), carbon tetrabromide (CBr 4) and combination dopant gas provide.
25. methods according to claim 18, wherein, described emitter layer has 50nm or less thickness.
26. methods according to claim 18, wherein, described III-V type semi-conducting material has scope from 10 13defect/cm 3to 10 21defect/cm 3defect concentration.
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