CN104671187A - Semiconductor device and forming method thereof - Google Patents
Semiconductor device and forming method thereof Download PDFInfo
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- CN104671187A CN104671187A CN201310617894.4A CN201310617894A CN104671187A CN 104671187 A CN104671187 A CN 104671187A CN 201310617894 A CN201310617894 A CN 201310617894A CN 104671187 A CN104671187 A CN 104671187A
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- testing cushion
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Abstract
The invention discloses a semiconductor device and a forming method thereof. The semiconductor device forming method comprises the following steps: etching the second surface of a cap wafer to form a cavity for accommodating a component protruding from the first surface of a semiconductor substrate, and an opening for forming a metal plug; filling the opening with a plate metal material; after the metal plug is formed, covering the first surface of the semiconductor substrate with the cap wafer in order that the component on the semiconductor substrate is positioned in the cavity, and the metal plug in the cap wafer is fixedly connected with a test pad on the semiconductor substrate; and grinding the first surface of the cap wafer to expose the metal plug. In the electrical performance test procedure of the formed semiconductor device, the component and an external test instrument are directly connected through the metal plug to finish the electrical performance test procedure of the component, so that the electrical performance test procedure of the semiconductor device is simplified, and the success rate of the electrical performance test procedure of the semiconductor device is increased.
Description
Technical field
The present invention relates to semiconductor preparation field, especially relate to a kind of semiconductor devices and forming method thereof.
Background technology
Along with the continuous progress of semiconductor integrated circuit manufacturing technology, the integrated level of integrated circuit constantly promotes, and the size of device also constantly reduces.Now at a ULSI (Ultra Large-Scale Integration; Be called for short, ULSI) in, components and parts up to a million can be comprised.
In so large-scale ic manufacturing process, in integrated circuit preparation process, in the specific time period, need the testing electrical property carried out for the various test structures on silicon chip, as the test of WAT(wafer receipt, Wafer Acceptance Test).By WAT data analysis, can problem in Timeliness coverage manufacture of semiconductor technique, help making technology to adjust.
Shown in figure 1 ~ Fig. 3, be MEMS(Micro-Electronic & Mechanical System, MEMS) encapsulate and WAT test technology.Specific embodiment comprises:
Shown in figure 1, in the substrate 10 that is equipped with MEMS chip 13, first form the tie point (bonding pad) 11 for encapsulating and the test point (testing pad) 12 for WAT test, wherein test point 12 and MEMS chip electrical connection; The covering substrate (Cap wafer) 20 providing surface to offer cavity 23, described cavity 23 is corresponding with MEMS chip 13 position; Shown in figure 2, covered by covering substrate 20 in described substrate 10, MEMS chip 13 is positioned at described cavity 23, tie point 11 and described covering substrate 20 fixing (bonding step); Remove part described covering substrate 20(dicing step) expose test point 12, for follow-up WAT test is prepared, and deposit electricity isolated layer (not shown) in described substrate 10, so far complete MEMS chip 13 and install.
Continue with reference to shown in figure 3, afterwards, carry out MEMS chip test, open the electricity isolated layer be positioned at above described test point 12, expose test point 12, and in electricity isolated layer, insert testing needle card (probe finger) 30, thus carry out the testing electrical property of MEMS chip.
In addition, in the WAT test process of reality, for the ease of the removal of covering substrate 20 afterwards, to expose test point 12, on covering substrate 20 surface, also need to offer groove 24 with test point 12 correspondence position.As mentioned above, the WAT test process of existing MEMS is loaded down with trivial details.And when testing needle card 30 inserts the opening of the electricity isolated layer be positioned at above test point, if misoperation, can there is deviation in described testing needle card 30; The through hole that electricity isolated layer above test point 12 offers if be positioned at is improper, or remove part covering substrate 20 position occur deviation time, testing needle card 30 also can touch with covering substrate 20, and above-mentioned situation all can cause testing needle card 30 to damage, and causes WAT test crash.
, how to improve in integrated circuit fabrication process, test technology success rate and testing efficiency are the problems that those skilled in the art need solution badly for this reason.
Summary of the invention
The problem that the present invention solves is to provide a kind of semiconductor devices and forming method thereof, thus efficiency when improving semiconducter device testing and the success rate of test step.
The formation method of a kind of semiconductor devices provided by the present invention, comprising:
Semiconductor substrate is provided, the first surface of described Semiconductor substrate has components and parts, there is in described Semiconductor substrate the testing cushion that surface is exposed to Semiconductor substrate first surface, noncontact between described components and parts and testing cushion, and by the interconnection line in described Semiconductor substrate by described components and parts and testing cushion electrical connection;
Covering substrate is provided, etches the second surface of described covering substrate, in described covering substrate, form opening;
In described opening, fill full metal material, form metal plug;
Etch the second surface of described covering substrate, in described covering substrate, form cavity;
The second surface of the first surface of described Semiconductor substrate and described covering substrate is fitted, makes the components and parts in described Semiconductor substrate be positioned at described cavity, and the testing cushion in described Semiconductor substrate is fixedly connected with described metal plug;
Grind the first surface of described covering substrate, until expose described metal plug, the first surface of described covering substrate is relative with the second surface position of covering substrate.
Alternatively, the degree of depth of described opening is 200 ± 50 μm, and aperture is 20 ± 10 μm.
Alternatively, the material of described testing cushion is copper, and described metal material is copper.
Alternatively, the method that described testing cushion is fixedly connected with described metal plug is binding technique, and described binding technique comprises:
At the temperature of 350 ± 50 DEG C, under the pressure of 40 ± 20KN, metal plug is kept to contact 10 ~ 40min with testing cushion.
Alternatively, the forming process of described metal plug comprises: form electricity isolated layer at the sidewall of described opening and bottom, backward described opening in fill full metal material, to form described metal plug.
Alternatively, the thickness of described electricity isolated layer is 1000 ~ 3000
.
Present invention also offers a kind of semiconductor devices, described semiconductor devices comprises:
Semiconductor substrate, the first surface of described Semiconductor substrate has components and parts, there is in described Semiconductor substrate the testing cushion that surface is exposed to Semiconductor substrate first surface, noncontact between described components and parts and testing cushion, and described components and parts are electrically connected by the interconnection line in described Semiconductor substrate with testing cushion;
Be covered in the covering substrate on the first surface of described Semiconductor substrate, the second surface of described covering substrate and the first surface of described Semiconductor substrate are fitted, wherein, in described covering substrate, offer cavity, the components and parts in described Semiconductor substrate are positioned at described cavity;
The metal plug running through the second surface of described covering substrate and the first surface of covering substrate is formed in described covering substrate, described metal plug is fixedly connected with described testing cushion, and the first surface of described covering substrate is relative with the second surface position of covering substrate.
Alternatively, the degree of depth of described metal plug is 200 ± 50 μm, and width is 20 ± 10 μm.
Alternatively, described metal plug comprises metal material and electricity isolated layer, and described electricity isolated layer is between described metal material and covering substrate.
Alternatively, the thickness of described electricity isolated layer is 1000 ~ 3000
.
Alternatively, the metal material in described metal plug is copper, and the material of described testing cushion is copper.
Compared with prior art, technical scheme of the present invention has the following advantages:
At the first surface of Semiconductor substrate, there are components and parts, there is the testing cushion that surface exposes Semiconductor substrate first surface in described Semiconductor substrate; Etch the second surface of described covering substrate, form the cavity of the components and parts on holding semiconductor substrate; Etch described covering substrate second surface, in described covering substrate, form opening, backward described opening in fill metal material, in covering substrate, form metal plug; The second surface of described covering substrate and the first surface of Semiconductor substrate is made to fit afterwards, make the components and parts in described Semiconductor substrate be positioned at the cavity of covering substrate, and the metal plug in described covering substrate is fixedly connected with the testing cushion in Semiconductor substrate; Etch the first surface of described covering substrate, until expose described metal plug, make described metal plug run through covering substrate first surface and second surface, form semiconductor devices.In the electric performance test operation of above-mentioned semiconductor device, the tester connection of components and parts and outside directly can be realized by described metal plug, complete the electric performance test operation to components and parts, thus simplify the electric performance test operation of semiconductor devices, and the success rate that the electric performance test operation improving semiconductor devices is carried out.
Accompanying drawing explanation
Fig. 1 ~ 3 are process schematic of the WAT test of existing MEMS chip;
Fig. 4 ~ 10 are structural representations of the formation method of the semiconductor devices that one embodiment of the invention provides.
Detailed description of the invention
As described in background, in semiconductor fabrication, the semiconductor devices to having manufactured is needed to test, as WAT test, thus the problem in Timeliness coverage manufacture of semiconductor, and be adjusted accordingly.
But, in existing test process, need the semiconductor devices of shaping to open, the testing cushion of semiconductor devices forms opening, and testing needle card is inserted in described opening, with continuity test pad, thus carry out corresponding test.This cumbersome, operation precision requirement is high, testing needle card not so can be caused to damage equivalent risk, thus cause test crash.
For this reason, the invention provides a kind of formation method of semiconductor devices and this semiconductor devices.Directly form the metal plug be electrically connected with testing cushion on the semiconductor device, thus change the technique that traditional employing testing needle card completes semiconducter device testing, simplify the test technology process of semiconductor devices, and improve the success rate of test technology.
For enabling above-mentioned purpose of the present invention, feature and advantage more become apparent, and are described in detail specific embodiments of the invention below in conjunction with accompanying drawing.
The flowage structure schematic diagram of the formation method of the semiconductor devices that Fig. 4 ~ Figure 10 provides for the present embodiment.Its detailed process comprises:
Shown in figure 4, provide semi-conductive substrate 100.The upper surface (that is, the first surface of Semiconductor substrate) of described Semiconductor substrate 100 has components and parts 110, and described components and parts 110 are raised in the upper surface of described Semiconductor substrate 100.In described Semiconductor substrate 100, also have testing cushion 120, the upper surface with described Semiconductor substrate 100 is exposed on the surface of described testing cushion 120.Keep at a certain distance away, in non-contact structure between described testing cushion 120 and components and parts 110.Described components and parts 110 and testing cushion 120 are by being located at the interconnection line electrical connection in described Semiconductor substrate 100.
Described Semiconductor substrate 100 can be silicon substrate, and also can be germanium, germanium silicon, gallium arsenide substrate or silicon-on-insulator substrate, common Semiconductor substrate all can be used as the Semiconductor substrate in the present embodiment.
In the present embodiment, described Semiconductor substrate 100 is silicon substrate.
Described components and parts 110 can be the electric elements of arbitrary integrated circuit, or IC chip.The present embodiment is described components and parts for MEMS chip.
In the present embodiment, described testing cushion (test pad) 120 is metal gasket, is chosen as copper lining.
Described Semiconductor substrate 100 forms described MEMS chip 110 and testing cushion 120, and the electrical connection technique of described MEMS chip 110 and testing cushion 120 is the maturation process of this area, does not repeat them here.
Shown in figure 5, provide a covering substrate 200, described covering substrate 200 comprises upper surface (that is, the first surface of covering substrate) 201 and lower surface (that is, the second surface of covering substrate) 202.Described covering substrate 200 is for covering the MEMS chip 110 in described Semiconductor substrate 100.
Etch the lower surface 202 of described covering substrate 200, in described covering substrate 200, form opening 210.
In the present embodiment, the degree of depth of described opening 210 is chosen as 200 ± 50 μm, and aperture is 20 ± 10 μm.
Described opening 210 formation process specifically comprises: first on the lower surface 202 of described covering substrate 200, form photoresist layer, after through exposure, after developing process, pattern is formed in described photoresist layer, and with the photoresist layer after patterning for covering substrate described in mask etching 200, formed described opening 210.Above-mentioned technique is the maturation process of this area, does not repeat them here.
Afterwards, in the opening 210 of described covering substrate 200, metal plug is formed.The formation process of described metal plug specifically comprises:
Shown in figure 6, first in described opening 210, form one deck electricity isolated layer 211.The thickness of described electricity isolated layer 211 is 1000 ~ 3000
.
In the present embodiment, described electricity isolated layer 211 is chosen as TEOS(ethyl orthosilicate) layer, silicon oxide layer etc., its formation process is CVD(chemical vapour deposition (CVD)) technique; Or can thermal oxidation technology be adopted, form one deck silicon oxide layer at the sidewall of described opening 210 and bottom.Described electricity isolated layer 211 layers of formation process are prior art, do not repeat them here.
Shown in figure 7, afterwards, then in described opening 210, fill full metal material, to form metal plug 220.
In the present embodiment, the metal material adopted is copper, and it is identical with the material of testing cushion 120, thus is convenient to follow-up described testing cushion 120 and metal plug binding.
In the present embodiment, the technique of filling metal material in opening 210 comprises: first can adopt such as PVD(physical vapour deposition (PVD)) technique first forms one deck copper seed layer above described electricity isolated layer 211, afterwards, electroplating technology is adopted to form the copper material bed of material on described copper seed layer basis, to fill up described opening 210, and adopting CMP(chemical mechanical polishing method afterwards) technique makes the surface of the described copper material bed of material flush with the lower surface 202 of described covering substrate 200, thus formation metal plug 220.
Shown in figure 8, after the described metal plug 220 of formation, continue the lower surface 202 of the described covering substrate 200 of etching, in described covering substrate 200, form cavity 230.
The formation process of described cavity 230 comprises, and first on the lower surface 202 of described covering substrate 200, covers photoresist layer, after through techniques such as exposure, developments, photoresist layer described in patterning; And with the lower surface 202 that the photoresist layer after patterning is covering substrate described in mask etching 200, thus form described cavity 230 in described covering substrate 200.Detailed process is the maturation process of this area, does not repeat them here.
Afterwards, shown in figure 9, after the described cavity 230 of formation, described covering substrate 200 is covered in described Semiconductor substrate 100.The lower surface 202 of described covering substrate 200 is fitted with the upper surface of described Semiconductor substrate 100, and described MEMS chip 110 is positioned in described cavity 230, and described metal plug 220 is fixedly connected with described testing cushion 120.
In the present embodiment, the technique that described metal plug 220 is fixedly connected with described testing cushion 120 is binding technique, and detailed process comprises:
Described covering substrate 200 is covered after in described Semiconductor substrate 100, metal plug 220 in described covering substrate 200 surface is fitted with the surface of the testing cushion 120 in Semiconductor substrate 100, the temperature in reaction chamber is regulated to be 350 ± 50 DEG C, pressure is 40 ± 20KN, keeps described metal plug 220 to contact 10 ~ 40min(minute with testing cushion 120).In this process, testing cushion 120 and the copper generation atomic migration in metal plug 220, thus realize testing cushion 120 and metal plug 220 binding.
Then with reference to shown in Figure 10, the upper surface 201 of described covering substrate 200 is ground, until expose described metal plug 220.
In the present embodiment, the method for described grinding is chosen as CMP, the concrete stepping rate that can adopt 0.2 ~ 4 μm/s, and 1000 ~ 3000 turns/min pad rotating speed grinds described covering substrate 200.
Afterwards, above described Semiconductor substrate 100 and covering substrate 200, adopt the process deposits dielectric layer (not shown) such as CVD, to wrap up described covering substrate 200, adopt the technique abrasive media layers such as CMP, make the upper surface flush of the surface of described dielectric layer and described covering substrate 200.
This enforcement also provides the semiconductor devices obtained by formation method adopting above-mentioned semiconductor.Its concrete structure, with reference to shown in Figure 10, comprising:
Semiconductor substrate 100, the upper surface (that is, the first surface of Semiconductor substrate) of described Semiconductor substrate 100 has components and parts 110, has the testing cushion 120 that surface is exposed to Semiconductor substrate 100 upper surface in described Semiconductor substrate 100.Noncontact between described components and parts 110 and testing cushion 120, and by the interconnection line electrical connection in described Semiconductor substrate 100.
Be covered in the covering substrate 200 above described Semiconductor substrate 100, the lower surface (that is, the second surface of covering substrate) of described covering substrate 200 and the upper surface of described Semiconductor substrate 100 are (namely.The first surface of Semiconductor substrate) laminating; Wherein, in described covering substrate 200, be formed with cavity 230, described components and parts 110 are positioned at described cavity 230;
In described covering substrate 200, be formed with the metal plug 220 running through described covering substrate upper surface (that is, the first surface of covering substrate) and lower surface (that is, the second surface of covering substrate), described metal plug 220 is fixedly connected with described testing cushion 120.
In the present embodiment, the degree of depth of described metal plug 220 is 200 ± 50 μm, and width is 20 ± 10 μm.
Described metal plug 200 comprises metal material and electricity isolated layer 211(is shown with reference to figure 6).Described electricity isolated layer 211 wraps described metal material, and between described metal material and covering substrate 200.
In the present embodiment, the thickness of described electricity isolated layer 211 is 1000 ~ 3000
, material is chosen as TEOS or silicon oxide layer dielectric material.
In the present embodiment, the metal material in described metal plug 220 and testing cushion 120 be all chosen as copper.
Described semiconductor devices also comprises the dielectric layer (not shown) be covered in above described Semiconductor substrate 100, and described dielectric layer wraps described covering substrate 200 periphery, and the upper surface flush of dielectric layer upper surface and described covering substrate 200.
In the test process of described semiconductor devices, the metal plug 220 running through the described upper and lower surface of covering substrate 200 directly connects outside tester, to realize the testing electrical property of semiconductor devices.Compared to the test step of existing employing testing needle card, it not only avoid and reopens semiconductor devices, exposes the cumbersome process such as testing cushion, and avoids the defects such as testing needle card damage.It greatly improves the convenient degree of semiconductor device electrical property test and the success rate of test step, to improve the efficiency of semiconducter device testing.
Although the present invention discloses as above, the present invention is not defined in this.Any those skilled in the art, without departing from the spirit and scope of the present invention, all can make various changes or modifications, and therefore protection scope of the present invention should be as the criterion with claim limited range.
Claims (11)
1. a formation method for semiconductor devices, is characterized in that, comprising:
Semiconductor substrate is provided, the first surface of described Semiconductor substrate has components and parts, there is in described Semiconductor substrate the testing cushion that surface is exposed to Semiconductor substrate first surface, noncontact between described components and parts and testing cushion, and by the interconnection line in described Semiconductor substrate by described components and parts and testing cushion electrical connection;
Covering substrate is provided, etches the second surface of described covering substrate, in described covering substrate, form opening;
In described opening, fill full metal material, form metal plug;
Etch the second surface of described covering substrate, in described covering substrate, form cavity;
The second surface of the first surface of described Semiconductor substrate and described covering substrate is fitted, makes the components and parts in described Semiconductor substrate be positioned at described cavity, and the testing cushion in described Semiconductor substrate is fixedly connected with described metal plug;
Grind the first surface of described covering substrate, until expose described metal plug, the first surface of described covering substrate is relative with the second surface position of covering substrate.
2. the formation method of semiconductor devices as claimed in claim 1, it is characterized in that, the degree of depth of described opening is 200 ± 50 μm, and aperture is 20 ± 10 μm.
3. the formation method of semiconductor devices as claimed in claim 1, it is characterized in that, the material of described testing cushion is copper, and described metal material is copper.
4. the formation method of semiconductor devices as claimed in claim 1, it is characterized in that, the method that described testing cushion is fixedly connected with described metal plug is binding technique, and described binding technique comprises:
At the temperature of 350 ± 50 DEG C, under the pressure of 40 ± 20KN, metal plug is kept to contact 10 ~ 40min with testing cushion.
5. the formation method of semiconductor devices as claimed in claim 1, it is characterized in that, the forming process of described metal plug comprises: form electricity isolated layer at the sidewall of described opening and bottom, backward described opening in fill full metal material, to form described metal plug.
6. the formation method of semiconductor devices as claimed in claim 5, it is characterized in that, the thickness of described electricity isolated layer is 1000 ~ 3000
.
7. a semiconductor devices, is characterized in that, comprising:
Semiconductor substrate, the first surface of described Semiconductor substrate has components and parts, there is in described Semiconductor substrate the testing cushion that surface is exposed to Semiconductor substrate first surface, noncontact between described components and parts and testing cushion, and described components and parts are electrically connected by the interconnection line in described Semiconductor substrate with testing cushion;
Be covered in the covering substrate on the first surface of described Semiconductor substrate, the second surface of described covering substrate and the first surface of described Semiconductor substrate are fitted, wherein, in described covering substrate, offer cavity, the components and parts in described Semiconductor substrate are positioned at described cavity;
The metal plug running through the second surface of described covering substrate and the first surface of covering substrate is formed in described covering substrate, described metal plug is fixedly connected with described testing cushion, and the first surface of described covering substrate is relative with the second surface position of covering substrate.
8. semiconductor devices as claimed in claim 7, it is characterized in that, the degree of depth of described metal plug is 200 ± 50 μm, and width is 20 ± 10 μm.
9. semiconductor devices as claimed in claim 7, it is characterized in that, described metal plug comprises metal material and electricity isolated layer, and described electricity isolated layer is between described metal material and covering substrate.
10. semiconductor devices as claimed in claim 9, it is characterized in that, the thickness of described electricity isolated layer is 1000 ~ 3000
.
11. semiconductor devices as claimed in claim 9, it is characterized in that, the metal material in described metal plug is copper, and the material of described testing cushion is copper.
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| CN202988703U (en) * | 2012-11-20 | 2013-06-12 | 苏州敏芯微电子技术有限公司 | Micro-electromechanical system device |
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|---|---|---|---|---|
| CN1508968A (en) * | 2002-12-19 | 2004-06-30 | ������������ʽ���� | Electronic element and its manufacturing method |
| US20070099395A1 (en) * | 2005-11-03 | 2007-05-03 | Uppili Sridhar | Wafer level packaging process |
| EP2009710A2 (en) * | 2007-06-27 | 2008-12-31 | Nihon Dempa Kogyo Co., Ltd. | Piezoelectric component and manufacturing method thereof |
| CN101350342A (en) * | 2007-07-19 | 2009-01-21 | 联华电子股份有限公司 | Integrated circuit structure for test |
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