CN104851885A - OTP memory, storage array and manufacturing method thereof - Google Patents
OTP memory, storage array and manufacturing method thereof Download PDFInfo
- Publication number
- CN104851885A CN104851885A CN201410050250.6A CN201410050250A CN104851885A CN 104851885 A CN104851885 A CN 104851885A CN 201410050250 A CN201410050250 A CN 201410050250A CN 104851885 A CN104851885 A CN 104851885A
- Authority
- CN
- China
- Prior art keywords
- semiconductor layer
- otp memory
- gate oxide
- gate electrode
- present
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Semiconductor Memories (AREA)
Abstract
The invention provides an OTP memory which comprises the components of a first semiconductor layer with a first doping type; a second semiconductor layer with a second doping type on the first semiconductor layer; a gate oxide layer on the second semiconductor layer; and a gate electrode on the gate oxide layer; wherein the gate electrode is electrically connected with a word line. The first semiconductor layer is electrically connected with a bit line. Compared with a memory device based on an MOS device, the OTP memory is advantageous in that breakdown only occurs at the gate oxide layer; narrower distribution range of the current for read operation after programming is realized; and higher stability and higher yield rate of the device are realized. Furthermore, simpler manufacturing process is realized, thereby facilitating OTP memory size reduction along with process dimension reduction, and realizing easy integration with other processes.
Description
Technical field
The present invention relates to semiconductor storage unit field, particularly a kind of otp memory, storage array and manufacture method.
Background technology
OTP(One Time Programmable) memory device is the one of non-volatility memorizer, applicable program applies constant occasion.And have that stability is high based on the otp memory of anti-fuse structures, programming easily and with the feature such as CMOS technology is compatible, be widely used in the fields such as analog circuit fine setting, key, chip-stored, Redundancy Design and RFID.
At present, the otp memory of most anti-fuse structures is the memory construction based on mos capacitance, as shown in Figure 1, memory cell selects the low pressure storage tube 120 of pipe 110 and thin grid oxygen to form by the high pressure of thick grid oxygen, wherein, high pressure selects pipe 110 to be switch element, and low pressure selects pipe 120 to be memory element.When programming, apply high voltage between WL and BL, first low pressure storage tube 120 punctures, the grid of rear low pressure storage tube of namely programming and drain electrode conducting.When read operation, apply operating voltage between WL and BL, the high pressure of the memory cell be programmed selects pipe to open, and namely between WL and BL, have electric current, the memory cell be not programmed does not have electric current, thus, realize the identification of store status.
But the breakdown area of the low pressure storage tube of the memory of this structure has certain randomness, breakdown point may be positioned at raceway groove, LDD region or Halo transition region, and like this, when causing read operation, CURRENT DISTRIBUTION scope is comparatively wide, affects stability and the yield of device.
Summary of the invention
The present invention is intended to for the problems referred to above provide a kind of feasible solution, and provide a kind of otp memory, storage array and manufacture method, breakdown area is single, read current narrow distribution range after programming.
The invention provides a kind of otp memory, comprising:
There is the first semiconductor layer of the first doping type;
Second semiconductor layer with the second doping type on first semiconductor layer;
Gate oxide on second semiconductor layer;
Gate electrode on gate oxide;
Wherein, gate electrode electrical connection wordline, the first semiconductor layer electrical connection bit line.
Alternatively, the thickness of described gate oxide is less than or equal to 5um.
Alternatively, described first semiconductor layer is bit line.
Alternatively, described gate electrode is wordline.
Further, present invention also offers the memory array be made up of above-mentioned memory.
In addition, present invention also offers the manufacture method of otp memory, comprising:
Semiconductor substrate is provided;
Form first semiconductor layer with the first doping type over the substrate;
Form second semiconductor layer with the second doping type on the first semiconductor layer;
Second semiconductor layer forms gate oxide;
Gate oxide forms gate electrode;
Wherein, gate electrode electrical connection wordline, the first semiconductor layer electrical connection bit line.
Alternatively, the method specifically comprises step:
Carry out ion implantation, in described substrate, form first semiconductor layer with the first kind;
There is at described first doped region Epitaxial growth the second semiconductor layer of Second Type;
Carry out mask, etch the second semiconductor layer, the first semiconductor layer and substrate successively, to form groove, the first semiconductor layer after etching is bit line;
Filling groove is to form isolation;
Deposit gate oxide and gate electrode;
Carry out mask, etching gate electrode, gate oxide, the second semiconductor layer and isolation, until expose the first semiconductor layer, the gate electrode after etching is wordline.
After exposure first semiconductor layer, continue the first semiconductor layer of etched portions thickness.
Alternatively, the thickness of described gate oxide is less than or equal to 5um.
The otp memory that the embodiment of the present invention provides, storage array and manufacture method, compare the memory device based on MOS device, puncture and occur over just gate oxide, and the CURRENT DISTRIBUTION scope of read operation is narrower after programming, and stability and the yield of device are better.In addition, its manufacturing process is more simple, is convenient to reduce along with reducing of process, is easy to integrated with other technique.
Accompanying drawing explanation
The present invention above-mentioned and/or additional aspect and advantage will become obvious and easy understand from the following description of the accompanying drawings of embodiments, wherein:
Fig. 1 shows the schematic equivalent circuit based on the otp memory unit of mos capacitance in prior art;
Fig. 2 shows the structural representation of the otp memory according to the embodiment of the present invention;
Fig. 3 shows the schematic equivalent circuit according to otp memory unit of the present invention;
Fig. 4 shows the schematic equivalent circuit of the otp memory array according to the embodiment of the present invention;
Fig. 5-9 shows the schematic cross-section forming each stage of otp memory according to the method for the embodiment of the present invention.
Embodiment
Be described below in detail embodiments of the invention, the example of described embodiment is shown in the drawings, and wherein same or similar label represents same or similar element or has element that is identical or similar functions from start to finish.Being exemplary below by the embodiment be described with reference to the drawings, only for explaining the present invention, and can not limitation of the present invention being interpreted as.
The invention provides a kind of otp memory part, shown in figure 2, comprising:
There is the first semiconductor layer 210 of the first doping type;
Second semiconductor layer 220 with the second doping type on first semiconductor layer 210;
Gate oxide 230 on second semiconductor layer 220;
Gate electrode 240 on gate oxide 230;
Wherein, gate electrode 240 is electrically connected wordline, and the first semiconductor layer 210 is electrically connected bit line.
Otp memory part provided by the invention is antifuse memory, in the present invention, as shown in Figure 3, for the schematic equivalent circuit of otp memory unit of the present invention, first semiconductor layer and the second semiconductor layer have different doping types, constitute PN junction diode 320, and pipe selected by the switch as otp memory unit of the present invention, gate electrode, gate oxide and the first semiconductor layer constitute electric capacity 310, as the storage tube of otp memory unit of the present invention.
For otp memory unit of the present invention, when programming, WL(wordline in the memory cell of required programming) upper offset high pressure Vpp, at BL(bit line) upper offset low pressure, this low pressure is generally 0V, also namely at gate electrode and the first semiconductor layer two ends bias high voltage, because gate oxide two ends have been biased high voltage, like this, gate oxide punctures over time.When read operation, in WL(wordline) the operating voltage Vdd of upper diode, at BL(bit line) upper offset low pressure, this low pressure is generally 0V, also the operating voltage of diode is namely biased at gate electrode and the first semiconductor layer two ends, for the memory cell of carrying out programming, oxide layer punctures owing to there occurs, be equivalent to the two ends biased operating voltage Vdd at diode, thus the PN junction diode conducting in this unit, BL can detect electric current, and for the memory cell of not carrying out programming, this PN junction not conducting, BL do not have electric current, thus, can be determined by the current signal on BL that the store status of memory cell is for " 1 " or " 0 ".
Otp memory provided by the invention, compares the memory device based on MOS device, punctures and occur over just gate oxide, and the CURRENT DISTRIBUTION scope of read operation is narrower after programming, and stability and the yield of device are better.In addition, its manufacturing process is more simple, is convenient to reduce along with reducing of process, is easy to integrated with other technique.
Utilize otp memory of the present invention to form memory array, the grid electrical connection wordline of memory cell forms a line, and the first semiconductor layer electrical connection bit line of memory cell forms row.As shown in Figure 4, for the 2x2 memory array be made up of otp memory unit of the present invention, when programming to memory cell 410, by biased to WL (1) bias high voltage Vpp, BL (1) 0V, other WL without the need to the memory cell of programming are biased 0V, BL and are biased Vpp; When memory cell 410 read operation, WL (1) operating voltage Vdd, BL (1) are connect current sensitive amplifier, other WL without the need to the memory cell of read operation are biased 0V, BL and are biased Vdd or shutoff, thus realize programming and the read operation of storage array.In the present invention, high pressure Vpp instigates to obtain the voltage that can puncture under the voltage of gate oxide between gate electrode and the first semiconductor layer.
In addition, present invention also offers the manufacture method of this device, comprise step:
Semiconductor substrate is provided;
Form first semiconductor layer with the first doping type over the substrate;
Form second semiconductor layer with the second doping type on the first semiconductor layer;
Second semiconductor layer forms gate oxide;
Gate oxide forms gate electrode;
Wherein, gate electrode electrical connection wordline, the first semiconductor layer electrical connection bit line.
For a better understanding of the present invention, below with reference to accompanying drawing, the embodiment of the present invention and manufacture method are described in detail.
First, provide Semiconductor substrate 200, shown in figure 5.
In the present invention, described Semiconductor substrate can be Si substrate, Ge substrate, SiGe substrate, SOI(silicon-on-insulator, Silicon On Insulator) or GOI(germanium on insulator, Germanium OnInsulator) etc.Described Semiconductor substrate can also be the substrate comprising other elemental semiconductors or compound semiconductor, such as GaAs, InP or SiC etc. can also be laminated construction, such as Si/SiGe etc., all right other epitaxial structures, such as SGOI(silicon germanium on insulator) etc.
In the present embodiment, described Semiconductor substrate is silicon substrate.
Then, carry out ion implantation, thus on substrate, form first semiconductor layer 210 with the first doping, shown in figure 5, Fig. 6.
In the present embodiment, carry out the injection of N-type ion, in Semiconductor substrate 200, form first semiconductor layer 210 with N-type doping, with the integrated technique of MOS device, the processing step of N-type active area can be utilized to form this first semiconductor layer.
Then, there is the second semiconductor layer 220 of Second Type, as shown in Figure 6 at described first doped region Epitaxial growth.
In the present embodiment, form the second semiconductor layer 220 of P type doping at the first semiconductor layer 210 Epitaxial growth, this second semiconductor layer can be Si, Ge or SiGe etc. of doping.
Then, carry out mask, etch the second semiconductor layer 220, first semiconductor layer 210 and substrate 200 successively, to form groove 202, the first semiconductor layer 210 after etching is bit line, shown in figure 7.
In the present embodiment, after carrying out mask, carry out the etching of the second semiconductor layer 220, first semiconductor layer 210 and substrate 200 successively, while forming isolated groove, form bit line, with the integrated technique of MOS device, bit line can be formed by STI isolation technology step.
Then, filling groove to form isolation 202, as shown in Figure 7.
In the present embodiment, after filling the isolated material of silicon dioxide, planarization is carried out to this isolated material, such as, adopts CMP(cmp) method, form isolation 202.
Then, deposit gate oxide 230 and gate electrode 240, as shown in Figure 8.
In the present invention, gate oxide can be silicon dioxide or high-g value (having high dielectric constant relative to silicon dioxide), high K medium material such as hafnium base oxide, HfO2, HfSiO, HfSiON, HfTaO, HfTiO etc.The size of the programming high pressure Vpp when thickness of gate oxide layers determines memory cell programming, in the present embodiment, the thickness of gate oxide layers can be equal to or less than 5um, in the CMOS technology of 0.18um, the thickness of gate oxide layers is 2.9um, and programming high pressure Vpp is about 6.6V.Gate electrode can be polysilicon or metal gate material, such as, can be Ti, TiAl
x, TiN, TaN
x, HfN, TiC
x, TaC
xetc..With the integrated technique of MOS device, the gate dielectric layer of device and the formation process of grid can be utilized to form gate oxide layers and the gate electrode of memory device.
Finally, carry out mask, etching gate electrode 240, gate oxide 230, second semiconductor layer 220 and isolation 202, until expose the first semiconductor layer 210, the gate electrode 240 after etching is wordline, as shown in Figure 9.
In the present embodiment, carry out a mask, form device cell, form wordline simultaneously, with the integrated technique of MOS device, this step can be carried out by the processing step of patterning grid and gate dielectric layer.Further, after exposure first semiconductor layer, continue the first semiconductor layer of the segment thickness that etching exposes, as shown in Figure 9.
To the otp memory and the array which form the embodiment of the present invention, in the present embodiment, as shown in Figure 9, the first semiconductor layer 210 is bit line, and gate electrode 240 is wordline, and structure is simple and be easy to realize.
The above is only preferred embodiment of the present invention, not does any pro forma restriction to the present invention.
Although the present invention discloses as above with preferred embodiment, but and be not used to limit the present invention.Any those of ordinary skill in the art, do not departing under technical solution of the present invention ambit, the Method and Technology content of above-mentioned announcement all can be utilized to make many possible variations and modification to technical solution of the present invention, or be revised as the Equivalent embodiments of equivalent variations.Therefore, every content not departing from technical solution of the present invention, according to technical spirit of the present invention to any simple modification made for any of the above embodiments, equivalent variations and modification, all still belongs in the scope of technical solution of the present invention protection.
Claims (9)
1. an otp memory, is characterized in that, comprising:
There is the first semiconductor layer of the first doping type;
Second semiconductor layer with the second doping type on first semiconductor layer;
Gate oxide on second semiconductor layer;
Gate electrode on gate oxide.
2. otp memory according to claim 1, is characterized in that, the thickness of described gate oxide is less than or equal to 5um.
3. otp memory according to claim 1, is characterized in that, described first semiconductor layer is bit line.
4. otp memory according to claim 1, is characterized in that, described gate electrode is wordline.
5. an otp memory array, is characterized in that, the otp memory according to any one of claim 1-4 forms.
6. a manufacture method for otp memory array, is characterized in that, comprising:
Semiconductor substrate is provided;
Form first semiconductor layer with the first doping type over the substrate;
Form second semiconductor layer with the second doping type on the first semiconductor layer;
Second semiconductor layer forms gate oxide;
Gate oxide forms gate electrode;
Wherein, gate electrode electrical connection wordline, the first semiconductor layer electrical connection bit line.
7. the manufacture method of otp memory array according to claim 6, it is characterized in that, the method specifically comprises step:
Carry out ion implantation, in described substrate, form first semiconductor layer with the first kind;
There is at described first doped region Epitaxial growth the second semiconductor layer of Second Type;
Carry out mask, etch the second semiconductor layer, the first semiconductor layer and substrate successively, to form groove, the first semiconductor layer after etching is bit line;
Filling groove is to form isolation;
Deposit gate oxide and gate electrode;
Carry out mask, etching gate electrode, gate oxide, the second semiconductor layer and isolation, until expose the first semiconductor layer, the gate electrode after etching is wordline.
8. the manufacture method of otp memory array according to claim 7, is characterized in that, after exposure first semiconductor layer, continues the first semiconductor layer of etched portions thickness.
9. the manufacture method of otp memory array according to claim 6, the thickness of described gate oxide is less than or equal to 5um.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410050250.6A CN104851885B (en) | 2014-02-13 | 2014-02-13 | A kind of manufacturing method of otp memory array |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410050250.6A CN104851885B (en) | 2014-02-13 | 2014-02-13 | A kind of manufacturing method of otp memory array |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN104851885A true CN104851885A (en) | 2015-08-19 |
| CN104851885B CN104851885B (en) | 2018-12-21 |
Family
ID=53851399
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410050250.6A Active CN104851885B (en) | 2014-02-13 | 2014-02-13 | A kind of manufacturing method of otp memory array |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN104851885B (en) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6185122B1 (en) * | 1998-11-16 | 2001-02-06 | Matrix Semiconductor, Inc. | Vertically stacked field programmable nonvolatile memory and method of fabrication |
| CN1503365A (en) * | 2002-11-27 | 2004-06-09 | 旺宏电子股份有限公司 | Mask type ROM having diode and mfg method thereof |
| CN101315906A (en) * | 2007-05-31 | 2008-12-03 | 和舰科技(苏州)有限公司 | Once programmable memory structure and manufacturing method thereof |
| CN101752002A (en) * | 2008-12-11 | 2010-06-23 | 旺宏电子股份有限公司 | Aluminum copper oxide based memory devices and methods for manufacture |
-
2014
- 2014-02-13 CN CN201410050250.6A patent/CN104851885B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6185122B1 (en) * | 1998-11-16 | 2001-02-06 | Matrix Semiconductor, Inc. | Vertically stacked field programmable nonvolatile memory and method of fabrication |
| CN1503365A (en) * | 2002-11-27 | 2004-06-09 | 旺宏电子股份有限公司 | Mask type ROM having diode and mfg method thereof |
| CN101315906A (en) * | 2007-05-31 | 2008-12-03 | 和舰科技(苏州)有限公司 | Once programmable memory structure and manufacturing method thereof |
| CN101752002A (en) * | 2008-12-11 | 2010-06-23 | 旺宏电子股份有限公司 | Aluminum copper oxide based memory devices and methods for manufacture |
Also Published As
| Publication number | Publication date |
|---|---|
| CN104851885B (en) | 2018-12-21 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US20200144279A1 (en) | High voltage cmos with co-planar upper gate surfaces for embedded non-volatile memory | |
| US20150194433A1 (en) | Gate substantial contact based one-time programmable device | |
| TWI654748B (en) | Non-volatile memory (nvm) device in semiconductor-on-insulator ( soi) technology and method of fabricating an according device | |
| US9111867B2 (en) | Split gate nanocrystal memory integration | |
| US9917090B1 (en) | Vertical antifuse structures | |
| US9716097B2 (en) | Techniques to avoid or limit implant punch through in split gate flash memory devices | |
| US10811410B2 (en) | Simultaneously fabricating a high voltage transistor and a FinFET | |
| US7687340B2 (en) | Protect diodes for hybrid-orientation substrate structures | |
| KR102178025B1 (en) | OTP Cell Having a Reduced Layout Area | |
| US10038000B2 (en) | Memory cell and fabricating method thereof | |
| US8969940B1 (en) | Method of gate strapping in split-gate memory cell with inlaid gate | |
| US8952431B2 (en) | Stacked carbon-based FETs | |
| US10229919B2 (en) | Vertical field effect transistor including integrated antifuse | |
| US9076791B1 (en) | MOS transistor operated as OTP cell with gate dielectric operating as an e-fuse element | |
| TW201810534A (en) | High-voltage transistor device | |
| US9583168B1 (en) | Drive current enhancement for integrated circuit memory structures | |
| KR101458332B1 (en) | Semiconductor device, method for manufacturing same, and nonvolatile semiconductor memory device | |
| US10008508B2 (en) | One time programmable (OTP) cell having improved programming reliability | |
| US20150236110A1 (en) | Split gate cells for embedded flash memory | |
| US20230020696A1 (en) | Memory device and formation method thereof | |
| US9704569B1 (en) | One time programmable read-only memory (ROM) in SOI CMOS | |
| CN104851885A (en) | OTP memory, storage array and manufacturing method thereof | |
| US20160322372A1 (en) | Semiconductor device and method for fabricating the same | |
| US8437184B1 (en) | Method of controlling a vertical dual-gate dynamic random access memory | |
| TW202205543A (en) | Method for manufacturing a seoi integrated circuit chip |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| EXSB | Decision made by sipo to initiate substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| TR01 | Transfer of patent right | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20220317 Address after: Room 108, floor 1, building 4, No. 2 dacuodeng Hutong, Dongcheng District, Beijing 100010 Patentee after: Beijing Zhongke micro Investment Management Co.,Ltd. Address before: 100029 Beijing city Chaoyang District Beitucheng West Road No. 3 Patentee before: Institute of Microelectronics, Chinese Academy of Sciences |