CN104915195B - A kind of method that neural computing is realized based on field programmable gate array - Google Patents
A kind of method that neural computing is realized based on field programmable gate array Download PDFInfo
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- CN104915195B CN104915195B CN201510258018.6A CN201510258018A CN104915195B CN 104915195 B CN104915195 B CN 104915195B CN 201510258018 A CN201510258018 A CN 201510258018A CN 104915195 B CN104915195 B CN 104915195B
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Abstract
The present invention relates to a kind of method that neural computing is realized based on field programmable gate array, belong to neural computing technical field.Initially set up the mapping relations of basic logic unit and each part of neutral net in field programmable gate array, with programming language, the function of each basic logic unit of field programmable gate array is described, the model for all basic logic units established in field programmable gate array, by the mapping relations of FPGA and neural network structure come simulative neural network, by between FPGA basic logic units interconnecting relation reconfigure and the operational capability of its own complete network self study process, the method consistent with actual nerve network structure compared to pursuit at this stage, the present invention larger reduction hardware spending of energy when simulating the neutral net of identical complexity.Secondly, the present invention completes the learning process of neutral net at the scene on programmable gate array software model, greatly reduces the cycle of study, saves time cost.
Description
Technical field
The present invention relates to a kind of method that neural computing is realized based on field programmable gate array, belong to neutral net
Computing technique field.
Background technology
Configurable logic blocks (Configurable is included based on field programmable gate array (hereinafter referred to as FPGA) inside
LogicBlock, hereinafter referred to as CLB), input/output module (Input Output Block, hereinafter referred to as IOB) and inside connects
Three parts of line (Interconnect).Wherein, CLB is the basic logic unit in FPGA, in the FPGA devices of Xilinx companies
In part, CLB is made up of multiple (generally 4 or 2) identical logic chips (Slice) and additional logic such as switch arrays.Often
Individual CLB modules can be not only used for realizing combinational logic, sequential logic, be also configured as distributed random access internal memory
(Random Access Memory, hereinafter referred to as RAM) and distributed read-only storage (Read Only Memory, it is simple below
Claim ROM).Logic chip (Slice) in logic chip (Slice) internal structure is by two 4 functions inputted, carry logic, arithmetic
Logic, storage logic sum function multiplexer composition.
Computer based on von Neumann system can be unable to reach under the application scenarios of self study deviation artificial intelligence
Satisfactory result, such as：Information fuzzy processing, intelligent robot, image recognition and screening etc..Currently, neutral net someone
Artificial neural networks (Artificial Neural Network, hereinafter referred to as ANN) and impulsive neural networks (Spiking
Neuron Networks, hereinafter referred to as SNN) two kinds of different implementations.ANN implementation relies primarily on deep learning
Algorithm, so as to reach a process of similar people's study.SNN fully simulates the operation principle of brain, to realize neural calculating.
Human brain is macroscopically that complicated internet forms an organic whole, and has substantial amounts of computing unit in FPGA
With configurable mutual contact mode, complex network is may make up using computing unit and interconnector (Interconnect), realizes god
It is computed, simulates Brain behavior.The popular method based on FPGA simulative neural networks is generated by EDA synthesis tools at this stage
Burning is in FPGA after circuit, and several basic logic unit combinations form and the same or similar structure of single neuron, and then
Whole network is formed, such as SNN so as to which simulative neural network, completion nerve calculate.In view of single basic logic unit has had foot
Enough operational capabilities, though the energy simulative neural network behavior of this method generates the huge wasting of resources.
The content of the invention
, will be existing the purpose of the present invention is to propose to a kind of method that neural computing is realized based on field programmable gate array
Complicated calculations possessed by field programmable gate array and the storage direct simulative neural network of network, with field programmable gate array
The part that basic logic unit comes in map neural network, field programmable gate array is set to have certainly by certain method
The interconnecting relation between adjusting device is adapted to, to realize neural computing.
The method proposed by the present invention that neural computing is realized based on field programmable gate array, is comprised the following steps：
(1) mapping relations of basic logic unit and each part of neutral net in field programmable gate array are established；
(2) function of each basic logic unit of field programmable gate array is described with programming language, foundation scene can compile
The model of all basic logic units in journey gate array, by the model of all basic logic units according to field-programmable gate array
The structure of row is combined, and obtains the model of field programmable gate array；
(3) it is that scene can to the multiple configuration signals of model specification of the field programmable gate array of step (2), configuration signal
The function of the interconnecting relation of each basic logic unit and each basic logic unit definition in gate array is programmed, makes field programmable gate
Each basic logic unit in Array Model forms the interconnecting relation of neural network, corresponding with neural computing by one
Input signal is applied in field programmable gate array model, the record output signal corresponding with the interconnecting relation；
(4) according to Learning Algorithm, the interconnecting relation between basic logic unit in Optimization Steps (3), make
The corresponding specific input of field programmable gate array software model is basic with specific output, on-site programmable gate array internal
Stable interconnecting relation is formed between logic unit；
(5) the stable interconnecting relation of step (4) is mapped in field programmable gate array, the field programmable gate array
Complete neural computing.
The method proposed by the present invention that neural computing is realized based on field programmable gate array, its advantage are：This hair
It is bright by the mapping relations of FPGA and neural network structure come simulative neural network, pass through to interconnect between FPGA basic logic units and close
System reconfigure and the operational capability of its own complete network self study process, compared at this stage pursue and actual nerve
The consistent method of network structure, the reduction hardware spending that the present invention can be larger when simulating the neutral net of identical complexity.Its
Secondary, the present invention completes the learning process of neutral net at the scene on programmable gate array software model, greatly reduce study
Cycle, save time cost.
Brief description of the drawings
Fig. 1 is the FPGA proposed by the present invention for realizing that the method for neural computing is related to based on field programmable gate array
Elementary cell and the mapping relations figure of actual nerve cell, wherein logic chip (Slice) unit can be used as neuron, switch arrays
(Switch Matrix) unit can be used as cynapse, and interconnector (Interconnect) can be used as aixs cylinder.
Embodiment
The method proposed by the present invention that neural computing is realized based on field programmable gate array, is comprised the following steps：
(1) mapping relations of basic logic unit and each part of neutral net in field programmable gate array are established；
For example, the logic blade unit (Slice) in field programmable gate array is regarded as the neuron in neutral net, can by scene
Switch arrays unit (Switch Matrix) in programming gate array is regarded as multiple cynapses in neutral net, can by scene
The interconnector of programming gate array is regarded as the aixs cylinder in neutral net, as shown in Figure 1.
(2) programming language, such as C language are used, describes the function of each basic logic unit of field programmable gate array, is established
The model of all basic logic units in field programmable gate array, by analyzing, field programmable gate array is each to patrol substantially
The circuit structure of unit is collected, understands its input/output relation and its control signal, with its function of programming language abstractdesription, is formed
The model of field programmable gate array basic logic unit.By the model of all basic logic units according to field-programmable gate array
The structure of row is combined, and obtains the model of field programmable gate array；Initial shape is in after the completion of being built due to neutral net
State, its process learnt needs a large amount of and repeatedly adjusts interconnection architecture, and the god that real field programmable gate array is formed
Need constantly to adjust hardware language code in debugging process through network and burning is in field programmable gate array, whole process
Time-consuming and efficiency is low.And the field programmable gate array model that software is realized can be in a manner of conveniently and quickly speed is carried out
The structural adjustment of on-site programmable gate array internal.
(3) it is that scene can to the multiple configuration signals of model specification of the field programmable gate array of step (2), configuration signal
The function of the interconnecting relation of each basic logic unit and each basic logic unit definition in gate array is programmed, makes field programmable gate
Each basic logic unit in Array Model forms the interconnecting relation of neural network, corresponding with neural computing by one
Input signal is applied in field programmable gate array model, such as picture signal, the record output corresponding with the interconnecting relation
Signal；
(4) according to Learning Algorithm, such as impulsive neural networks (Shared nearest neighbor clustering) learning algorithm, improve
The interconnecting relation of the basic logic unit formed in step (3), finally make field programmable gate array software model for specific
Input, it has specific output and its internal basic logic unit to have stable interconnecting relation；Such as to field programmable gate
During the data signal that Array Model input is transformed by image, field programmable gate array model can correspond in output image
II yard of the Chinese ASC of object.This is the training of whole scene programmable gate array software model, learning process.
(5) the stable interconnecting relation of step (4) is mapped in field programmable gate array, the field programmable gate array is complete
Into neural computing.
In the inventive method, multiple field programmable gate arrays can be cascaded, shape according to the needs of neural computing
Into field programmable gate array network to simulate larger neutral net.
One embodiment of the inventive method introduced below：
After completing FPGA modeling works, according to FPGA and the mapping relations of neutral net, FPGA models are configured so that FPGA
Neural network structure is formed between basic logic unit.Logic blade unit, which has, in field programmable gate array calculates, stores work(
Can, therefore can be as the neuron in neural network.Switch arrays unit in field programmable gate array can complete difference and patrol
The connection between blade unit is collected, therefore can be as the cynapse in neural network.The interconnector of field programmable gate array regard as
Aixs cylinder in neutral net is to transmit signal.By license plate for vehicle picture signal, i.e. picture element matrix is applied to as input signal
FPGA mode inputs end, is emulated to FPGA models, passes through impulsive neural networks (Shared nearest neighbor clustering) learning algorithm journey
The annexation of basic logic unit in sequence adjustment FPGA models, until the output signal of FPGA models is car plate in input signal
The code values of ASC II of numeral or letter.The annexation of basic logic unit in now FPGA models is copied into real FPGA
In, this FPGA is the function that Car license recognition can be achieved.
More than, only presently preferred embodiments of the present invention, but protection scope of the present invention is not limited thereto is any to be familiar with sheet
Those skilled in the art the invention discloses technical scope in, the change or replacement that can readily occur in should all be covered
Within protection scope of the present invention.Therefore, protection scope of the present invention should be defined by the protection domain that claim is defined.
Claims (1)
- A kind of 1. method that neural computing is realized based on field programmable gate array, it is characterised in that this method includes following Step：(1) mapping relations of basic logic unit and each part of neutral net in field programmable gate array are established；(2) function of each basic logic unit of field programmable gate array is described with C language, establishes field programmable gate array In all basic logic units model, the structure by the model of all basic logic units according to field programmable gate array It is combined, obtains the model of field programmable gate array；(3) it is field-programmable to the multiple configuration signals of model specification of the field programmable gate array of step (2), configuration signal The function of the interconnecting relation of each basic logic unit and each basic logic unit defines in gate array, makes field programmable gate array Each basic logic unit in model forms the interconnecting relation of neural network, and one corresponding with neural computing is inputted Signal is applied in field programmable gate array model, the record output signal corresponding with the interconnecting relation；(4) according to Learning Algorithm, the interconnecting relation between basic logic unit in Optimization Steps (3), scene is made The corresponding specific input of programmable gate array software model has specific output, on-site programmable gate array internal basic logic Stable interconnecting relation is formed between unit；(5) the stable interconnecting relation of step (4) is mapped in field programmable gate array, the field programmable gate array is completed Neural computing.
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| CN105279555B (en) * | 2015-10-28 | 2017-10-17 | 清华大学 | A kind of adaptive learning neural network implementation method based on evolution algorithm |
| CN105701540B (en) * | 2016-01-11 | 2017-12-19 | 清华大学 | A kind of self-generating neutral net construction method |
| CN105678379B (en) | 2016-01-12 | 2020-08-07 | 腾讯科技（深圳）有限公司 | CNN processing method and device |
| CN106991477B (en) * | 2016-01-20 | 2020-08-14 | 中科寒武纪科技股份有限公司 | Artificial neural network compression coding device and method |
| US11568232B2 (en) * | 2018-02-08 | 2023-01-31 | Quanta Computer Inc. | Deep learning FPGA converter |
| US20200117978A1 (en) * | 2018-10-12 | 2020-04-16 | Alibaba Group Holding Limited | Systems and methods for efficiently mapping neural networks to programmable logic devices |
| CN109685210A (en) * | 2018-12-29 | 2019-04-26 | 百度在线网络技术（北京）有限公司 | Convolutional neural networks processing method, convolutional neural networks device |
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