CN104934471A - Trench type power metal-oxide-semiconductor field effect transistor and manufacturing method thereof - Google Patents
Trench type power metal-oxide-semiconductor field effect transistor and manufacturing method thereof Download PDFInfo
- Publication number
- CN104934471A CN104934471A CN201410105142.4A CN201410105142A CN104934471A CN 104934471 A CN104934471 A CN 104934471A CN 201410105142 A CN201410105142 A CN 201410105142A CN 104934471 A CN104934471 A CN 104934471A
- Authority
- CN
- China
- Prior art keywords
- doped region
- insulating barrier
- effect transistor
- semiconductor field
- epitaxial layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Abstract
The invention provides a trench type power metal-oxide-semiconductor field effect transistor and a manufacturing method thereof. A grid electrode of the trench type power metal-oxide-semiconductor field effect transistor includes an upper doping area and a lower doping area, and a PN junction is formed. Thus, when the trench type power metal-oxide-semiconductor field effect transistor works, junction capacitance formed by the PN junction can be connected in series with capacitance between the grid electrode and a drain electrode, thereby enabling the equivalent capacitance of the grid electrode and the drain electrode to be decreased.
Description
Technical field
The present invention relates to a kind of power MOSFET transistor and manufacture method thereof, particularly relate to a kind of trench power metal-oxide semiconductor field-effect transistor and manufacture method thereof.
Background technology
Power MOSFET transistor (Power Metal Oxide Semiconductor FieldTransistor, Power MOSFET) be widely used in the switching device of electric device, be such as power supply unit, rectifier or low voltage motor controller etc.The design of vertical stratification taked by power MOSFET transistor now more, with lift elements density.And there is the power formula metal-oxide half field effect transistor of trench gate structure, not only have higher component density, also have lower conducting resistance, its advantage to expend under lower powered situation, and control voltage carries out the operation of element.
The work-loss costs of power-type metal-oxide half field effect transistor can be divided into switch cost (switchingloss) and the large class of conduction losses (conducting loss) two, and wherein the capacitance (Cgd) of gate/drain is the important parameter affecting switch cost.The too high meeting of gate/drain capacitance causes switch cost to increase, and then the switch speed of power-limiting type metal-oxide half field effect transistor, is unfavorable in application high-frequency circuit.
Summary of the invention
Technical problem to be solved by this invention is, there is provided a kind of trench power metal-oxide semiconductor field-effect transistor and its manufacture manufacture method for the deficiencies in the prior art, it has the grid of PN junction (PN junction) to reduce gate/drain capacitance by means of one.
Technical problem to be solved by this invention is achieved by the following technical solution:
A kind of trench power metal-oxide semiconductor field-effect transistor, comprises base material, epitaxial layer and multiple plough groove type transistor unit; Epitaxial layer is formed at above this base material, and multiple plough groove type transistor unit is formed in epitaxial layer, and wherein each plough groove type transistor unit comprises trench gate structure; Trench gate structure comprises groove and grid, and wherein channel shaped is formed in epitaxial layer, and the madial wall of groove forms an insulating barrier, and grid is formed in groove, and wherein grid to comprise on one doped region and once doped region, to form a PN junction.
The invention provides a kind of manufacture method of trench power metal-oxide semiconductor field-effect transistor, comprise and a base material is provided; Form an epitaxial layer above base material; One body dopant manufacture process is carried out to form one first doped region to epitaxial layer; Form multiple trench gate structure in epitaxial layer and this first doped region, each trench gate structure to comprise on one doped region with once doped region to form a PN junction; And one source pole doping manufacture process is carried out to form one source pole district and a matrix area to this first doped region, wherein this source area is positioned at above this matrix area.
The present invention also provides a kind of manufacture method of trench power metal-oxide semiconductor field-effect transistor, comprising: provide base material; Form epitaxial layer above base material; Body dopant manufacture process is carried out to form the first doped region to epitaxial layer; Form multiple groove in epitaxial layer; Formed one first type doped region and a Second-Type doped region in these grooves described one of them, wherein the first type doped region has irrigation canals and ditches, and Second-Type doped region is positioned within irrigation canals and ditches; One source pole doping manufacture process is carried out to the first doped region; And carry out a thermal diffusion manufacture process to form one source pole district and a matrix area, wherein the first type doped region forms doped region through thermal diffusion manufacture process, Second-Type doped region through thermal diffusion manufacture process to outdiffusion to form doped region on, wherein go up doped region and lower doped region forms a PN junction.
In sum, trench power metal-oxide semiconductor field-effect transistor of the present invention and its manufacture method can form PN junction in the gate.Because PN junction can produce junction capacitance (junction capacitance, Cj) under reverse bias, and junction capacitance is and gate/drain electric capacity (Cgd) series connection, therefore can reduce the equivalent capacitance value of gate/drain.
For above-mentioned feature and advantage of the present invention can be become apparent, preferred embodiment cited below particularly, and coordinate accompanying drawing, be described in detail below.
Accompanying drawing explanation
Figure 1A is the part section structural representation of the trench power metal-oxide semiconductor field-effect transistor of one embodiment of the invention;
Figure 1B is the part section structural representation of the trench power metal-oxide semiconductor field-effect transistor of one embodiment of the invention;
Fig. 2 A is the part section structural representation of the trench power metal-oxide semiconductor field-effect transistor of another embodiment of the present invention;
Fig. 2 B is the part section structural representation of the trench power metal-oxide semiconductor field-effect transistor of another embodiment of the present invention;
Fig. 3 is the flow chart of the trench power metal-oxide semiconductor field-effect transistor manufacture method of one embodiment of the invention;
Fig. 4 A to Fig. 4 M is the partial cutaway schematic of each step in the manufacture method of the trench power metal-oxide semiconductor field-effect transistor of one embodiment of the invention;
Fig. 5 is the flow chart of the trench power metal-oxide semiconductor field-effect transistor manufacture method of another embodiment of the present invention;
Fig. 6 A to Fig. 6 G is the partial cutaway schematic of each step in the manufacture method of the trench power metal-oxide semiconductor field-effect transistor of one embodiment of the invention.
[description of reference numerals]
Base material 100
Plough groove type transistor unit 101
Epitaxial layer 110
Drift region 120
Matrix area 130
Source area 140
Trench gate structure 150
Groove 151
Insulating barrier 154,154 ', 180
Grid 157,157 '
Upper doped region 155
Lower doped region 156,156 "
PN junction 102
Upper insulating barrier 152
Lower insulating barrier 153,153 "
First insulating barrier 153a, 180a
Second insulating barrier 153b, 180b
3rd insulating barrier 153c, 180c
First doped region 130 '
Oxide skin(coating) 153 '
Polysilicon structure 160
First space 151a
Second space 151b
First polysilicon structure 156 '
Second polysilicon structure 155 '
Irrigation canals and ditches 170
Process step S300 ~ S306, S500 ~ S504
Embodiment
Hereinafter, will illustrate that embodiments of the invention are to describe the present invention in detail by means of accompanying drawing, and the same reference numbers in accompanying drawing can in order to element like representation class.Aforementioned and other technology contents, feature and effect for the present invention, in the following detailed description coordinated with reference to each embodiment of accompanying drawing, can clearly present.The direction term mentioned in following examples such as: upper and lower, front, rear, left and right etc., is only the direction with reference to accompanying drawing.Therefore, the direction term of use is used to illustrate, and is not used for limiting the present invention.Further, in following each embodiment, adopt identical label to represent identical or approximate element.
Figure 1A is the part section structural representation of the trench power metal-oxide semiconductor field-effect transistor of one embodiment of the invention.Trench power metal-oxide semiconductor field-effect transistor comprises base material 100, epitaxial layer 110 and multiple plough groove type transistor unit (as 2 in Figure 1A).
Base material 100 has the first type conductive impurities of high concentration, and forms the first heavily doped region.First heavily doped region is intended for the drain electrode (drain) of trench power metal-oxide semiconductor field-effect transistor, and can be distributed in the regional area of base material 100 or be distributed in whole base material 100.Be be distributed in whole base material 100 in first heavily doped region of the present embodiment, but be only not used to for citing limit the present invention.Aforesaid first type conductive impurities can be N-type or P-type conduction impurity.Suppose that base material 100 is for silicon substrate, N-type conductive impurities is pentad ion, such as phosphonium ion or arsenic ion, and P-type conduction impurity is triad ion, such as boron ion, aluminium ion or gallium ion.
If trench power metal-oxide semiconductor field-effect transistor is N-type, base material 100 doped N-type conductive impurities.On the other hand, if P type trench power metal-oxide semiconductor field-effect transistor, then base material 100 doped p-type conductive impurities.In the embodiment of the present invention, be illustrate for N-type trench power metal-oxide semiconductor field-effect transistor.
Epitaxial layer (epitaxial layer) 110 is formed at above base material 100, and has the first type conductive impurities of low concentration.That is, for nmos pass transistor, base material 100 is N-type doping (N+) of high concentration, and epitaxial layer 110 is then N-type doping (N-) of low concentration.Otherwise, for PMOS transistor, base material 100 is P type doping (P+doping) of high concentration, and epitaxial layer 110 is then P type doping (P-doping) of low concentration.
Multiple plough groove type transistor unit 101 is formed in epitaxial layer 110, wherein each plough groove type transistor unit comprises drift region 120, matrix area (body region) 130, source area (drainregion) 140 and trench gate structure 150, and wherein matrix area 130 and source area 140 are formed in the epitaxial layer 110 of trench gate structure 150 side.
Furthermore, matrix area 130 is by means of adulterating Second-Type conductive impurities and being formed in epitaxial layer 110, source area 140 is then formed by means of the first type conductive impurities in matrix area 130 doped with high concentration, and source area 140 is the first halves being formed at matrix area 130.For example, pair nmos transistor, matrix area 130 is P type doping (as p type wells, P-well), and source area 140 is N-type doping.In addition, the doping content of matrix area 130 is less than the doping content of source area 140.
That is, by means of adulterate in zones of different variable concentrations and dissimilar conductive impurities, epitaxial layer 110 can be divided into drift region 120, matrix area 130 and source area 140.Matrix area 130 and source area 140 are the both sides being in close proximity to trench gate structure 150, and 120, drift region is near base material 100.In other words, matrix area 130 and source area 140 are the first halves being formed at epitaxial layer 110, and 120, drift region is formed at the Lower Half of epitaxial layer 110.
Trench gate structure 150 comprises groove 151, insulating barrier 154 and gate pole 157.Groove 151 is formed in epitaxial layer 120, and insulating barrier 154 and grid 157 are all formed in groove 151, and wherein insulating barrier 154 is positioned at the madial wall of groove 151, with isolated gate 157 and epitaxial layer 120.
Illustrate, the plough groove type transistor unit 101 of the embodiment of the present invention has deep trench (deep trench) structure.That is, groove 151 extends downward matrix area less than 130 by the surface of epitaxial layer 110, namely extends in drift region 120, and the closer base material 110 in the bottom of groove 151.
Aforesaid deep groove structure contributes to the breakdown voltage increasing plough groove type transistor unit 101, but but can increase the electric capacity (Cgd) of gate/drain.Accordingly, the grid 157 of the embodiment of the present invention to comprise on one doped region 155 and once doped region 156, wherein go up doped region 155 and lower doped region 156 forms a PN junction (PN junction) 102.In other words, adulterating veriform conductive impurities respectively in upper doped region 155 and lower doped region 156, and forms PN junction 102 between.In one embodiment, the position of PN junction 102 is lower than the lower edge of matrix area 130.In another embodiment, upper doped region 155 is the first halves being formed at groove 151, and lower doped region 156 is the Lower Halves being formed at groove 151, and PN junction 102 is the centre positions being positioned at about groove 151.The position of PN junction 102 can affect the equivalent capacity (Cgd) between the gate/drain of transistor, its position can be arranged at desired position according to the property requirements of element, for example, PN junction 102 is positioned at the lower edge of matrix area 130 or can reduces the equivalent capacity (Cgd) of gate/drain slightly lower than the place of matrix area 130 lower edge, significantly improves gate charge (Qgd) thus and can reduce the switch cost of element.
In addition, no matter the relative position that it should be noted that PN junction 102 and matrix area 130 why, as long as there is the existence of PN junction 102, its junction capacitance produced can be connected with the lock/capacitance of drain bottom trench gate structure 150, reduces the Equivalence Gate/capacitance of drain of integral member thus.PN junction 102 also can some microbit puts the change with shape because of the impact of doping or diffusion process, but all can reach effect of reduction Equivalence Gate/capacitance of drain.
Please refer to the part section structural representation that Figure 1B is the trench power metal-oxide semiconductor field-effect transistor of one embodiment of the invention.As shown in Figure 1B, due to deep groove structure, the electric capacity Cgd of gate/drain is formed by the first electric capacity C1, the second electric capacity C2 and the 3rd electric capacity C3 parallel connection, that is Cgd=C1+C2+C3.
As previously mentioned, too high gate/drain electric capacity can reduce the switch speed of groove type gold oxygen half field effect transistor.Therefore, in embodiments of the present invention, in grid 157, PN junction is formed.Because PN junction can produce junction capacitance (junction capacitance under reverse bias, Cj), and junction capacitance Cj is and gate/drain electric capacity (Cgd) series connection, makes equivalent capacity Ct, gate/drain electric capacity Cgd and junction capacitance Cj meet following relationship: Ct=(Cgd*Cj)/(Cgd+Cj).Because equivalent capacity Ct can be less than gate/drain electric capacity Cgd originally, the switch cost of groove type gold oxygen half field effect transistor thus can be made to reduce.
In addition, during in order to be in conducting state (ON) at plough groove type transistor unit, can produce junction capacitance Cj at the PN junction of grid 157, the conductive impurities adulterated in upper doped region 155 is identical with source area 140, and contrary with matrix area 130.For nmos pass transistor, source area 140 and upper doped region 155 are all N-type and adulterates, and matrix area 130 and lower doped region 156 are all P type and adulterate.
When applying positive bias to the upper doped region 155 of grid 157, the negative electrical charge of matrix area 130 can be accumulate to groove 151 side and form the carrier passage between source electrode and drain electrode, makes plough groove type transistor unit be in conducting state.But, then produce exhaustion region due to reverse bias at the PN junction of grid 157, junction capacitance Cj can be formed.Otherwise for PMOS transistor, source area 130 and upper doped region 155 are all P type and adulterates, and matrix area 140 and lower doped region 156 are all N-type and adulterate.
Suppose with the lower edge of matrix area 130 for datum level, groove 151 can roughly be divided into the first half and Lower Half.In one embodiment, insulating barrier 154 to comprise on one insulating barrier 152 and once insulating barrier 153, and wherein go up the interior sidewall surface that insulating barrier 152 is formed at groove 151 first half, lower insulating barrier 153 is the interior sidewall surface being formed at groove 151 Lower Half.In addition, the lower doped region 156 of grid 157 is also formed in the space of groove 151 Lower Half, and upper doped region 155 is then formed in the space of groove 151 first half.Upper insulating barrier 152 is in order to isolate matrix area 130 and source area 140 with upper doped region 155, and lower insulating barrier 153 is then in order to isolate lower doped region 156 and epitaxial layer 120.
In one embodiment, the thickness of lower insulating barrier 153 is greater than the thickness of insulating barrier 152, and in this case, as shown in Figure 1A, the width of upper doped region 155 can be greater than the width of lower doped region 156.Insulating barrier 154 is such as silicon dioxide, and grid 157 is such as polysilicon gate.
In the present embodiment, lower doped region 155 extends beyond the top of lower insulating barrier 153 by the bottom of groove 151, and roughly extends to directly over the top of lower insulating barrier 153 towards the two side of groove 151.In addition, the top of lower insulating barrier 153 and the position of PN junction 102 are close to the lower edge of matrix area 130.In Figure 1A embodiment, the top of lower insulating barrier 153 and the position of PN junction 102 are the lower edge a little less than matrix area 130.
Please refer to the part section structural representation that Fig. 2 A and Fig. 2 B is the trench power metal-oxide semiconductor field-effect transistor of another embodiment of the present invention.In the present embodiment, be still in grid 157 ' and there is upper doped region 155 and lower doped region 156 ", to form PN junction 102.With previous embodiment unlike, lower doped region 156 " by extending to bottom groove 151 close to lower insulating barrier 153 " top, but do not continue to extend to lower insulating barrier 153 towards both sides " top directly over.But, lower doped region 156 " top close to the lower edge of matrix area 130.In another embodiment, lower doped region 156 " top be can a little less than the lower edge of matrix area 130.
In addition, the insulating barrier 154 ' of the present embodiment comprises insulating barrier 152 and lower insulating barrier 153 ".Lower insulating barrier 153 " there is laminated construction, comprise the first insulating barrier 153a, the second insulating barrier 153b and the 3rd insulating barrier 153c, wherein the second insulating barrier 153b is located between the first insulating barrier 153a and the 3rd insulating barrier 153c.First insulating barrier 153a, the second insulating barrier 153b and the 3rd insulating barrier 153c can be oxide or nitride.Such as, first insulating barrier 153a and the 3rd insulating barrier 153c is oxide skin(coating), and the second insulating barrier 153b is nitride layer, lower doped region 156 can be prevented " in Impurity Diffusion to drift region 120, and then avoid causing bad impact to the work of trench power metal-oxide semiconductor field-effect transistor.In addition, lower insulating barrier 153 " top close to the lower edge of matrix area 130.In the embodiment of Fig. 2 A and Fig. 2 B, lower insulating barrier 153 " top be lower edge lower than matrix area 130.
In addition, the embodiment of the present invention provides the manufacture method of trench power metal-oxide semiconductor field-effect transistor.Please refer to Fig. 3 and coordinate with reference to Fig. 4 A to Fig. 4 I.Fig. 3 is the flow chart of the trench power metal-oxide semiconductor field-effect transistor manufacture method of one embodiment of the invention.Fig. 4 A to Fig. 4 I is the partial cutaway schematic of each step in the manufacture method of the trench power metal-oxide semiconductor field-effect transistor of one embodiment of the invention.
In S300, provide a base material 100.Then, in S301, an epitaxial layer (epitaxial layer) 110 is formed on base material 100.Please coordinate with reference to Fig. 4 A.As shown in Figure 4 A, base material 100, and on base material 100, formed an epitaxial layer (epitaxial layer) 110, wherein base material 100 is such as silicon substrate (silicon substrate), its first heavily doped region with high-dopant concentration is using the drain electrode (drain) as trench power metal-oxide semiconductor field-effect transistor, and epitaxial layer 110 is low doping concentration.
Then, carry out S303, a body dopant manufacture process is carried out to epitaxial layer 110, with in the side of epitaxial layer 110 away from base material 100, form the first doped region 130 as following body district 130 ', as shown in Figure 4 A.In addition, can find out by Fig. 4 A, other regions in epitaxial layer 110 form the drift region 120 of trench power metal-oxide semiconductor field-effect transistor.
Then, in S303, after formation first doped region 130 '.Form multiple groove in epitaxial layer 110, as shown in Figure 4 B.
Please also refer to Fig. 4 B, in epitaxial layer 110, form multiple groove 151.In one embodiment, be the position utilizing light shield (not shown) to define grid, and in epitaxial layer 110, produce a plurality of groove 151 in the mode of dry ecthing or wet etching.It should be noted that in the present embodiment, epitaxial layer 110 can first carry out adulterating to form the first doped region 130 ' before trench gate structure 150 is formed, and this first doped region 130 ' is the preparation area of matrix area 130.After trench gate structure 150 is formed, the first doped region 130 ' can be defined out corresponding matrix area 130.Thus, the thermal diffusion manufacture process that can avoid the formation of matrix area affects the doped structure in grid structure.
Then, in S304, formed the first type doped region in these grooves 151 described one of them, wherein the first type doped region has irrigation canals and ditches 151, and Second-Type doped region is then formed within irrigation canals and ditches 151.Detailed flow process please refer to Fig. 4 C to Fig. 4 L.
First, in Fig. 4 C to Fig. 4 H, formed if the lower insulating barrier 153 of Figure 1A is in the Lower Half of groove 151.Specifically, as shown in Figure 4 C, first code-pattern ground forms monoxide layer 153 ' on epitaxial layer 110.Oxide skin(coating) 153 ' can be silicon oxide layer (SiO2), can utilize thermal oxidation manufacture process to be formed.In other embodiments, physical vapour deposition (PVD) or chemical vapour deposition (CVD) mode also can be utilized to form oxide skin(coating) 153 '.Oxide skin(coating) 153 ' is formed at the surface of epitaxial layer 110 and the side wall surface of groove 151 and bottom.
Please refer to Fig. 4 D, form polysilicon structure 160 on oxide skin(coating) 153 ', and insert in groove 151.Polysilicon structure 160 can be containing the polysilicon structure (dopedpoly-Si) of conductive impurities or not containing the polysilicon structure (non-doped poly-Si) of conductive impurities.Then, as shown in Figure 4 E, eat-back (etch back) and remove oxide skin(coating) 153 ' polysilicon structure covered on the surface 160, and be positioned at the polysilicon structure 160 of groove 151 first half, and only leave the polysilicon structure 160 being positioned at groove 151 Lower Half.In Fig. 4 E, be positioned at the lower edge of top higher than the first doped region 130 ' of the polysilicon structure 160 of groove 151 Lower Half.
The oxide skin(coating) 153 ' on epitaxial layer 110 surface please refer to Fig. 4 F, with polysilicon structure 160 as cover power, carries out an etch process, will be covered in and be covered in the oxide skin(coating) 153 ' thinning of side wall surface of groove 151 first half.Illustrate, because the polysilicon structure 160 being positioned at groove 151 Lower Half is not removed in a previous step, so the thickness being positioned at the oxide skin(coating) 153 ' of groove 151 Lower Half is not affected.
Then, as shown in Figure 4 G, the polysilicon structure 160 being positioned at groove 151 is all removed.Now, the side wall surface of groove 151 inferior and superior halves covers the oxide skin(coating) 153 ' of different-thickness, and make groove 151 inner space can divide into the first larger space 151a and less second space 151b, wherein the first space 151a is positioned at above second space 151b, and the first space 151a is connected with second space 151b.This step can utilize selective etch mode, when not removing oxide skin(coating) 153 ', removes the polysilicon structure 160 in groove 151.
Please refer to Fig. 4 H, remove the oxide skin(coating) 153 ' of thinning.That is, the oxide skin(coating) 153 ' being covered in epitaxial layer 110 surface and being positioned at groove 151 first half is removed completely.When carrying out this step, the oxide skin(coating) 153 ' being positioned at groove 151 Lower Half also can removing by part.But because the oxide skin(coating) 153 ' thickness of groove 151 Lower Half is thicker, therefore when removing the oxide skin(coating) 153 ' of groove 151 first half, can't completely the oxide skin(coating) 153 ' of groove 151 Lower Half be removed.In this step, the oxide skin(coating) 153 ' of groove 151 Lower Half is the lower insulating barrier 153 in Figure 1A, and the top of lower insulating barrier 153 is lower than the lower edge of the first doped region 130.
Please refer to Fig. 4 I, in formation, insulating barrier 152 is on oxide skin(coating) 153 '.That is, the side wall surface of upper insulating barrier 152 covering groove 151 first half, and be formed at the surface of epitaxial layer 110.The manufacture process of insulating barrier 152 in formation, and the manufacture process being used for being formed oxide skin(coating) 153 ' in Fig. 4 C can be identical manufacture process, the upper insulating barrier 152 of such as deposition can be all utilize thermal oxidation manufacture process with deposited oxide layer 153 '.But in other embodiments, the manufacture process of insulating barrier 152 in formation, and the manufacture process being used for being formed oxide skin(coating) 153 ' in Fig. 4 C also can be different.In embodiments of the present invention, upper insulating barrier 152 has different thickness from oxide skin(coating) 153 ', and the thickness of the Thickness Ratio oxide skin(coating) 153 ' of upper insulating barrier 152 is thin.In addition, upper insulating barrier 152 and oxide skin(coating) 153 ' form insulating barrier 154 as shown in Figure 1A jointly.
Please refer to Fig. 4 J to Fig. 4 L, formed if the grid 157 of Figure 1A is in irrigation canals and ditches 151, wherein grid 157 comprises doped region 155 and lower doped region 156, and upper doped region 155 is positioned at above lower doped region 156 to form PN junction in groove 151.For the material of grid 157 for polysilicon is described as follows.
Specifically, as shown in fig. 4j, code-pattern ground forms one first polysilicon structure 156 ' and is covered on insulating barrier 152, and inserts in the second space 151b of groove 151.In addition, there are irrigation canals and ditches 170 in the first polysilicon structure 156 '.In the present embodiment, the first polysilicon structure 156 ' has the first type doped region.For example, when manufacturing nmos pass transistor, the first polysilicon structure 156 ' doped p-type conductive impurities, such as: boron, aluminium or gallium etc. and form the first type doped region.When forming the first polysilicon structure 156 ', can directly to be formed in interior doping chemical vapour deposition (CVD) manufacture process (in-situ doping CVD process).Be noted that with the polysilicon structure carrying out dopant deposition conductive impurities in interior doping chemical vapour deposition (CVD) manufacture process can save ion cloth plant (ion implant) and annealing time and cost.But, in other embodiments, also can first form unadulterated polysilicon structure, then plant manufacture process with ion cloth polysilicon structure is adulterated, then carry out annealing process.
Then, please refer to Fig. 4 K, form one second polysilicon structure 155 ' and be covered in the first polysilicon structure 156 ' comprehensively, and insert in irrigation canals and ditches 170.In the present embodiment, the second polysilicon structure 155 ' is to be formed in interior doping chemical vapour deposition (CVD) manufacture process (in-situ doping CVDprocess).Second polysilicon structure 155 ' has Second-Type doped region.As previously mentioned, when carrying out nmos pass transistor and manufacturing, the first type doped region is P type, then Second-Type doped region is N-type.
Subsequently, as illustrated in fig. 4l, eat-back the first polysilicon structure 156 ' and second polysilicon structure 155 ' of top, removal first doped region 130 ', leave the first polysilicon structure 156 ' and the second polysilicon structure 155 ' that are positioned at groove 151.
In S305, one source pole doping manufacture process is carried out to the first doped region 130 ', after in S306, carry out a thermal diffusion manufacture process to form source area 140 and matrix area 130, as shown in fig. 4m, in the step of carrying out thermal diffusion manufacture process, the Impurity Diffusion in the first type doped region and form doped region 156, the impurity in Second-Type doped region then spreads and forms doped region 155 on.Namely lower doped region 156 forms PN junction 102 with upper doped region 155 in groove 151.
Please refer to Fig. 5 and coordinate with reference to Fig. 6 A to Fig. 6 G.Fig. 5 is the flow chart of the trench power metal-oxide semiconductor field-effect transistor manufacture method of another embodiment of the present invention.Fig. 6 A to Fig. 6 G is the partial cutaway schematic of each step in the manufacture method of the trench power metal-oxide semiconductor field-effect transistor of another embodiment of the present invention.The corresponding S500 to S502 of step in Fig. 6 A, and similar to Fig. 4 A, therefore repeat no more.In addition, the present embodiment represents with identical label with similar elements in previous embodiment.
Then carry out step S503, after Figure 1A forms the first doped region 130 ', form multiple trench gate structure in epitaxial layer 110, each trench gate structure to comprise on one doped region 155 and once doped region 156 to form a PN junction 102.In S503, detailed fabrication process flow please refer to Fig. 6 B to Fig. 6 F.
In fig. 6b, multiple groove 151 is formed in epitaxial layer 110.Then, please refer to Fig. 6 C, form multiple groove 151 in epitaxial layer 110 after, insulating barrier 180 is formed at the surface of epitaxial layer 110, and the side wall surface of groove 151 and bottom.In the present embodiment, be sequentially form the first insulating barrier 180a, the second insulating barrier 180b and the 3rd insulating barrier 180c.That is, the second insulating barrier 180b is located between the first insulating barrier 180a and the 3rd insulating barrier 180c.In one embodiment, the first insulating barrier 180a and the 3rd insulating barrier 180c is all silicon oxide layer, and the second insulating barrier 180b is nitride layer.The mode forming the first insulating barrier 180a, the second insulating barrier 180b and the 3rd insulating barrier 180c can select physical vaporous deposition or chemical vapour deposition technique.
Then, as shown in Fig. 6 D to Fig. 6 F, with at interior doping chemical vapour deposition (CVD) manufacture process (in-situ doping CVD process), grid is formed in groove 151.Specifically, in figure 6d, the first polysilicon structure 156 ' is formed on the 3rd insulating barrier 180c at interior doping chemical vapour deposition (CVD) manufacture process code-pattern, and insert in groove 151.Then, eat-back (etch back) and remove the first covered on the surface polysilicon structure 156 ' of the 3rd insulating barrier 180c, and be positioned at the first polysilicon structure 156 ' of groove 151 first half, and only leave the first polysilicon structure 156 ' being positioned at groove 151 Lower Half.Therefore, be positioned at that the first polysilicon structure 156 ' of groove 151 Lower Half is follow-up will form the lower doped region 156 of Figure 1A and Fig. 2 A.In addition, the top of the first polysilicon structure 156 ' close to the boundary line of the first doped region 130 ' with drift region 120, namely close to the lower edge of the first doped region 130 '.
Please refer to Fig. 6 E, with the first polysilicon structure 156 ' as cover power, remove the second insulating barrier 180b and the 3rd insulating barrier 180c partially.Specifically, be positioned at the first top, doped region 130 ', and be positioned at the second insulating barrier 180b of groove 151 first half side wall surface and the 3rd insulating barrier 180c and can be removed.The insulating barrier 180 being only positioned at groove 151 Lower Half can by complete reservation.It is worth mentioning that, the insulating barrier 180 of groove 151 Lower Half is the functional similarity with the lower insulating barrier 153 in Figure 1A, but structure is different, the first insulating barrier 180a then with for the function of the upper insulating barrier 152 in Fig. 2 A identical, and structural similarity.In the present embodiment, the insulating barrier 180 being positioned at groove 151 Lower Half uses as lower insulating barrier, is gripped with mononitride layer in insulating barrier 180.That is, the second insulating barrier 180b formed in previous step is nitride layer.And in Fig. 6 E, the top of the second insulating barrier 180b and the 3rd insulating barrier 180c is a little less than the lower edge of matrix area 130.
Subsequently, as fig 6 f illustrates, one second polysilicon structure 155 ' is formed in groove 151.Specifically, be first covered on the first insulating barrier 180a to form the second polysilicon structure 155 ' in interior doping chemical vapour deposition (CVD) manufacture process comprehensively, and insert in groove 151.Second polysilicon structure 155 ' has Second-Type doped region.When carrying out nmos pass transistor and manufacturing, the first type doped region is P type, then Second-Type doped region is N-type.Then, eat-back the second polysilicon structure 155 ' of top, removal first doped region 130 ', leave the second polysilicon structure 155 ' being positioned at groove 151.
Then, carry out S504, after carrying out one source pole doping manufacture process to the first doped region 130 ', carry out a thermal diffusion manufacture process to form source area 140 and matrix area 130, wherein source area 140 is positioned at the upper of matrix area 130, as shown in Figure 6 G.In the step of carrying out thermal diffusion manufacture process, the impurity in the first type doped region forms doped region 155 to outdiffusion, and the impurity in Second-Type doped region then forms doped region 156 on to outdiffusion.Further, namely upper doped region 156 forms PN junction with lower doped region 155 in groove 151.Via the explanation of above-described embodiment, the art those of ordinary skill should be known other easily by inference and be implemented CONSTRUCTED SPECIFICATION, does not add repeat at this.
In sum, the trench power metal-oxide semiconductor field-effect transistor of the embodiment of the present invention and its manufacture method, can form PN junction in the gate.Because PN junction can produce junction capacitance (junction capacitance, Cj) under reverse bias, and junction capacitance is and gate/drain electric capacity (Cgd) series connection, can reduce equivalent capacity Ct thus.So, when power-type metal-oxide half field effect transistor works, because equivalent capacity Ct reduces, the switch speed of element can be increased.
Although embodiments of the invention are open as above; but the present invention is not limited to above-described embodiment; those of ordinary skill in the art; not departing from scope disclosed in this invention; when doing a little change and adjustment, what therefore protection scope of the present invention should define with accompanying claims is as the criterion.
Claims (20)
1. a trench power metal-oxide semiconductor field-effect transistor, is characterized in that, comprising:
One base material;
One epitaxial layer, is formed at above this base material; And
Multiple plough groove type transistor unit, is formed in this epitaxial layer, and wherein respectively this plough groove type transistor unit comprises a trench gate structure, and this trench gate structure comprises:
One groove, is formed in this epitaxial layer, and the madial wall of this groove is formed with an insulating barrier; And
One grid, is formed in this groove, and wherein this grid to comprise on one doped region and once doped region, to form a PN junction.
2. trench power metal-oxide semiconductor field-effect transistor as claimed in claim 1, it is characterized in that, respectively this plough groove type transistor unit more comprises:
One source pole district, is positioned at the side of this trench gate structure; And
One matrix area, is positioned at the side of this trench gate structure and is formed at below this source area;
Wherein, this PN junction is positioned at or lower than this matrix area lower edge.
3. trench power metal-oxide semiconductor field-effect transistor as claimed in claim 1, it is characterized in that, on this, doped region is positioned at above this lower doped region, to form this PN junction in the centre position of this groove.
4. trench power metal-oxide semiconductor field-effect transistor as claimed in claim 3, it is characterized in that, on this, doped region and source area are N type semiconductor, and this lower doped region is P type semiconductor.
5. trench power metal-oxide semiconductor field-effect transistor as claimed in claim 3, it is characterized in that, wherein on this, doped region and source area are P type semiconductor, and this lower doped region is N type semiconductor.
6. trench power metal-oxide semiconductor field-effect transistor as claimed in claim 1, it is characterized in that, on this, doped region is positioned at above this lower doped region, and on this, width of doped region is greater than the width of this lower doped region.
7. trench power metal-oxide semiconductor field-effect transistor as claimed in claim 1, it is characterized in that, wherein this insulating barrier to comprise on one insulating barrier and once insulating barrier, on this, insulating barrier is positioned at above this lower insulating barrier, wherein the thickness of this lower insulating barrier is greater than the thickness of insulating barrier on this, and the top of this lower insulating barrier is lower than a matrix area lower edge of this plough groove type transistor unit.
8. trench power metal-oxide semiconductor field-effect transistor as claimed in claim 1, it is characterized in that, wherein this insulating barrier to comprise on one insulating barrier and once insulating barrier, on this, insulating barrier is in order to isolate doped region and this epitaxial layer on this, this lower insulating barrier is in order to isolate this lower doped region and this epitaxial layer, wherein be gripped with mononitride layer in this lower insulating barrier, and the top of this lower insulating barrier is lower than the lower edge of a matrix area of this plough groove type transistor unit.
9. trench power metal-oxide semiconductor field-effect transistor as claimed in claim 1, it is characterized in that, wherein respectively this plough groove type transistor unit more comprises a drift region, and this trench gate structure is extended in this drift region by the surface of this epitaxial layer.
10. a manufacture method for trench power metal-oxide semiconductor field-effect transistor, is characterized in that, comprising:
One base material is provided;
Form an epitaxial layer above this base material;
One body dopant manufacture process is carried out to form one first doped region to epitaxial layer;
Form multiple trench gate structure in this epitaxial layer and this first doped region, respectively this trench gate structure to comprise on one doped region with once doped region to form a PN junction; And
Carry out one source pole doping manufacture process to form one source pole district and a matrix area to this first doped region, wherein this source area is positioned at above this matrix area.
The manufacture method of 11. trench power metal-oxide semiconductor field-effect transistor as claimed in claim 10, it is characterized in that, this PN junction is lower than the lower edge of this matrix area.
The manufacture method of 12. trench power metal-oxide semiconductor field-effect transistor as claimed in claim 10, it is characterized in that, the step wherein forming respectively this trench gate structure comprises:
Form a groove in this epitaxial layer;
Form an insulating barrier in the madial wall of this groove; And
Form a grid in this groove, wherein this grid comprises doped region and this lower doped region on this, and on this, doped region is positioned at above this lower doped region to form this PN junction in this groove.
The manufacture method of 13. trench power metal-oxide semiconductor field-effect transistor as claimed in claim 12, it is characterized in that, the step forming this insulating barrier more comprises:
Formed insulating barrier in this channel bottom, to isolate this lower doped region and this epitaxial layer; And
In formation one, insulating barrier is above this lower insulating barrier, and to isolate doped region and this epitaxial layer on this, wherein the thickness of this lower insulating barrier is greater than the thickness of insulating barrier on this, and the top of this lower insulating barrier is lower than the lower edge of this matrix area.
The manufacture method of 14. trench power metal-oxide semiconductor field-effect transistor as claimed in claim 13, it is characterized in that, the step wherein forming this lower insulating barrier more comprises:
Form mononitride layer in this lower insulating barrier, make this lower insulating barrier this nitride layer sandwiched.
The manufacture method of 15. trench power metal-oxide semiconductor field-effect transistor as claimed in claim 12, is characterized in that, the step wherein forming this grid comprises and is used in interior doping chemical vapour deposition (CVD) manufacture process and forms doped region and this lower doped region on this respectively.
The manufacture method of 16. trench power metal-oxide semiconductor field-effect transistor as claimed in claim 10, is characterized in that, this source area and on this doped region be N type semiconductor, this lower doped region is P type semiconductor.
The manufacture method of 17. trench power metal-oxide semiconductor field-effect transistor as claimed in claim 10, is characterized in that, this source area and on this doped region be P type semiconductor, this lower doped region is N type semiconductor.
The manufacture method of 18. trench power metal-oxide semiconductor field-effect transistor as claimed in claim 10, is characterized in that, multiple described trench gate structure extends downward below this matrix area from this epitaxial layer surface.
The manufacture method of 19. 1 kinds of trench power metal-oxide semiconductor field-effect transistor, is characterized in that, comprising:
One base material is provided;
Form an epitaxial layer above this base material;
One body dopant manufacture process is carried out to form one first doped region to this epitaxial layer;
Form multiple groove in this epitaxial layer;
Formed one first type doped region and a Second-Type doped region in these grooves described one of them, wherein this first type doped region has irrigation canals and ditches, and this Second-Type doped region is positioned within these irrigation canals and ditches;
One source pole doping manufacture process is carried out to this first doped region; And
Carry out a thermal diffusion manufacture process to form one source pole district and a matrix area, wherein this first type doped region forms doped region through this thermal diffusion manufacture process, this Second-Type doped region through this thermal diffusion manufacture process to outdiffusion to form doped region on, wherein on this, doped region and this lower doped region form a PN junction.
The manufacture method of 20. trench power metal-oxide semiconductor field-effect transistor as claimed in claim 19, is characterized in that, formed multiple groove in this epitaxial layer after, more comprise:
Form that insulating barrier is in this channel bottom, to isolate this lower doped region and this epitaxial layer, wherein this lower insulating barrier is a laminated construction, and at least comprises mononitride layer; And
In formation one, insulating barrier is to isolate doped region and this epitaxial layer on this above this lower insulating barrier, and wherein the thickness of this lower insulating barrier is greater than the thickness of insulating barrier on this, and the top of this lower insulating barrier is lower than the lower edge of this matrix area.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410105142.4A CN104934471B (en) | 2014-03-20 | 2014-03-20 | Trench power metal-oxide semiconductor field-effect transistor and its manufacturing method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410105142.4A CN104934471B (en) | 2014-03-20 | 2014-03-20 | Trench power metal-oxide semiconductor field-effect transistor and its manufacturing method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN104934471A true CN104934471A (en) | 2015-09-23 |
| CN104934471B CN104934471B (en) | 2019-02-15 |
Family
ID=54121555
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410105142.4A Active CN104934471B (en) | 2014-03-20 | 2014-03-20 | Trench power metal-oxide semiconductor field-effect transistor and its manufacturing method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN104934471B (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107808827A (en) * | 2016-09-09 | 2018-03-16 | 帅群微电子股份有限公司 | Groove type power semiconductor component and its manufacture method |
| US11049950B2 (en) | 2016-09-09 | 2021-06-29 | Super Group Semiconductor Co., Ltd. | Trench power seminconductor device and manufacturing method thereof |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040232407A1 (en) * | 1999-12-20 | 2004-11-25 | Fairchild Semiconductor Corporation | Power MOS device with improved gate charge performance |
| CN101145576A (en) * | 2006-09-12 | 2008-03-19 | 东部高科股份有限公司 | Trench type MOS transistor and method for manufacturing the same |
| CN101785091A (en) * | 2007-08-21 | 2010-07-21 | 飞兆半导体公司 | Method and structure for shielded gate trench FET |
| CN101807546A (en) * | 2009-02-13 | 2010-08-18 | 尼克森微电子股份有限公司 | Trench type metal-oxide semiconductor device and manufacture method thereof |
| US20110204439A1 (en) * | 2010-02-24 | 2011-08-25 | Kabushiki Kaisha Toshiba | Semiconductor device |
| US20120313164A1 (en) * | 2010-02-16 | 2012-12-13 | Toyota Jidosha Kabushiki Kaisha | Semiconductor devices |
| CN203746863U (en) * | 2014-03-20 | 2014-07-30 | 帅群微电子股份有限公司 | Trench type power metal oxide semi-field-effect transistor |
-
2014
- 2014-03-20 CN CN201410105142.4A patent/CN104934471B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040232407A1 (en) * | 1999-12-20 | 2004-11-25 | Fairchild Semiconductor Corporation | Power MOS device with improved gate charge performance |
| CN101145576A (en) * | 2006-09-12 | 2008-03-19 | 东部高科股份有限公司 | Trench type MOS transistor and method for manufacturing the same |
| CN101785091A (en) * | 2007-08-21 | 2010-07-21 | 飞兆半导体公司 | Method and structure for shielded gate trench FET |
| CN101807546A (en) * | 2009-02-13 | 2010-08-18 | 尼克森微电子股份有限公司 | Trench type metal-oxide semiconductor device and manufacture method thereof |
| US20120313164A1 (en) * | 2010-02-16 | 2012-12-13 | Toyota Jidosha Kabushiki Kaisha | Semiconductor devices |
| US20110204439A1 (en) * | 2010-02-24 | 2011-08-25 | Kabushiki Kaisha Toshiba | Semiconductor device |
| CN203746863U (en) * | 2014-03-20 | 2014-07-30 | 帅群微电子股份有限公司 | Trench type power metal oxide semi-field-effect transistor |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107808827A (en) * | 2016-09-09 | 2018-03-16 | 帅群微电子股份有限公司 | Groove type power semiconductor component and its manufacture method |
| CN107808827B (en) * | 2016-09-09 | 2020-07-14 | 帅群微电子股份有限公司 | Trench type power semiconductor element and manufacturing method thereof |
| US11049950B2 (en) | 2016-09-09 | 2021-06-29 | Super Group Semiconductor Co., Ltd. | Trench power seminconductor device and manufacturing method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| CN104934471B (en) | 2019-02-15 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN105870022B (en) | The manufacturing method of shield grid groove MOSFET | |
| CN106298941B (en) | Shield grid groove power device and its manufacturing method | |
| CN103426765B (en) | The forming method of semiconductor device, the forming method of fin field effect pipe | |
| TWI570917B (en) | Trench power mosfet and manufacturing method thereof | |
| CN104332502B (en) | A kind of complementary tunneling field-effect transistor and preparation method thereof | |
| CN102623495B (en) | Tunneling field effect transistor with multi-doping pocket structure and manufacturing method for tunneling field effect transistor | |
| CN105513971A (en) | Manufacturing method of trench gate power device with shield gate | |
| CN107644913A (en) | One kind has high K charge compensations longitudinal double diffusion metal oxide elemental semiconductor field-effect transistor | |
| CN104425593A (en) | Tunneling field effect transistor and forming method thereof | |
| CN104009078A (en) | Junction-free transistor and manufacturing method thereof | |
| CN105355548A (en) | Manufacturing method for trench gate MOSFET with shield gate | |
| CN104979213A (en) | Process of forming an electronic device having a termination region including an insulating region | |
| CN104409334A (en) | Method for preparing super junction device | |
| CN203746863U (en) | Trench type power metal oxide semi-field-effect transistor | |
| CN104934471A (en) | Trench type power metal-oxide-semiconductor field effect transistor and manufacturing method thereof | |
| CN104992943B (en) | The process for making of SONOS memories | |
| CN104425606B (en) | Tunneling field-effect transistor and forming method thereof | |
| TWM480763U (en) | Trench power MOSFET | |
| CN104900703A (en) | Trench MOSFET terminal structure, trench MOSFET device and manufacture method thereof | |
| CN102339851B (en) | Power semiconductor with polysilicon structure at bottom of trench and method for manufacturing same | |
| CN105244277A (en) | Junction-free field effect transistor and formation method thereof | |
| CN105810732B (en) | Trench power metal-oxide semiconductor field-effect transistor and its production method | |
| CN106409888A (en) | Groove type power transistor structure and manufacturing method thereof | |
| CN106653610A (en) | Improved groove superbarrier rectifier device and manufacturing method thereof | |
| CN106601811A (en) | Trench type power transistor |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |