CN104978455A - Design method for improving power supply reliability - Google Patents
Design method for improving power supply reliability Download PDFInfo
- Publication number
- CN104978455A CN104978455A CN201510352846.6A CN201510352846A CN104978455A CN 104978455 A CN104978455 A CN 104978455A CN 201510352846 A CN201510352846 A CN 201510352846A CN 104978455 A CN104978455 A CN 104978455A
- Authority
- CN
- China
- Prior art keywords
- power
- simulation
- layout
- design
- board
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E40/00—Technologies for an efficient electrical power generation, transmission or distribution
- Y02E40/70—Smart grids as climate change mitigation technology in the energy generation sector
Abstract
The invention particularly relates to a design method for improving power supply reliability. According to the design method for improving power supply reliability, in a Power design process, a Power simulation and comparison link is introduced, and a layout board simulation result of a public board or a developed and verified board of a chip manufacturer serves as a judgment standard; and then, a to-be-developed differentiated Server product is subjected to Power simulation comparison and optimization until the simulation value of a new product is superior to a judgment standard value. According to the design method for improving power supply reliability, in the Power design process, the Power simulation and comparison link is introduced, the simulation result of the to-be-developed differentiated Server product is compared with the layout board simulation result of the existing public board or developed and verified board, and a relatively good optimization scheme is selected according to the simulation result for optimizing the Power design, so that the reliability of the Power design is improved and the board re-knocking probability is reduced.
Description
Technical field
The present invention relates to Power technical field of circuit design, particularly a kind of method for designing improving power supply reliability.Specifically by increasing the link of a step simulation comparison in Power design cycle, and then promote the stability of power-supply system.
Background technology
Due to the project that Server product development is a kind of more complicated, the scattered of any link may cause the probability again re-packed.And again re-pack, not only costly, and be fabricated onto later stage testing authentication from PCB, the time about at least spending February.Therefore, in the development and Design stage, must pay close attention to each link, thus reduce the probability again re-packed as far as possible.
But for Power deviser, in the stage of designing and developing, chip manufacturer does not provide relevant design aids.Thus, the exploitation of power unit at least will experience the testing authentication that re-packs of 2 ~ 3 times.This mode is exactly rely on traditional development and Design to the checking that re-packs, for optimal design is accumulated experience.This mode not only efficiency is lower, and causes the waste of cost and the growth in cycle.
For evading above-mentioned testing efficiency, lower, the problem that testing cost is high and test period is long, the present invention proposes a kind of method for designing improving power supply reliability.Based on current present situation, in Power design cycle, import Power simulation comparison link, this mode can contrast Optimal improvements scheme, and selects good prioritization scheme, promotes the reliability of Power design, reduces the probability again re-packed.
Summary of the invention
The present invention, in order to make up the defect of prior art, provides a kind of cost low, the method for designing of the raising power supply reliability of the integrality that efficiency is high.
The present invention is achieved through the following technical solutions:
Improve a method for designing for power supply reliability, it is characterized in that: in Power design cycle, import Power simulation comparison link, using the public plate of chip manufacturer or developed witness plate the simulation result of layout board as criterion; Then, Power simulation comparison and optimization are carried out to the differentiation Server product that will develop, until the simulation value of new product is better than criterion value.
The present invention improves the method for designing of power supply reliability, comprises the following steps:
(1) the public plate layout board provided with chip manufacturer or developed and the board document of similar Power power demands that passes through of testing authentication for reference design plate, Power simulation analysis is carried out to the layout board of one of its above-mentioned two kinds, using its Power simulation result as with reference to decision content;
(2) to the differentiation Server product P ower functional requirement that will develop, requiring under lamination number at present, carrying out Power first edition layout and design, and utilize Power simulation software to carry out simulation analysis, to obtain first edition Layout simulation value;
(3) contrast with reference to decision content with the emulation obtained in first edition layout simulation value and step (1), if first edition Layout simulation value is better than with reference to decision content, represent that this first edition layout Power designs risk lower, testing authentication of can drawing a design; If reference decision content is better than first edition Layout simulation value, then optimize layout Power design, be better than with reference to decision content until optimize layout design simulation results, to guarantee that Power designs risk minimization of drawing a design.
Described Power emulation adopts Cadence PowerDC simulation software.
In described step (3), the improvement optimization for layout Power relates to the lamination number of plies, and Power layer distributes, Power copper thickness, layout Power plane sizes, the quantity of VIA via hole and putting position, the complex optimum assessment of the aspects such as the putting position of Power chip.
The invention has the beneficial effects as follows: the method for designing of this raising power supply reliability, in Power design cycle, import Power simulation comparison link, the simulation result of the differentiation Server product that will develop and existing public plate or the layout board that developed witness plate compares, and select good prioritization scheme to optimize Power design according to simulation result, improve the reliability of Power design, reduce the probability again re-packed.
Accompanying drawing explanation
Accompanying drawing 1 improves the method for designing schematic flow sheet of power supply reliability for the present invention;
Accompanying drawing 2 is for develop witness plate card laminated information schematic diagram;
Board Power simulation result schematic diagram developed by accompanying drawing 3;
Accompanying drawing 4 is the first laminated information schematic diagram of board newly developed;
Accompanying drawing 5 is board newly developed first Power simulation result schematic diagram;
Accompanying drawing 6 is board Optimal improvements laminated information schematic diagram newly developed;
Accompanying drawing 7 is board Optimal improvements Power simulation result schematic diagram newly developed.
Embodiment
Below in conjunction with accompanying drawing, the present invention is described in detail.
The method for designing of this raising power supply reliability, in Power design cycle, imports Power simulation comparison link, using the public plate of chip manufacturer or developed witness plate the simulation result of layout board as criterion; Then, Power simulation comparison and optimization are carried out to the new product that will develop, until the simulation value of new product is better than criterion value.
The present invention improves the method for designing of power supply reliability, comprises the following steps:
(1) the public plate layout board provided with chip manufacturer or developed and the board document of similar Power power demands that passes through of testing authentication for reference design plate, Power simulation analysis is carried out to the layout board of one of its above-mentioned two kinds, using its Power simulation result as with reference to decision content;
(2) to the differentiation Server product P ower functional requirement that will develop, requiring under lamination number at present, carrying out Power first edition layout and design, and utilize Power simulation software to carry out simulation analysis, to obtain first edition Layout simulation value;
(3) contrast with reference to decision content with the emulation obtained in first edition layout simulation value and step (1), if first edition Layout simulation value is better than with reference to decision content, represent that this first edition layout Power designs risk lower, testing authentication of can drawing a design; If reference decision content is better than first edition Layout simulation value, then optimize layout Power design, be better than with reference to decision content until optimize layout design simulation results, to guarantee that Power designs risk minimization of drawing a design.
Described Power emulation adopts Cadence PowerDC simulation software.
In described step (3), the improvement optimization for layout Power relates to the lamination number of plies, and Power layer distributes, Power copper thickness, layout Power plane sizes, the quantity of VIA via hole and putting position, the complex optimum assessment of the aspects such as the putting position of Power chip.
Now design and develop with certain Server products C PU Power below and improve Optimal Example demonstration and illustrate:
1), develop witness plate card laminated information and Power simulation result respectively as shown in accompanying drawing 2 and accompanying drawing 3, board first edition laminated information newly developed and Power simulation result are respectively as shown in figures 4 and 5.Simulation result shows, and board first edition design result newly developed is 1.69V, and exploitation checking board simulation result is 1.717V, and its result will lower than reference value, and thus this plate Power design exists certain risk.
2), by finding as follows to two board lamination comparative analyses:
To verifying exploitation board: VCCIN is totally 5 Layer, copper is thick is 7oz; GND is totally 3 Layer, and copper is thick is: 4oz;
To new board first edition design: VCCIN is totally 5 Layer, and copper is thick is 6oz; GND is totally 4 Layer, and copper is thick is 4oz;
Conclusion: the new total thickness of slab of board is greater than develops board, and thus power supply VIA via hole is longer, and backflow impedance is large.
Find that board Power plane newly developed is not enough by above-mentioned steps analysis, its VIA via hole is comparatively large, causing backflow impedance comparatively large, having influence on its board Power designing quality lower than developing checking board.
Thus, for the problems referred to above and under considering the unalterable situation of the total thickness of slab of new board, stress to carry out improvement optimization for the distribution of Power plane, as shown in accompanying drawing 6 and accompanying drawing 7, the Power simulation result after its improvement is 1.737V, is better than reference value.Actual measurement of simultaneously carrying out drawing a design is followed the tracks of, and it is 1.799V that checking board result has been developed in actual measurement, and surveying new board optimization, to improve result be 1.809V, and the reliability demonstrating Power design is further effectively improved.
Claims (4)
1. improve a method for designing for power supply reliability, it is characterized in that: in Power design cycle, import Power simulation comparison link, using the public plate of chip manufacturer or developed witness plate the simulation result of layout board as criterion; Then, Power simulation comparison and optimization are carried out to the differentiation Server product that will develop, until the simulation value of new product is better than criterion value.
2. the method for designing of raising power supply reliability according to claim 1, is characterized in that comprising the following steps:
(1) the public plate layout board provided with chip manufacturer or developed and the board document of similar Power power demands that passes through of testing authentication for reference design plate, Power simulation analysis is carried out to the layout board of one of its above-mentioned two kinds, using its Power simulation result as with reference to decision content;
(2) to the differentiation Server product P ower functional requirement that will develop, requiring under lamination number at present, carrying out Power first edition layout and design, and utilize Power simulation software to carry out simulation analysis, to obtain first edition Layout simulation value;
(3) contrast with reference to decision content with the emulation obtained in first edition layout simulation value and step (1), if first edition Layout simulation value is better than with reference to decision content, represent that this first edition layout Power designs risk lower, testing authentication of can drawing a design; If reference decision content is better than first edition Layout simulation value, then optimize layout Power design, be better than with reference to decision content until optimize layout design simulation results, to guarantee that Power designs risk minimization of drawing a design.
3. the method for designing of the raising power supply reliability according to claim 1,2, is characterized in that: described Power emulation adopts Cadence PowerDC simulation software.
4. the method for designing of raising power supply reliability according to claim 2, it is characterized in that: in described step (3), improvement optimization for layout Power relates to the lamination number of plies, Power layer distributes, Power copper thickness, layout Power plane sizes, the quantity of VIA via hole and putting position, the complex optimum assessment of the aspects such as the putting position of Power chip.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510352846.6A CN104978455A (en) | 2015-06-24 | 2015-06-24 | Design method for improving power supply reliability |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510352846.6A CN104978455A (en) | 2015-06-24 | 2015-06-24 | Design method for improving power supply reliability |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN104978455A true CN104978455A (en) | 2015-10-14 |
Family
ID=54274958
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201510352846.6A Pending CN104978455A (en) | 2015-06-24 | 2015-06-24 | Design method for improving power supply reliability |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN104978455A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106919757A (en) * | 2017-03-02 | 2017-07-04 | 济南浪潮高新科技投资发展有限公司 | A kind of method of the more piece point source emulation based on Cadence |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5539652A (en) * | 1995-02-07 | 1996-07-23 | Hewlett-Packard Company | Method for manufacturing test simulation in electronic circuit design |
| CN101604351A (en) * | 2008-06-13 | 2009-12-16 | 电力集成公司 | The method and apparatus that is used for the design of power supply |
| CN102799718A (en) * | 2012-06-29 | 2012-11-28 | 浪潮电子信息产业股份有限公司 | Differentiated simulation design method |
-
2015
- 2015-06-24 CN CN201510352846.6A patent/CN104978455A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5539652A (en) * | 1995-02-07 | 1996-07-23 | Hewlett-Packard Company | Method for manufacturing test simulation in electronic circuit design |
| CN101604351A (en) * | 2008-06-13 | 2009-12-16 | 电力集成公司 | The method and apparatus that is used for the design of power supply |
| CN102799718A (en) * | 2012-06-29 | 2012-11-28 | 浪潮电子信息产业股份有限公司 | Differentiated simulation design method |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106919757A (en) * | 2017-03-02 | 2017-07-04 | 济南浪潮高新科技投资发展有限公司 | A kind of method of the more piece point source emulation based on Cadence |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US20130174110A1 (en) | Circuit assembly yield prediction with respect to form factor | |
| US8769470B2 (en) | Timing closure in chip design | |
| CN102339338B (en) | Time sequence repairing method | |
| US20150064813A1 (en) | Microprocessor image correction and method for the detection of potential defects | |
| CN101782931B (en) | Processing method and system of constraint areas of circuit board wiring | |
| CN107908884B (en) | Interactive ECO method for improving time sequence by adjusting clock tree branches | |
| CN107092757B (en) | Method for checking through hole pressure dividing line in PCB design | |
| CN104573261B (en) | A kind of super large-scale integration VLSI integrated approach | |
| CN104978455A (en) | Design method for improving power supply reliability | |
| CN102662962B (en) | Dynamic display method based on webpage elements | |
| CN103440197B (en) | A kind of method automatically generating difference test report based on contrast test | |
| CN202167721U (en) | Antenna Connector Fixing Device | |
| CN103942326A (en) | Information providing method and device and search result providing method and device | |
| US20120026902A1 (en) | Computing device and crosstalk information detection method | |
| CN117455895A (en) | Preparation device and preparation method for realizing wire clamp | |
| CN203012720U (en) | Circuit after restoration of multi-terminal retention time violation paths | |
| US8959470B2 (en) | Integrated circuit with areas having uniform voltage drop and method therefor | |
| CN102339341A (en) | Method for automatically controlling extraction precision of parasitic parameters during physical layout simulation | |
| CN106919407A (en) | The method of the embedded product information synchronized update of computer | |
| US20130304413A1 (en) | Computing device and method for testing electromagnetic compatiblity of printed circuit board | |
| US11215659B2 (en) | Method for faster testing of manufactured PCB, apparatus, system, and storage medium used in method | |
| CN100446638C (en) | Method and system for creating B side and T side detailed list of veneer | |
| CN102546334A (en) | Data resource uniqueness combining method based on enterprise service bus | |
| CN106294926A (en) | A kind of line class problem inspection method of printed circuit board | |
| CN102236660A (en) | Printed circuit board maintenance data analysis method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20151014 |
|
| RJ01 | Rejection of invention patent application after publication |