CN105185752A - Semiconductor device and fabrication method thereof - Google Patents

Semiconductor device and fabrication method thereof Download PDF

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Publication number
CN105185752A
CN105185752A CN201510549992.8A CN201510549992A CN105185752A CN 105185752 A CN105185752 A CN 105185752A CN 201510549992 A CN201510549992 A CN 201510549992A CN 105185752 A CN105185752 A CN 105185752A
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Prior art keywords
ditch
matrix pad
semiconductor chip
chip
semiconductor device
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CN201510549992.8A
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Chinese (zh)
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CN105185752B (en
Inventor
藤泽敦
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Renesas Electronics Corp
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Renesas Electronics Corp
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Priority to CN201510549992.8A priority Critical patent/CN105185752B/en
Publication of CN105185752A publication Critical patent/CN105185752A/en
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    • H01L23/49503—Lead-frames or other flat leads characterised by the die pad
    • H01L23/49513—Lead-frames or other flat leads characterised by the die pad having bonding material between chip and die pad
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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Die Bonding (AREA)

Abstract

Groove parts (grooves) are respectively formed at four corners of a tetragonal chip carrying region of a semiconductor device provided with a planar shape smaller than the appearance size of a die bonding pad, each groove part is formed along a direction which crosses the diagonal line of the corners provided with the grooves and the two ends of each groove part extend to the outer side of the chip carrying region. A semiconductor chip is carried onto the chip carrying region by a die bonding material, and therefore, the stripping of the die bonding material can be suppressed in the density flow process for installing the semiconductor device on a substrate; and moreover, the stripping development also can be suppressed if the stripping occurs.

Description

Semiconductor device and manufacture method thereof
The application is application number is 201080066405.5, the applying date be May 12 in 2010 day, be called the divisional application of the application for a patent for invention of " semiconductor device and manufacture method thereof ".
Technical field
The present invention relates to semiconductor device and manufacturing technology thereof, particularly relate to the effective technology of semiconductor-chip-mounting to the semiconductor device in the overall dimension chip carrying portion larger than semiconductor chip.
Background technology
The semiconductor device exposing the chip carrying portion being equipped with semiconductor chip from seal is described in Fig. 2 of Japanese Unexamined Patent Publication 2009-71154 publication (patent documentation 1).In addition, in patent documentation 1, the overall dimension in chip carrying portion is larger than the overall dimension of semiconductor chip.
In addition, describe in Fig. 8 (a) of Japanese Unexamined Patent Publication 2007-134394 publication (patent documentation 2) semiconductor-chip-mounting to the semiconductor device defined at upper surface (surface) in the chip carrying portion of ditch.
< patent documentation 1> Japanese Unexamined Patent Publication 2009-71154 publication
One No. 394 publication described in < patent documentation 2> Japanese Unexamined Patent Publication 2007-134
Summary of the invention
(inventing the problem that will solve)
Along with the high speed (or multifunction) of electronic equipment, there is the tendency of increase by the caloric value of the semiconductor device carried.So, the present inventor analyzes as shown in Fig. 2 of above-mentioned patent documentation 1, expose the chip carrying portion (matrix pad (diepad, die pad), contact pin (tab)) being equipped with semiconductor chip from seal structure.If such structure, then owing to the lower surface in chip carrying portion (back side) can be connected with mounting substrates, so can thermal diffusivity be improved with cover the structure in chip carrying portion with seal compared with.In addition, by the Fig. 2 as above-mentioned patent documentation 1, make the overall dimension in chip carrying portion larger than the overall dimension of semiconductor chip, thermal diffusivity can be improved further.
But iff the overall dimension increasing chip carrying portion, then the semiconductor chip that first surface is fixed in chip carrying portion is easily peeled off.Its reason is because the base material (lead frame) forming chip carrying portion is made up of the material different from the material forming semiconductor chip.That is, be because difference appears in their coefficient of linear expansion.Therefore, if apply heat to such semiconductor device, then the expansion/contraction amount of base material is different with the expansion/contraction amount of semiconductor chip, in the die molding material (adhesives) in order to semiconductor chip being fixed to use in chip carrying portion, produce stress.
In addition, when the respective flat shape in used semiconductor chip and chip carrying portion is all quadrangle, especially easily there is the problem of this stripping in the bight (bight of semiconductor chip) in chip carrying portion.Its reason is because the respective stress from the part away from central portion and bight place is maximum.And in the bight in chip carrying portion, if there is the stripping of the die molding material that stress causes, then the central portion peeled off to chip carrying portion develops, and result, die molding material is peeled off on a large scale, becomes the reason of reliability decrease.
And, shown in the Fig. 2 as above-mentioned patent documentation 1, from a part (lower surface) of seal exposed chip equipped section, be difficult between chip carrying portion and seal seal completely.Therefore, with cover the structure in chip carrying portion with seal compared with, moisture easily invades semiconductor device inside.
As described above, overall dimension in chip carrying portion is larger than the overall dimension of semiconductor chip, and from the structure of a part (lower surface) for seal exposed chip equipped section, if the time is long, just become the reason that semiconductor device reliability declines.
So, even if enter the structure of the stripping that also can suppress die molding material as such as moisture, the present inventor's upper surface (surface) analyzed such as in chip carrying portion forms the ditch as shown in Fig. 8 (a) of above-mentioned patent documentation 2.
But, find that the shown such ditch of Fig. 8 (a) of the like above-mentioned patent documentation 2 of use-case fully can not reduce the stress at the bight place in chip carrying portion.Also find, when occurring at bight place to peel off, stripping can develop via the central portion of the region not forming ditch to chip carrying portion, and result, die molding material can be peeled off on a large scale.
The present invention just in view of the above problems and propose, its object is to the technology that the reliability decrease that can suppress semiconductor device is provided.
In addition, another object of the present invention is to the technology that the thermal diffusivity that can improve semiconductor device is provided.
Above-mentioned and other object of the present invention and novel feature, can clearly be seen that from the description of this specification and accompanying drawing.
(be used for the means of dealing with problems)
If be briefly described the summary of the representative solution in invention disclosed in the application, then as described below.
That is, according to the semiconductor device as a mode of the present invention, the flat shape of carrying the chip carrying district of the matrix pad of semiconductor chip is the quadrangle less than the overall dimension of matrix pad.In addition, on said chip pickup zone, form the first ditch in the first bight of said chip pickup zone; Second bight opposite with above-mentioned first bight at the central portion across said chip pickup zone forms the second ditch; The 3rd ditch is formed in the third corner between above-mentioned first bight and above-mentioned second bight; Four bight opposite with above-mentioned third corner at the above-mentioned central portion across said chip pickup zone forms the 4th ditch.In addition, by die molding material above-mentioned semiconductor-chip-mounting to said chip pickup zone.
In addition, above-mentioned first ditch and above-mentioned second ditch, on plan view, formed along with the first direction that above-mentioned first bight being connected said chip pickup zone and first diagonal in above-mentioned second bight intersect respectively.In addition, above-mentioned 3rd ditch and above-mentioned 4th ditch, on plan view, respectively along and the second diagonal of said chip pickup zone of intersecting of above-mentioned first diagonal second direction of intersecting formed.And above-mentioned first ditch, above-mentioned second ditch, above-mentioned 3rd ditch and above-mentioned 4th ditch, on plan view, formed from the region overlapping with above-mentioned semiconductor chip to the nonoverlapping region of above-mentioned semiconductor chip.
(effect of invention)
If be briefly described the effect obtained respectively by the representative solution in invention disclosed in the application, then as described below.
That is, the reliability decrease of semiconductor device can be suppressed.
Accompanying drawing explanation
Fig. 1 is the vertical view of the semiconductor device as one embodiment of the present invention.
Fig. 2 is the upward view of the semiconductor device shown in Fig. 1.
Fig. 3 is the profile of the A-A line along Fig. 1.
Fig. 4 is the amplification profile that the assembling structure having installed the semiconductor device shown in Fig. 3 on mounting substrates is shown.
Fig. 5 be illustrate eliminate the sealing resin shown in Fig. 1 state under the plane graph of internal structure of semiconductor device.
Fig. 6 is the profile of the B-B line along Fig. 5.
Fig. 7 is the amplification profile amplifying the matrix pad peripheral portion shown in Fig. 5 that illustrates.
Fig. 8 is the amplification profile of the C-C line along Fig. 7.
Fig. 9 is the plane graph that the lead frame prepared with lead frame preparatory process is shown.
Figure 10 is the amplification view in the D portion of Fig. 9.
Figure 11 illustrates the amplification view being configured with the state of bonding slurry on the matrix pad shown in Figure 10.
Figure 12 is the amplification profile of the E-E line along Figure 11.
Figure 13 is the amplification profile of the state illustrated to district of the chip carrying portion pressing semiconductor chip shown in Figure 12.
Figure 14 illustrates to carry semiconductor chip in the chip carrying district shown in Figure 11, makes the amplification view of bonding slurry state that drawout comes in whole chip carrying district.
Figure 15 is the amplification profile of the F-F line along Figure 14.
Figure 16 is the plane graph that the state semiconductor chip shown in Figure 14 and multiple lead-in wire (lead) have been electrically connected by silk thread (wire) is shown.
Figure 17 is the amplification profile of the G-G line along Figure 16.
Figure 18 illustrates to clamp with shaping dies the amplification profile that the lead frame shown in Figure 17 defines the state of sealing resin.
Figure 19 illustrates the integrally-built plane graph defining the lead frame of sealing resin at each device area.
Figure 20 is the amplification view that the state that the intercell connector of the lead frame shown in Figure 19 (tiebar) has been cut off is shown.
Figure 21 illustrates that the surface at multiple lead-in wires of deriving from sealing resin defines the amplification profile of the state of outside plated film.
Figure 22 illustrates from the frame portion of lead frame to cut off the multiple lead-in wires defining outside plated film, and the amplification view of the state be shaped.
Figure 23 illustrates to cut off multiple hanging lead respectively on multiple device areas of lead frame, makes semiconductor device become the plane graph of the state of monolithic.
Figure 24 is the plane graph of the semiconductor device illustrated as the variation for the semiconductor device shown in Fig. 5.
Figure 25 is the profile of the H-H line along Figure 24.
Figure 26 is the amplification view of the semiconductor device illustrated as the variation for the semiconductor device shown in Fig. 7.
Figure 27 is the profile of the semiconductor device illustrated as the variation for the semiconductor device shown in Fig. 6.
Figure 28 is the amplification view of the first comparative example that the matrix pad shown in Fig. 8 is shown.
Figure 29 is the profile of the J-J line along Figure 28.
Figure 30 is the amplification view of the second comparative example that the matrix pad shown in Fig. 8 is shown.
Figure 31 is the profile of the K-K line along Figure 30.
(description of reference numerals)
1: semiconductor device; 2: die molding material (adhesives); 2a: bonding slurry (adhesives); 3: semiconductor chip; 3a: upper surface (interarea, surface); 3b: lower surface (interarea, the back side); 3c: electrode pad (bonding welding pad); 4: lead-in wire; 4a: inner lead; 4b: outside lead; 4c: outside plated film; 5: silk thread (electroconductive component); 6: sealing resin (seal); 6a: upper surface; 6b: lower surface; 6c: side; 7: hanging lead; 7a: rake; 8: intercell connector (dykes and dams bar); 10: matrix pad (chip carrying portion); 10a: upper surface (chip carrying face); 10b: lower surface; 10c: outside plated film; 10d: chip carrying district; 10e: chip carrying district; 11: bight; 11a: the first bight; 11b: the second bight; 11c: third corner: 11d: the four bight; 12: central portion; 13: ditch portion (ditch); 13a: the first ditch; 13b: the second ditch; 13c: the three ditch: the 13d: the four ditch; 14: ditch portion (ditch); 20: mounting substrates; 22: soldering material (grafting material); 23: terminal; 30: lead frame; 30a: device area; 30b: frame portion; 35: shaping dies; 36: patrix; 36a: die face; 36b: cavity; 37: counterdie; 37a: die face; 37b: cavity; 40: semiconductor device; 41: semiconductor chip; 41a: upper surface (interarea, surface); 41b: lower surface (interarea, the back side); 41c: electrode pad (bonding welding pad); 42: die molding material (adhesives); 45: semiconductor device; 100: semiconductor device; 101: matrix pad; 102: central portion; 102: semiconductor device; 103: matrix pad; 104: ditch portion; 105: non-ditch region
Embodiment
In this application, the description of execution mode, as required, conveniently be divided into multiple parts etc. to be described, but not that except such situation, they are not separate irrelevant except expressing especially, before no matter being described in or rear, the each several part of an example, one is another a part of details or the variation etc. of part or all.In addition, in principle repeat specification is omitted to identical part.In addition, each inscape in execution mode, is not such situation, the situation being defined in this number from principle except expressing especially and is not except such situation obviously viewed from context, neither be required,
Similarly, in the description of execution mode etc., about material, composition etc., " X be made up of A " etc. also, are not such situations except expressing especially and are not except such situation obviously viewed from context, do not get rid of the key element comprised beyond A.Such as, about composition, mean " taking A as the X that main component comprises A " etc.Such as, " silicon parts " etc., being also not limited to is pure silicon, also comprise SiGe (SiGe) alloy, other with silicon be main component multicomponent alloy, comprise the parts of other additive.About gold-plated, Cu layer, nickel plating etc., not except such situation except expressing especially, being not only pure material, also comprising respectively with the parts that gold, Cu, nickel etc. are main component.
And, when mentioning specific numerical value, quantity be also, not such situation, the situation being defined in this number from principle except expressing especially and be not except such situation obviously viewed from context, can be above the numerical value of this special value, also can be the numerical value being less than this special value.
In addition, in each accompanying drawing of execution mode, give same or similar mark or Reference numeral to identical part, omit repeat specification in principle.
In addition, in the accompanying drawings, when complexity or time clear and definite with the difference in space, even section also can omit hacures etc. sometimes.Related to this, when obviously known from explanation etc., even sometimes in the plane blind bore also can omit the outline line of background.And, even if be not section, also can not space to express and add hacures.
(execution mode 1)
In the present embodiment, as an example of semiconductor device, the semiconductor device choosing QFP (QuadFlatPackage) type is described.Fig. 1 is the vertical view of the semiconductor device of present embodiment.Fig. 2 is the upward view of the semiconductor device shown in Fig. 1.Fig. 3 is the profile of the A-A line along Fig. 1.In addition, Fig. 4 is the amplification profile that the assembling structure having installed the semiconductor device shown in Fig. 3 on mounting substrates is shown.In addition, Fig. 5 is the plane graph of the internal structure of the semiconductor device illustrated under the state eliminating the sealing resin shown in Fig. 1.Fig. 6 is the profile of the B-B line along Fig. 5.
< semiconductor device >
First, the formation of the semiconductor device 1 of present embodiment is described with Fig. 1 ~ Fig. 4.As shown in Figure 3, the semiconductor device 1 of present embodiment comprises: matrix pad 10; The semiconductor chip 3 on matrix pad 10 is carried via die molding material 2; Be configured in the multiple lead-in wires 4 around semiconductor chip 3; Multiple silk threads 5 that multiple electrode pad 3c and multiple lead-in wire 4 of semiconductor chip 3 are electrically connected respectively; And the sealing resin 6 of sealing semiconductor chips 3, multiple silk thread 5 and matrix pad 10.
The flat shape of sealing resin (seal) 6 is rectangular shape, in the present embodiment as shown in Figure 1, is quadrangle.In more detail, rounding processing is carried out to each bight, suppress the breach of seal thus.In addition, as shown in Figure 2, sealing resin 6 has upper surface 6a, lower surface (back side, the installed surface) 6b of the side contrary with this upper surface 6a and the side 6c between this upper surface 6a and lower surface 6b.
As shown in Figure 1, multiple lead-in wire 4 exposes from each side 6c (each limit) of sealing resin 6.In more detail, a respective part (outside lead 4b) for the multiple lead-in wires 4 formed along each limit of sealing resin 6 as shown in Figure 3, derive laterally from each side 6c (each limit) of sealing resin 6, and in the outside of sealing resin 6 towards the lower surface 6b lateral bend of sealing resin 6.In other words, derive multiple outside lead 4b from each limit of sealing resin 6, form the gull wing (gullwing) shape respectively.The semiconductor device with such encapsulation shape is called as the semiconductor device of QFP type.Multiple lead-in wire 4, be the external connection terminals (outside terminal) when semiconductor device 1 is installed on the mounting substrates 20 shown in Fig. 4, the grafting material via soldering material 22 grade is electrically connected with the multiple welding zones (terminal) 21 formed at the installed surface of mounting substrates 20.Therefore, shown in Fig. 1 ~ Fig. 3, in order to the connectivity (wettability) of go between when improving installation 4 and soldering material (grafting material) 22 (with reference to Fig. 4), the outside plated film 4c be made up of such as scolding tin is formed on the surface of multiple lead-in wire 4 (in more detail, outside lead 4b).
In addition, as shown in Figure 2, on the lower surface 6b of sealing resin 6, the lower surface 10b of matrix pad 10 (chip carrying portion, contact pin) exposes from sealing resin 6.That is, semiconductor device 1 is the semiconductor device of matrix pad exposed type (contact pin exposed type).In addition, matrix pad 10 is made up of the metal material that thermal conductivity ratio sealing resin 6 is high, is made up of in the present embodiment such as copper (Cu).In more detail, the outside plated film (omitting in figure) be made up of such as nickel (Ni) is formed on the surface of the base material be made up of copper (Cu).Like this, the semiconductor device of matrix pad exposed type, by expose thermal conductivity ratio sealing resin 6 high, the parts (matrix pad 10) that to be made up of etc. the metal material of such as copper (Cu) etc., compared with the semiconductor device do not exposed with matrix pad 10, the thermal diffusivity of encapsulation can be improved.In addition, when semiconductor device 1 is installed to the mounting substrates 20 shown in Fig. 4, if via such as soldering material (grafting material) 24, the terminal 23 of the lower surface 10b of matrix pad 10 and mounting substrates 20 is electrically connected, then the heat produced by semiconductor device 1 can be dispelled the heat to mounting substrates 20 side more expeditiously.In addition, the terminal 23 shown in Fig. 4 and semiconductor chip 3 also can be the terminals of the heat transmission be not electrically connected, but also can be electrically connected with the lower surface 3b of semiconductor chip 3, are used as the terminal such as to semiconductor chip 3 supply power current potential or reference potential.In addition, as shown in Figure 4, when the lower surface 10b of matrix pad 10 is connected with the terminal 23 of mounting substrates 20, in order to improve the lower surface 10b of matrix pad 10 and the connectivity (wettability) with soldering material (grafting material) 24, preferably, as shown in Figure 3, form at the lower surface 10b of matrix pad 10 the outside plated film 10c be made up of such as scolding tin.
The following describes the internal structure of semiconductor device 1.As shown in Figure 5, the flat shape of upper surface (chip carrying face) 10a of matrix pad 10 is quadrangles.And to arrange flat shape on the upper surface of matrix pad 10 be dimetric chip carrying district 10d (with reference to Fig. 3 and Fig. 6).
In addition, in the present embodiment, matrix pad 10 as the parts carrying semiconductor chip 3 is distinguished come with the chip carrying district 10d (with reference to Fig. 3 and Fig. 6) as the region of carrying semiconductor chip 3 arranged on the upper surface 10a of matrix pad 10, is described.Namely, matrix pad 10 be carry the chip carrying parts of semiconductor chip 3 at least partially, as such as shown in Fig. 5, the planar dimension of matrix pad 10 is not necessarily consistent with the planar dimension of upper surface (interarea) 3a (or lower surface (interarea) 3b shown in Fig. 3 and Fig. 6) of semiconductor chip 3.On the other hand, the region overlapping with semiconductor chip 3 on plan view in the upper surface 10a of the chip carrying district 10d finger print sheet pad 10 shown in Fig. 3 and Fig. 6.Therefore, in the semiconductor device 1 of the overall dimension (planar dimension) of matrix pad 10 present embodiment large with the overall dimension (planar dimension) than semiconductor chip 3, the planar dimension of upper surface (interarea, the first interarea) 3a (or lower surface (interarea, the second interarea) 3b) of semiconductor chip 3 is consistent with the planar dimension of chip carrying district 10d.Such as, in the present embodiment, the overall dimension of matrix pad 10 is about 7mm × 7mm.On the other hand, the overall dimension of semiconductor chip 3 and the overall dimension of chip carrying district 10d are about 5mm × 5mm.
In addition, the thickness of semiconductor chip is such as 280 μm, and the thickness of matrix pad 10 is 150 μm, and the thickness (distance between lower surface 3b and upper surface 10a) of die molding material 2 is about 10 μm ~ 20 μm.In addition, in Fig. 3, Fig. 4 and Fig. 6, in order to easily judge the overall structure of semiconductor device, change the length-width ratio (aspectratio) of each parts, Width is shown than above-mentioned numerical value constriction.In addition, about die molding material 2, because thickness is 10 μm ~ about 20 μm, very thin, so illustrate in integrally-built Fig. 3, Fig. 4 and Fig. 6 of semiconductor device 1, the above-mentioned numerical value of Thickness Ratio of record is thick.In addition, about the thickness of die molding material 2, in magnified partial view described later (such as Fig. 8), the thickness suitable with above-mentioned numerical value is shown.Other detailed construction of matrix pad 10 as described later.
The chip carrying district 10d of matrix pad 10 is equipped with semiconductor chip 3.In the present embodiment, semiconductor chip 3 is carried in the central authorities of matrix pad.Make under the state that lower surface 3b is relative with the upper surface of matrix pad 10, via die molding material (adhesives) 2, semiconductor chip 3 is being carried on chip carrying district 10d.That is, utilize the opposite what is called in the face contrary with the upper surface 3a defining multiple electrode pad 3c and face, chip carrying portion is faced up (face-up) mounting means, carry.Adhesives when this die molding material 2 is die molding semiconductor chips 3, in the present embodiment, uses the die molding material 2 such as containing the metallic be made up of silver (Ag) etc. in epoxies thermosetting resin.The thermosetting resin contained in this die molding material 2 has the character of slurry (paste) shape upon hardening, from can reliably imbed this point between chip carrying district 10d and semiconductor chip 3, is preferred.In addition, containing metallic in die molding material 2, from the heat transfer efficiency this point of the heat-transfer path (heat dissipation path) that can improve from the lower surface 3b of semiconductor chip 3 to matrix pad 10, be preferred.In addition, by making containing metallic in die molding material 2, the lower surface 3b of matrix pad 10 with semiconductor chip 3 can be electrically connected, so such as, as modified embodiment of the present embodiment, also the lower surface 3b of semiconductor chip 3 can be used as electrode.
As shown in Figure 5, the flat shape of the semiconductor chip 3 matrix pad 10 carried is quadrangles.In addition, shown in Fig. 3 and Fig. 6, semiconductor chip 3 has upper surface (interarea, surface) 3a, lower surface (interarea, the back side) 3b of the side contrary with upper surface 3a and the side between this upper surface 3a and lower surface 3b.
And shown in Fig. 3 and Fig. 5, form multiple electrode pad (bonding welding pad) 3c at the upper surface 3a of semiconductor chip 3, in the present embodiment, each limit along upper surface 3a forms multiple electrode pad 3c.In addition, although omit in figure, but semiconductor chip 3 interarea (in more detail, the semiconductor element forming region that the upper surface of the base material of semiconductor chip 3 is arranged) form semiconductor element (circuit element), multiple electrode pad 3c is electrically connected via the wiring (omitting in figure) in the wiring layer of inside (in more detail, between upper surface 3a and not shown semiconductor element forming region) being configured at semiconductor chip 3 and this semiconductor element.
Semiconductor chip 3 (in more detail, the base material of semiconductor chip 3) is made up of such as silicon (Si).Therefore, semiconductor chip 3 is different from the coefficient of linear expansion of matrix pad 10.In more detail, the coefficient of linear expansion of the matrix pad 10 that the coefficient of linear expansion of the semiconductor chip 3 formed primarily of silicon (Si) is formed than the metal material primarily of copper (Cu) etc. is low.In addition, formed at upper surface 3a and cover the base material of semiconductor chip 3 and the dielectric film of wiring, be formed at the peristome place in this dielectric film, the respective surface of multiple electrode pad 3c is exposed from dielectric film.
In addition, this electrode pad 3c is made up of metal, in the present embodiment, is made up of such as aluminium (Al).In addition, also on the surface of this electrode pad 3c, as plated film, gold (Au) film can be formed across such as nickel (Ni) film.Thus, because the surface of electrode pad 3c is covered by nickel film, so the corrosion (pollution) of electrode pad 3c can be suppressed.
In addition, as shown in Figure 5, around semiconductor chip 3 (in more detail, matrix pad 10 around) configuration as the multiple lead-in wires 4 be made up of copper (Cu) in the same manner as matrix pad 10.In more detail, the plated film (omitting in figure) be made up of such as nickel (Ni) is formed on the surface of the base material be made up of copper (Cu).And, multiple electrode pads (bonding welding pad) 3c formed at the upper surface 3a of semiconductor chip 3 is electrically connected respectively via multiple silk thread (electroconductive component) 5 and the multiple lead-in wires 4 (another part of lead-in wire, inner lead 4a) being positioned at sealing resin 6 inside.Silk thread 5 is made up of such as gold (Au), and a part (such as an end) for silk thread 5 is engaged on electrode pad 3c, and another part (such as another end) is engaged on the bonding region of inner lead 4a.In addition, although omit in figure, form plated film on the surface (surface of the plated film in more detail, be made up of nickel (Ni)) of the bonding region of inner lead 4a.Plated film is made up of such as silver (Ag) or gold (Au).Formed the plated film be made up of silver (Ag) or gold (Au) by the surface of the bonding region at inner lead 4a, the bond strength with the silk thread 5 be made up of gold (Au) can be improved.
In addition, as shown in Figure 3, in the present embodiment, with level configurations (biased (offset) configure) the matrix pad 10 different from inner lead 4a.In more detail, matrix pad 10 is configured in (below (downset) configures) on the position lower than inner lead 4a.4 be formed as in the encapsulation of gull wing going between as present embodiment, preferably, at the side 6c of sealing resin 6, lead-in wire 4 is derived from upper surface 6a and the position of lower surface 6b centre at the side 6c of sealing resin 6.This be in order to sealing resin 6 firmly fixing internal lead-in wire 4a.On the other hand, in order to expose matrix pad 10 from sealing resin 6, must with the level configurations matrix pad 10 different from inner lead 4a.Therefore, in the present embodiment, matrix pad 10 bias configuration (below configuration).Be connected with matrix pad 10 with multiple hanging leads 7 that matrix pad 10 forms.In the present embodiment, as shown in Figure 5, each bight of matrix pad 10 is electrically connected with hanging lead 7 respectively.That is, four hanging leads 7 are connected altogether.Hanging lead 7 is in the manufacturing process of semiconductor device 1 described later, links with the frame portion of lead frame (forming the base material of matrix pad 10 and multiple lead-in wire 4), supports the support component of matrix pad 10.And, the plurality of hanging lead 7 forms rake 7a respectively.Like this, by forming rake 7a at each hanging lead 7, matrix pad 10 bias configuration (below configuration).
The detailed construction > of < matrix pad
The following describes the detailed construction of the matrix pad 10 shown in Fig. 5 and the effect by adopting this structure to obtain.Fig. 7 is the amplification profile amplifying the matrix pad peripheral portion shown in Fig. 5 that illustrates, Fig. 8 is the amplification profile of the C-C line along Fig. 7.In addition, Figure 28 is the amplification view of the first comparative example that the matrix pad shown in Fig. 8 is shown, Figure 29 is the profile of the J-J line along Figure 28.In addition, Figure 30 is the amplification view of the second comparative example that the matrix pad shown in Fig. 8 is shown, Figure 31 is the profile of the K-K line along Figure 30.In addition, in the figure 7, in order to illustrate the planar configuration of the ditch formed at the upper surface of matrix pad, the state after eliminating the semiconductor chip shown in Fig. 5 and die molding material is shown.
The semiconductor device 100 as the first comparative example for present embodiment shown in Figure 28 and Figure 29 is except the upper surface 10a at matrix pad 101 is not formed except ditch, identical with the structure of the semiconductor device 1 shown in Fig. 7 with Fig. 8.The semiconductor chip 3 of the semiconductor device 100 shown in Figure 28 with Figure 29 is different from the coefficient of linear expansion of matrix pad 101 (in more detail, semiconductor chip 3 is formed primarily of silicon (Si), and matrix pad 101 is formed primarily of copper (Cu)).Therefore, if heat-treated semiconductor device 100 in installation procedure, then stress can be produced in the die molding material 2 in order to semiconductor chip 3 being fixed on use on matrix pad 101.In more detail, at the bonding interface of semiconductor chip 3 and die molding material 2 and die molding material 2 stress (shear stress) with the direction, generation face, bonding interface place of matrix pad 101.And this stress produces on the region that semiconductor chip 3 is overlapping with matrix pad 101, maximum at each bight 11 place namely from central portion position farthest with the chip carrying district 10d (semiconductor chip 3) of dimetric flat shape.
Like this, even if produce stress, if apply energy from outside to semiconductor device 100, the stripping at the bonding interface place that die molding material 2 and semiconductor chip 3 or matrix pad 101 occur also is difficult to.But, analysis according to present inventor judges, semiconductor device 100 after assembling is terminated is installed in density current (reflow) operation (heating installation procedure) on mounting substrates 20 (mounting substrates 20 such as shown in Fig. 4), if heating semiconductor 100, then the die molding material 2 of semiconductor device 100 inside and semiconductor chip 3 or matrix pad 101 can be peeled off.
In density current operation, semiconductor device 100 is heated to the high temperature of such as more than 260 DEG C.If semiconductor device 100 is heated to such high temperature, then semiconductor device 100 inside comprise or invade the moisture of semiconductor device 100 inside from outside and sharply expand (blast).And, if cause moisture sharply to expand, namely the region that then stress is maximum is formed as bight 11 place of the chip carrying district 10d (semiconductor chip 3) of dimetric flat shape, and die molding material 2 can be peeled off with semiconductor chip 3 or matrix pad 101.And the stripping that bight 11 place produces develops to the central portion 12 of chip carrying portion 10d, die molding material 2 can be peeled off on a large scale.If because die molding material 2 and semiconductor chip 3 or matrix pad 101 are peeled off, can gap be produced, so moisture can infiltrate in this gap, become the reason of semiconductor device 100 internal corrosion.That is, the reason of the reliability decrease of semiconductor device 100 is become.In addition, if produce gap, the thermal diffusivity of semiconductor device 100 also can decline.Cause the inside that the moisture peeled off is included in such as sealing resin 6.In addition, semiconductor device 100 and expose the semiconductor device of matrix pad 10 from sealing resin 6 as the semiconductor device 1 shown in Fig. 8, moisture easily invades from outside.
Like this, in order to prevent or suppress to peel off the reliability decrease of the semiconductor device caused because of die molding material 2 or thermal diffusivity declines, present inventor analyzes the structure forming ditch at the chip carrying district 10d of the upper surface 10a of matrix pad 101.
First, analyze as the matrix pad 103 had as the semiconductor device 102 of the second comparative example for present embodiment shown in Figure 30, in chip carrying district 10d, form the structure of multiple ditch portion (ditch) 104.In the matrix pad 103 shown in Figure 30, form ditch portion 104 respectively at four bights 11 place of chip carrying district 10d.Ditch portion 104 is the depressions formed by such as etching and processing, defining the region in ditch portion 104, shown in Figure 31, and the lower thickness of matrix pad 103.In addition, ditch portion 104 is only formed in chip carrying district 10d, is not formed in the outside of chip carrying district 10d.In other words, on the extended line in ditch portion 104, configuration is positioned at chip carrying district 10d and does not form the non-ditch region 105 of ditch.Present inventor thinks, due to the region of the lower thickness at matrix pad 103, thermal expansion amount or the thermal shrinking quantity (hereinafter referred to as amount of distortion) of the coefficient of linear expansion matrix pad 103 larger than semiconductor chip 3 (with reference to Figure 31) can be reduced, so the value of the stress at bight 11 place can be reduced.Also think, by make ditch portion 104 along with in two diagonal of chip carrying district 10d, direction that the diagonal that is connected the bight 11 configuring ditch portion 104 intersects extends, even if if peel off at bight 11 place, also can suppress the development of peeling off.
But, to the semiconductor device 102 shown in Figure 30 evaluate as a result, after finding to implement density current operation, the problem that the bonding interface that can not solve die molding material 2 and semiconductor chip 3 or matrix pad 101 is peeled off.Even if also find the number increasing the ditch portion 104 shown in Figure 30 further, such peeling can be there is too.Consider that its reason is as described below.
Namely, at the stress (shear stress) that the bonding interface place of die molding material 2 and semiconductor chip 3 or matrix pad 101 produces, as described above, from matrix pad 103 central portion 12 more away from larger, be maximum from bight 11 place of central portion chip carrying district 10d farthest.This is because the amount of distortion of matrix pad 103 from central portion more away from larger.At this, when the matrix pad 103 shown in Figure 30, defining the region in ditch portion 104, the amount of distortion of matrix pad 103 reduces, but owing to there is non-ditch region 105 on the extended line in ditch portion 104, so fully can not reduce the amount of distortion of the matrix pad 103 at bight 11 place.Its result, can not reduce the stress in bight 11.
In addition, when occurring at bight 11 place to peel off, by making ditch portion 104 extend along with the direction that the diagonal being connected the bight 11 configuring ditch portion 104 intersects at each bight 11 place, can prevent to a certain extent peeling off and linearly developing to central portion 12 from bight 11.But owing to there is non-ditch region 105, peel off and develop into central portion 12 from non-ditch region 105 is roundabout, result stripping can develop into the bonding interface of broad range.
In addition, die molding material 2 is imbedded in ditch portion 104, but when there is non-ditch region 105 at the two ends in ditch portion 104 as matrix pad 103, be difficult to die molding material 2 reliably to imbed ditch portion 104, easily remaining pore (bubble) in ditch portion 104.This is because on matrix pad 103 during bonding semiconductor chip 3, the path of extruding the air in ditch portion 104 is very narrow.And if moisture (moisture that sealing resin 6 inside such as shown in Figure 31 is contained) is accumulated in the pore that remains in ditch portion 104, then this moisture sharply expands (blast) in density current operation, so easily cause stripping.
Present inventor, based on the above-mentioned analysis result of independent analysis, has found the structure of the matrix pad 10 shown in Fig. 7 and Fig. 8.
The matrix pad 10 of the present embodiment shown in Fig. 7 and Fig. 8, as shown in Figure 7, each bight 11 place being dimetric chip carrying district 10d in flat shape forms ditch portion (ditch) 13.In more detail, the first ditch 13a is formed at the first bight 11a of chip carrying district 10d.In addition, form the second ditch 13b at the second bight 11b, on plan view, the central portion 12 that the second bight 11b intersects across two diagonal of chip carrying district 10d is opposite with the first bight 11a.In addition, the 3rd ditch 13c is formed at third corner 11c, on plan view, third corner 11c is (on the second in more detail, different from first diagonal of connection first bight 11a and the second bight 11b diagonal) between the first bight 11a and the second bight 11b.In addition, form the 4th ditch 13d at the 4th bight 11d, on plan view, the 4th bight 11d is opposite with third corner 11c across the central portion 12 of chip carrying district 10d.
In addition, on plan view, the first ditch 13a and the second ditch 13b are formed along intersecting the first direction of (preferably orthogonal) with first diagonal of the second bight 11b with the first bight 11a being connected chip carrying district 10d respectively.In addition, on plan view, the 3rd ditch 13c and the 4th ditch 13d respectively along and second diagonal of the chip carrying district 10d that the first diagonal intersects intersect the second direction of (preferably orthogonal) and formed.
In addition, on the region in the outside (region nonoverlapping with semiconductor chip 3) from chip carrying district 10d (region overlapping with semiconductor chip 3) to chip carrying district 10d, form the first ditch 13a, the second ditch 13b, the 3rd ditch 13c and the 4th ditch 13d.In more detail, each ditch portion 13 passes through in chip carrying district 10d outside chip carrying district 10d, and extends to the outside of chip carrying district 10d further and formed.In other words, the two ends in each ditch portion 13 extend to the outside of chip carrying district 10d.
Like this, by the outside making the two ends in each ditch portion 13 extend to chip carrying district 10d, can make ditch portion 13 reliably between produce stress chip carrying district 10d in, from central portion 12 to the path in each bight 11.Therefore, can reduce the amount of distortion of the matrix pad 10 at each bight 11 place, result can reduce the value of the stress (shear stress) that each bight 11 place produces.Its result, when such as shown in Figure 4 semiconductor device 1 being arranged on mounting substrates 20, even if be heated to more than 260 DEG C as density current operation, the die molding material 2 at bight 11 place and the stripping of semiconductor chip 3 or matrix pad 101 also can be suppressed.In addition, in the present embodiment, although to compare with the semiconductor device 100 shown in Figure 28 the stress that bight 11 place that can reduce chip carrying district 10d produces with the semiconductor device 102 shown in Figure 30, the position that the chip carrying district 10d internal stress shown in Fig. 7 is the highest remains bight 11.Therefore, if the stripping of the die molding material 2 at bight 11 place can be prevented, the stripping of other position in chip carrying district 10d can just be prevented.
In addition, if when occurring at bight 11 place to peel off, from the angle of prevent or suppress peel off to central portion 12 development be also, by as shown in Figure 7, the two ends in each ditch portion 13 are made to extend to the outside of chip carrying district 10d, can prevent or suppress as the matrix pad 103 shown in above-mentioned Figure 30, peel off and roundaboutly to develop to central portion 12.The roundabout reason developed to central portion 12 of the stripping that bight 11 place occurs is that the stress owing to producing in chip carrying district 10d causes.That is, if peeled off at bight 11 place, then stress focuses on from the unstripped region away from the distance second of central portion 12, peels off and develops to central portion 12 at leisure.But according to the present embodiment, the two ends due to each ditch portion 13 extend to the outside of chip carrying district 10d, so the developing direction of stripping can be made towards the outside of stress d/d chip carrying district 10d, so can be suppressed it.
In addition, from the angle of the development effectively suppressing to peel off, preferably, as shown in Figure 7, each ditch portion 13 is formed along with the direction that the diagonal being connected the bight 11 configuring ditch portion 13 intersects.If form ditch portion 13 at the upper surface 10a of matrix pad 10, then the bearing of trend peeled off along ditch portion 13 develops.Therefore, by making ditch portion 13 be formed along with the direction intersected towards the direction of central portion 12 from bight 11, the developing direction of stripping can be made reliably to escape towards the outside of chip carrying district 10d.Especially, along with connect configure the mutually orthogonal direction of the diagonal in the bight 11 in ditch portion 13 form ditch portion 13 time, Min. can be suppressed to peeling off area.
In addition, as described above, the stripping of die molding material 2, occurs at the bonding interface place with semiconductor chip 3 sometimes, sometimes occurs at the bonding interface place with matrix pad 10.But as present embodiment, when the coefficient of linear expansion of matrix pad 10 is larger than semiconductor chip 3, form ditch portion 13 by the matrix pad 10 larger at the amount of distortion caused because of heat, the stripping at which interface can prevent or suppress.This is because, by the amount of distortion of the amount of distortion that reduces to cause because of the heat matrix pad 10 larger than semiconductor chip 3, the stress occurred with the bonding interface place of die molding material 2 at semiconductor chip 3 can also be reduced.In addition, the relation that the size of stress and the bonding force at bonding interface place occurred by bonding interface in which interface occurs to peel off determines, but such as present embodiment, when semiconductor chip 3 is formed primarily of silicon (Si), matrix pad 10 is formed primarily of copper (Cu), easily peel off at the bonding interface place of matrix pad 10 with die molding material 2.Therefore, it is particularly preferred for forming ditch portion 13 at matrix pad 10.
In addition, by the outside making the two ends in ditch portion 13 extend to chip carrying district 10d, when semiconductor chip 3 is bonded on matrix pad 10, air in ditch portion 13 can be expressed into the broad spatial outside chip carrying district 10d, so can prevent or suppress the generation of pore (remaining).Therefore, can prevent or suppress Water accumulation in pore, so the sharply expansion of the moisture in density current operation when semiconductor device 1 is installed on the mounting substrates 20 shown in Fig. 4 can be suppressed.Therefore, the factor causing and peel off can be reduced.
In addition, from the angle reducing the stress produced at bight 11 place, preferably, on from central portion 12 to the path in bight 11, make the area in the region that the thickness of matrix pad 10 is thin (i.e. the area of plane in ditch portion 13) large as much as possible.But if the area of plane in each ditch portion 13 (ditch width) is too large, then the Stiffness of matrix pad 10, can worry that breakage occurs matrix pad 10 in manufacturing process.
So in the present embodiment, as shown in Figure 7, multiple row ditch portion 13 is formed respectively at each bight 11 place.If illustrated in greater detail, the central portion 12 from the first bight 11a of chip carrying district 10d to chip carrying district 10d forms the first ditch 13a in multiple row.In addition, the central portion 12 from the second bight 11b of chip carrying district 10d to chip carrying district 10d forms the second ditch 13b in multiple row.In addition, the central portion 12 from the third corner 11c of chip carrying district 10d to chip carrying district 10d forms the 3rd ditch 13c in multiple row.In addition, the central portion 12 from the 4th bight 11d of chip carrying district 10d to chip carrying district 10d forms the 4th ditch 13d in multiple row.In the present embodiment, such as, as shown in Figure 7,5 row ditch portions 13 are formed respectively at each bight 11 place.In addition, the ditch width in each ditch portion 13 is such as 100 μm.
Like this, by forming multiple row ditch portion 13 respectively at each bight 11 place, compared with when only forming a row ditch portion 13 respectively, can on from central portion 12 to the path in bight 11, the area (i.e. the area of plane sum in each ditch portion 13) in the region that the thickness of increase matrix pad 10 is thin.In addition, because the ditch width in each ditch portion 13 can set, so can prevent or suppress the breakage of the matrix pad 10 in manufacturing process in the scope of Stiffness that can suppress matrix pad 10.
In addition, as shown in Figure 7, in each bight 11, place forms multiple row ditch portion 13 respectively, is also preferred from the angle of preventing from peeling off development.That is, if peeled off at bight 11 place, peel off and develop into nearest ditch portion 13 of digression portion 11, then maximum at the stress at the boundary line place in the region of having peeled off and unstripped region.And, if sharply expanded as the moisture peeling off priming factors in this condition, then there is the possibility occurring further at boundary line place to peel off.But, even if when there occurs such second time and peeling off, also the development that this second time is peeled off can be rested on the region defining near ditch portion 13 of digression portion 11 second.Like this, by forming multiple row ditch portion 13 respectively at each bight 11 place, though there occurs repeatedly peel off time, also can suppress peel off development.Such as, as present embodiment, when each bight 11 place forms 5 row ditch portion 13 respectively, can substantially reliably prevent stripping from developing into central portion 12.
Like this, according to the present embodiment, by forming multiple row ditch portion 13 respectively at each bight 11 place, can prevent or suppress stripping to develop into central portion 12, so do not form ditch portion 13 on central portion 12.In more detail, the first ditch 13a, the second ditch 13b, the 3rd ditch 13c and the 4th ditch 13d are not formed on the central portion 12 of chip carrying district 10d.As illustrating, from the angle of suppressing the stripping of die molding material 2 and suppressing to peel off development, it was effective for forming ditch portion 13 at chip carrying district 10d.But, if form ditch portion 13, then in ditch portion 13, imbed die molding material 2.Therefore, the configuration amount of die molding material 2 increases, and is difficult to make the configuration amount of the die molding material 2 in chip carrying district 10d even.So, by as present embodiment, central portion 12 does not form ditch portion 13, reduces the total amount of die molding material 2, easily thus in chip carrying district 10d, configure die molding material 2 equably.
In addition, in the present embodiment, in chip carrying district 10d, each ditch portion 13 is configured to not intersect.In more detail, multiple row first ditch 13a, multiple row second ditch 13b, multiple row the 3rd ditch 13c and multiple row the 4th ditch 13d, in chip carrying district 10d, be configured to mutually non-cross respectively.As described above, when forming ditch portion 13, peeling off and developing along ditch portion 13, so be configured to not intersect by each ditch portion 13 in chip carrying district 10d, can prevent stripping from crossing the development of ground, multiple ditch portion 13.In addition, when die molding material 2 is imbedded in ditch portion 13, from the angle suppressing pore to produce, preferably, the path branches of imbedding of die molding material 2 is not become multiple path.In the present embodiment, because ditch portion 13 each in chip carrying district 10d is configured to not intersect, thus die molding material 2 imbed path not branch, from the angle that pore can be suppressed to produce, be also preferred.
In addition, as shown in Figure 7, on the upper surface 10a of the matrix pad 10 of present embodiment, formation ditch portion (ditch around chip carrying district 10d, 5th ditch) 14, this ditch portion 14 has the flat shape of the ring-type on each limit along chip carrying district 10d.Ditch portion 14 forms ring-type (frame-shaped) in the mode of the surrounding surrounding chip carrying district 10d.From the angle of the thermal diffusivity of raising semiconductor device 1, reduce the configuration amount of die molding material 2, the distance shortening the lower surface 3b of the semiconductor chip 3 and upper surface 10a of matrix pad 10 is preferred.In addition, in order to reliably imbed die molding material 2 in each ditch portion 13, the configuration amount of the die molding material 2 in chip carrying district 10d is made to be evenly very important.So, by as present embodiment, around chip carrying district 10d, form the ditch portion 14 of the ring-type of surrounding it, die molding material 2 can be made to expand to around chip carrying district 10d, prevent from the part in ditch portion 13 producing the region not imbedding die molding material 2.In addition, die molding material 2 can be made reliably to expand on whole chip carrying district 10d.This is because ditch portion 14 is used as the dam unit of the diffusion of the die molding material 2 suppressed on the upper surface 10a of matrix pad 10.
In addition, in the present embodiment, the two ends in each ditch portion 13 are connected with ditch portion 14.In other words, the first ditch 13a, the second ditch 13b, the 3rd ditch 13c are connected with ditch portion 14 with the respective two ends of the 4th ditch 13d.Like this, linked by the two ends and ditch portion 14 making each ditch portion 13, as shown in Figure 7, the upper surface 10a of matrix pad 10 can be divided into the region surrounded by each ditch portion 13 and ditch portion 14.Therefore, be confined to due to the development of stripping can be made in the region that surrounded by ditch portion 13 and ditch portion 14, so the development of peeling off can be suppressed more reliably.
As described above, the semiconductor device 1 of present embodiment, the ditch portion 13 outside chip carrying district 10d is extended to, the value of the stress (stress in direction, face: shear stress) that each bight 11 place that can be reduced in chip carrying district 10d produces by formation two ends.In addition, formed along with the direction that the diagonal being connected the bight 11 configuring ditch portion 13 intersects by making each ditch portion 13, even if when die molding material 2 has been peeled off with semiconductor chip 3 or matrix pad 10, also the development of peeling off can be confined in little scope.Especially, as present embodiment, at the lower surface 6b place of sealing resin 6, expose the semiconductor device 1 of lower surface 10b (with reference to Fig. 8) of matrix pad 10 from sealing resin 6, owing to easily invading from outside as the moisture peeling off priming factors, if so use the technology illustrated in the present embodiment of the development that can suppress generation or the stripping of peeling off, then can effectively suppress.
In addition, as shown in Figure 8, ditch portion 13 and ditch portion 14 are formed from the upper surface 10a of matrix pad 10 towards lower surface 10b, but not through lower surface 10b, be formed into (roughly) between the upper surface 10a of matrix pad 10 and lower surface 10b.In other words, the ditch depth that the first ditch 13a, the second ditch 13b, the 3rd ditch 13c (with reference to Fig. 7) and the 4th ditch 13d (with reference to Fig. 7) are respective is more shallow than the thickness of above-mentioned matrix pad.Such as in the present embodiment, for the thickness 150 μm of matrix pad 10, form the ditch portion 13 of ditch depth about 75 μm.Like this, by each ditch portion 13 is formed as not through matrix pad 10, can prevent die molding material 2 in the manufacturing process of semiconductor device 1 from leaking from the lower face side of matrix pad 10.
The manufacture method > of < semiconductor device
Below, the manufacturing process of the semiconductor device 1 in present embodiment is described.The semiconductor device 1 in present embodiment is manufactured by the following assembling flow path that will illustrate.Below, the details of each operation is described with Fig. 9 ~ Figure 23.
1: lead frame preparatory process:
Fig. 9 is the plane graph of the lead frame with the preparation of lead frame preparatory process; Figure 10 is the amplification view in the D portion of Fig. 9.
First, as lead frame preparatory process, prepare lead frame 30 as shown in Figure 9.In the lead frame 30 used in the present embodiment, form multiple device area 30a in the inner side of frame portion (framework) 30b, in the present embodiment, there are four device area 30a.Lead frame is made up of metal, in the present embodiment, is made up of such as copper (Cu).In more detail, as described above, the plated film be made up of such as nickel (Ni) is formed on the surface of the base material be made up of copper (Cu).
Each device area 30a, shown in the magnified partial view of Fig. 9 and Figure 10, the matrix pad 10 that the central portion being formed in device area 30a is formed and the multiple lead-in wires 4 configured around matrix pad 10.In the lead frame 30 prepared by this operation, matrix pad 10 and multiple lead-in wire 4 link with frame portion 30b respectively, form.In more detail, on matrix pad 10, matrix pad 10 and frame portion 30b form, matrix pad 10 with link matrix pad 10 and frame portion 30b multiple (in the present embodiment, article 4) hanging lead 7 connects, and supports matrix pad 10 with hanging lead 7.In addition, on multiple lead-in wire 4, multiple lead-in wire 4 forms with frame portion 30b, and multiple lead-in wire 4 is connected with the intercell connector (dykes and dams bar) 8 of frame portion 30b with the multiple lead-in wire 4 of link, supports multiple lead-in wire 4 with intercell connector 8.In addition, multiple hanging lead 7 has been formed for as described above the rake 7a of matrix pad 10 bias configuration (below configuration).That is, the upper surface 10a of matrix pad 10 is configured in the position lower than the upper surface of multiple lead-in wire 4.In addition, in the present embodiment, multiple hanging lead 7 and flat shape are that each bight 11 of dimetric matrix pad 10 is connected.
In addition, as shown in Figure 10, on the upper surface 10a of matrix pad 10, configuration plane shape is dimetric chip carrying district 10d.In addition, the ditch portion 14 of multiple ditch portion 13 and ring-type illustrated in the detailed construction > of above-mentioned < matrix pad is formed at upper surface 10a.In addition, about the detailed construction in the ditch portion (ditch) 14 of multiple ditch portion (ditch) 13 and ring-type, due to illustrated in the detailed construction > of above-mentioned < matrix pad identical, so omit repeat specification.
The lead frame 30 shown in Fig. 9 and Figure 10 can be formed as such as.
First, prepare the thin plate be made up of copper (Cu), form matrix pad 10, hanging lead 7, lead-in wire 4 and intercell connector 8 by etching and processing or pressurization processing with the predetermined pattern shown in Figure 10.
Then, as shown in Figure 10, the ditch portion 14 (ditch portion formation process) of multiple ditch portion 13 and ring-type is formed at the upper surface 10a of matrix pad 10.Ditch portion 13,14 can pass through such as, the upper surface 10a side of the mask (omitting in figure) and matrix pad 10 defining through hole in the position forming ditch portion 13,14 is abutted, formed by etching, at this, in the present embodiment, because ditch portion 13,14 is formed as not through matrix pad 10, so formed by the so-called half-etching processing terminating etch processes before ditch portion 13,14 arrival matrix pad 10 lower face side formed with etching.In addition, although in the present embodiment, about the ditch depth in ditch portion 13,14 is formed as the about half of the thickness of matrix pad 10 as described above, the ditch depth in ditch portion 13,14 is not limited thereto.In the manufacturing process of semiconductor device 1, formed comparatively dark (such as dark than half) is preferred in the scope that can prevent matrix pad 10 breakage.
Then, from the position (biased operation) of the upper surface 10a of upper surface location bias (in the present embodiment, being below configuration) the matrix pad 10 of lead-in wire 4.In this biased operation, such as, with staking punch (omitting in figure) and mould (omitting in figure), bending machining is carried out to a part for hanging lead 7, form rake 7a.In addition, above-mentioned ditch portion formation process was carried out before biased operation, but in order to easily configure mask (etching mask), in the present embodiment, after ditch portion formation process, carried out biased operation.But, also can carry out biased operation before ditch portion formation process.Now, by carrying out biased operation before formation ditch portion 13,14, the biased damage adding the matrix pad 10 in man-hour can be suppressed.
2, die molding operation:
Figure 11 illustrates the amplification view being configured with the state of bonding slurry on the matrix pad shown in Figure 10; Figure 12 is the amplification profile of the E-E line along Figure 11.In addition, Figure 13 is the amplification profile of the state illustrated to district of the chip carrying portion pressing semiconductor chip shown in Figure 12.In addition, Figure 14 illustrates to carry semiconductor chip in the chip carrying district shown in Figure 11, makes the amplification view of bonding slurry state that drawout comes in whole chip carrying district; Figure 15 is the amplification profile of the F-F line along Figure 14.
Then, as die molding operation, shown in Figure 14 and Figure 15, by die molding material 2, semiconductor chip 3 is carried on the chip carrying district 10d of matrix pad 10.In the present embodiment, shown in Figure 15, carry to make what is called that the lower surface 3b of semiconductor chip 3 (face of the side contrary with the upper surface 3a defining multiple electrode pad 3c (with reference to Figure 14)) state opposite with the upper surface 10a of matrix pad 10 is carried (face-up) mounting means that faces up.
Usually, as semiconductor chip, the adhesives be adhesively fixed on matrix pad is the adhesives of pulp-like (aqueous) and the adhesives of adhesive tape-like (flake).When using the adhesives of pulp-like (there is the state of mobility and (such as high than water) viscosity), by in advance at matrix pad configuration (coating) adhesives (bonding slurry), press with semiconductor chip when carrying semiconductor chip, pressing is sprawled and bonding adhesives.Then, adhesives is hardened, fixing semiconductor chip.On the other hand, when using the adhesives of adhesive tape-like, the adhesive linkage in advance two sides at base material being defined the adhesive tape of adhesive linkage attaches in the mounting surface of semiconductor chip, bonding in the chip carrying district another adhesive linkage being attached to matrix pad.When using the adhesives of this adhesive tape-like also, after bonding, the adhesives of this adhesive tape-like is hardened, fixing semiconductor chip 3.
In the present embodiment, because the chip carrying district 10d at matrix pad 10 forms ditch portion 13, so use in above-mentioned two kinds of adhesivess, easily can to imbed the pulp-like in ditch portion 13 adhesivess and bonding slurry 2a.Because if form gap between ditch portion 13 and adhesives (die molding material 2), then become the reason of Water accumulation in ditch portion 13 as described above.Below, the die molding operation of the present embodiment employing bonding slurry 2a is described.
First, shown in Figure 11 and Figure 12, the chip carrying district 10d of matrix pad 10 configures (coating) bonding slurry 2a.Bonding slurry 2a is made up of the thermosetting resin of such as epoxies.In addition, in the present embodiment, from the angle improving thermal diffusivity, containing the metallic be made up of silver (Ag) etc. in thermosetting resin.
In addition, in the present embodiment, from making bonding slurry 2a spread into angle in whole chip carrying district 10d roughly equably, as shown in Figure 11, bonding slurry 2a is configured on multiple positions of chip carrying district 10d.In fig. 11, respectively bonding slurry 2a is configured on 9 positions between the central portion 12 of chip carrying district 10d, each bight 11 and each bight 11 totally.The collocation method of para-linkage slurry 2a is not particularly limited, but in the present embodiment, use the drop-coating of coating amount and the coating position that can control bonding slurry 2a accurately (never the nozzle of figure is sprayed onto bonding slurry 2a the method on matrix pad 10).
Then, shown in Figure 13, the upper surface 10a towards chip carrying district 10d presses lower surface (interarea, the second interarea) 3b of semiconductor chip 3.Bonding slurry 2a can be imbedded in each of multiple ditch portion 13 thus.And, if further towards the lower surface 3b of the upper surface 10a pressing semiconductor chip 3 of chip carrying district 10d, then shown in Figure 15, bonding slurry 2a is imbedded ditch portion 13, while make bonding slurry 2a spread on whole chip carrying district 10d.Thus, make the lower surface 3b of semiconductor chip 3 be bonded slurry 2a to cover.
At this, in the present embodiment, due to shown in Figure 14, the two ends in ditch portion 13 are made to extend to the outside of chip carrying district 10d, so by being pressed into semiconductor chip 3, the air in ditch portion 13 is expressed into the outside of chip carrying district 10d while imbed bonding slurry 2a.Therefore, in die molding operation, can prevent or suppress the generation of the pore in ditch portion 13 (remaining).That is, owing to can suppress Water accumulation in pore, so the sharply expansion of the moisture in density current operation when semiconductor device 1 is installed on the mounting substrates 20 shown in Fig. 4 can be suppressed.Therefore, the factor causing and peel off can be reduced.
In addition, in the present embodiment, in chip carrying district 10d, each ditch portion 13 is configured to not intersect.In more detail, multiple row first ditch 13a, multiple row second ditch 13b, multiple row the 3rd ditch 13c and multiple row the 4th ditch 13d, in chip carrying district 10d, be configured to mutually non-cross respectively.In other words, bonding slurry 2a imbeds path 2 not branch, and the bonding slurry 2a imbedding ditch portion 13 presses out along ditch portion 13 to the outside of chip carrying district 10d successively.Therefore, in die molding operation, the generation of pore can be suppressed more reliably.
In addition, from the angle improving thermal diffusivity, the distance shortening the lower surface 3b of the semiconductor chip 3 and upper surface 10a of matrix pad 10 is preferred.As present embodiment, time in die molding material 2 (bonding slurry 2a) containing metallic, the die molding material that thermal conduction characteristic compares not containing metal particle is high, even if but under these circumstances, also thermal conduction characteristic can be improved further by the distance shortening the lower surface 3b of the semiconductor chip 3 and upper surface 10a of matrix pad 10.And from the angle of the distance of the shortening lower surface 3b of the semiconductor chip 3 and upper surface 10a of matrix pad 10, the configuration amount reducing the die molding material 2 (bonding slurry 2a) between lower surface 3b and upper surface 10a is preferred.In the present embodiment, the lower surface 3b of semiconductor chip 3 is shorter than the ditch depth in ditch portion 13 with the distance of the upper surface 10a of matrix pad 10.Such as described above, for the ditch depth about 75 μm in ditch portion 13, the distance of the lower surface 3b of semiconductor chip 3 and the upper surface 10a of matrix pad 10 is made to be about 10 μm ~ 20 μm.Like this, by reducing the configuration amount of the die molding material 2 (bonding slurry 2a) between lower surface 3b and upper surface 10a, thermal diffusivity can be improved.
In addition, iff the configuration amount reducing die molding material 2 (bonding slurry 2a), then die molding material 2 (bonding slurry 2a) is sprawled in the part less than chip carrying district 10d sometimes, becomes the reason of poor attachment.That is, the configuration amount of the die molding material 2 (bonding slurry 2a) sometimes in chip carrying district 10d is uneven.
So on the upper surface 10a of the matrix pad 10 of present embodiment, formation ditch portion (ditch, the 5th ditch) 14 around chip carrying district 10d, this ditch portion 14 forms the flat shape of the ring-type on each limit along chip carrying district 10d.Ditch portion 14 forms ring-type (frame-shaped) in the mode of the surrounding surrounding chip carrying district 10d.Thus, die molding material 2 can be made to expand to around chip carrying district 10d, prevent from the part in ditch portion 13 producing the region not imbedding die molding material 2.In addition, die molding material 2 can be made reliably to expand on whole chip carrying district 10d.This is because ditch portion 14 is used as the dam unit of the diffusion of the die molding material 2 suppressed on the upper surface 10a of matrix pad 10.
In addition, when ditch portion 13 and ditch portion 14 are the gaps being formed as through matrix pad 10, if pressed by semiconductor chip 3, then a part of bonding slurry 2a can drain to the lower surface 10b side of matrix pad 10 from gap.Therefore, the amount of bonding slurry 2a is understood not enough and poor attachment occurs sometimes.
So in the present embodiment, shown in Figure 15, ditch portion 13 and the not through lower surface 10b in ditch portion 14, be formed into (centre) between the upper surface 10a of matrix pad 10 and lower surface 10b.In other words, the ditch depth that the first ditch 13a, the second ditch 13b, the 3rd ditch 13c (with reference to Figure 14) and the 4th ditch 13d (with reference to Figure 14) are respective is more shallow than the thickness of above-mentioned matrix pad.Such as in the present embodiment, for the ditch portion 13 of the thickness 150 μm formation ditch depth about 75 μm of matrix pad 10.Like this, by each ditch portion 13 is formed as not through matrix pad 10, can prevent die molding material 2 in die molding operation from leaking from the lower face side of matrix pad 10.Therefore, even if pressed by semiconductor chip 3, bonding slurry 2a also can not drain to the lower surface 10b side of matrix pad 10, can expand on whole chip carrying district 10d.
Then, shown in Figure 14 and Figure 15, make bonding slurry 2a harden and become die molding material 2.In the present embodiment, because bonding slurry 2a comprises thermosetting resin, so carry out heat treated (such as 100 DEG C ~ about 150 DEG C) to lead frame 30, bonding slurry 2a is hardened.
3, thread bonded operation:
Figure 16 is the plane graph that the state semiconductor chip shown in Figure 14 and multiple lead-in wire have been electrically connected by silk thread is shown; Figure 17 is the amplification profile of the G-G line along Figure 16.
Then, as thread bonded operation, shown in Figure 16 and Figure 17, by multiple silk thread (electroconductive component) 5, multiple electrode pad 3c of semiconductor chip 3 and multiple lead-in wire 4 are electrically connected respectively.
In this operation, such as, prepare the heating station (omitting in figure) being formed with recess, in the mode making matrix pad 10 be positioned at recess, the lead frame 30 having carried semiconductor chip 3 is configured in heating station.Then, by silk thread 5, the electrode pad 3c of semiconductor chip 3 and lead-in wire 4 electrical connection are got up.At this, in the present embodiment, utilize by capillary (omitting in figure) supply silk thread 5, and fetch with ultrasonic wave and hot pressing and make articulate so-called ailhead bonding (nailheadbonding) mode of silk thread 5 be connected silk thread 5.
In addition, the temperature used in the present embodiment is such as 170 ~ 230 DEG C.In addition, as described above, form plated film in a part (bonding region) for lead-in wire 4, a part for silk thread 5 is electrically connected by this plated film and lead-in wire 4.
In addition, silk thread 5 is made up of metal, in the present embodiment, is made up of such as gold (Au).Therefore, by forming gold (Au) on the surface of the electrode pad 3c of semiconductor chip 3 as described above, the close adhesion of silk thread 5 and electrode pad 3c can be improved.
In addition, in the present embodiment, utilize after making a part for silk thread be connected with the electrode pad 3c of semiconductor chip 3, the positive bonding pattern of what is called that in making another part of silk thread 5 and going between, the bonding bonding pad (part defining plated film gone between in the upper surface of 4) of 4 is connected connects silk thread.
4, molding process:
Figure 18 illustrates to clamp with shaping dies the amplification profile that the lead frame shown in Figure 17 defines the state of sealing resin.In addition, Figure 19 illustrates the integrally-built plane graph defining the lead frame of sealing resin at each device area.
Then, as molding process, shown in Figure 18, form sealing resin (seal) 6, sealing semiconductor chips 3, multiple silk thread 5 and matrix pad 10.In the present embodiment, form sealing resin 6 in the mode of the lower surface 10b exposing matrix pad 10 from sealing resin 6, the upper surface 10a side of sealing matrix pad 10.
In this operation, first shown in Figure 18, preparation has the shaping dies 35 of patrix (the first mould) 36 and counterdie (the second mould) 37, cavity (recess) 36b that patrix 36 has die face (the first die face) 36a and formed at this die face 36a, cavity (recess) 37b that counterdie 37 has die face (second die face) 37a opposite with the die face 36a of patrix 36 and formed at this die face 37a.Then, be positioned at the cavity 36b of patrix 36 to make semiconductor chip 3 and matrix pad 10 is positioned at the mode of the cavity 37b of counterdie 37, the lead frame 30 implementing thread bonded operation be configured in the inside (between patrix 36 and counterdie 37) of shaping dies 35.At this, in the present embodiment, owing to exposing the lower surface 10b of matrix pad 10 from sealing resin 6, so lower surface 10b abuts with the bottom surface of the cavity 37b of counterdie 37.
Then, lead frame 30 is clamped with patrix 36 and counterdie 37.At this moment, be jammed in a part for multiple lead-in wires 4 of lead frame 30 formation when clamping lead frame 30.Then, a part for lead-in wire 4 (inner lead 4a) is configured in cavity 36b, 37b, and go between 4 another part (outside lead 4b) mould 35 that is formed in the outside of cavity 36b, 37b clamp.
Then, under the state of clamping lead frame 30 with patrix 36 and counterdie 37, sealing resin is supplied, with a part (inner lead 4a) for sealing resin-encapsulated semiconductor chip 3, multiple silk thread 5, multiple lead-in wire 4 and the upper surface 10a of matrix pad 10 in the space being overlapped by the cavity 36b of patrix 36 and the cavity 37b of counterdie 37 and formed.
Then, by making the sealing resin thermmohardening that is supplied to and forming sealing resin 6.At this, the sealing resin in present embodiment is thermosetting epoxylite, containing multiple filler (quartz).In addition, the temperature of the shaping dies 35 in present embodiment is such as about 180 DEG C.
Then, by taking out lead frame 30 after enforcement thermmohardening operation in shaping dies, the lead frame 30 defining sealing resin 6 as shown in Figure 19 at each device area 30a is obtained.
Then, the lead frame 30 taken out from shaping dies 35 is transported in oven (omitting in figure), again to lead frame 30 heat treatment.Its reason is, although in thermmohardening operation in above-mentioned sealing process, the resin be fed in cavity 36b, 37b can harden, and resin is the state of not hardening completely.This is because, sealing process to be carried out as early as possible to the next lead frame 30 be next transported in shaping dies 35.Therefore, in the present embodiment, the hardening process of sealing resin is divided into twice, by using the heat treatment of oven, sealing resin 6 is hardened completely.In addition, in oven, the lead frame 30 defining sealing resin 6 is configured in the hot atmosphere of such as 150 DEG C, heats 3 hours.
5, intercell connector excision operation:
Figure 20 is the amplification view that the state that the intercell connector of the lead frame shown in Figure 19 has been cut off is shown.
Then, as the intercell connector excision operation shown in Fig. 7, shown in Figure 20, the intercell connector 8 between the adjacent legs 4 connected in multiple lead-in wire 4 is cut off.In addition, in the present embodiment, a part for removing intercell connector 8 is cut off with not shown cutting knife (mould, drift).
6, deburring operation:
Then, as deburring operation, remove the resin burr (omitting in figure) formed in above-mentioned molding process.As the removing method of resin burr, with such as, removing can be irradiated with laser, sprays removing or their combination etc. with high-pressure cleaning liquid.
7, plating operation:
Figure 21 illustrates that the surface at multiple lead-in wires of deriving from sealing resin defines the amplification profile of the state of outside plated film.
Then, as plating operation, form outside plated film 4c on the surface of multiple lead-in wires 4 (outside lead 4b) of deriving from sealing resin 6.In the present embodiment, the lower surface 10b of matrix pad 10 exposes from the lower surface 6b of sealing resin 6, also forms outside plated film 10c in the lower surface 10b side of matrix pad 10.
In this operation, using as being configured in the coating bath (figure omits) putting into plating solution (figure omits) by the lead frame 30 of plating machining object, form outside plated film 4c, 10c in the lump with such as electroplating method.
Outside plated film 4c, 10c of present embodiment are made up of the so-called Pb-free solder being substantially free of Pb (lead), are such as: pure Sn (tin), Sn (tin)-Bi (bismuth) or Sn (tin)-Ag (silver)-Cu (copper) etc.At this, Pb-free solder refers to that Pb (lead) content is the scolding tin of below 0.1wt%, and this content is determined based on RoHs (noxious substance forbidding) regulation.
Therefore, the plating solution used in this plating operation contains such as Sn 2+, Bi 3+deng slaine.In addition, in the present embodiment, the example as Pb-free solder uses the plating of Sn-Bi metal of alloying, but also Bi can be replaced to the metal of Cu, Ag etc.
8, marking procedures:
Then, as marking procedures, form the mark of the identification sign identifying semiconductor device 1 etc.In the present embodiment, such as marker recognition mark is carried out by irradiating laser on the upper surface 6a to the sealing resin 6 shown in Figure 21.
9, lead forming operation:
Figure 22 illustrates from the frame portion of lead frame to cut off the multiple lead-in wires defining outside plated film, the amplification view of the state be shaped.
Then, as lead forming operation, after the linking portion of multiple lead-in wires 4 that the frame portion 30b with lead frame 30 is linked cuts off, bending machining is carried out to lead-in wire 4 and is shaped.
In this operation, first, cut off in linking part office and link with frame portion 30b respectively and integrated multiple lead-in wires 4, as parts (lead-in wire cuts off operation) independently.Cut off in operation at this lead-in wire, by lower face side configuration mould (support component omits in figure) respectively at lead frame 30, at the upper surface side configuration drift (cutting knife of lead frame 30, omit in figure), carry out pressure processing and cut off lead-in wire 4.The end of the lead-in wire 4 cut off by pressure processing in this wise, as shown in Figure 3, has the section of general planar, exposes from outside plated film 4c at the base material of section place lead-in wire 4.The individual components separated respectively is become by the multiple lead-in wire 4 of this operation.
Then, bending machining and be shaped (bending machining operation) are carried out to cut-off multiple lead-in wires 4.In the present embodiment, such as shown in Figure 3, outside lead 4b is formed as gull wing.
Then, as shown in Figure 3, cut off the tip of lead-in wire 4 (outside lead 4b), make the contraction in length (wire tip cut-out operation) of multiple lead-in wire 4.This lead-in wire front end cuts off operation and cuts off in the same manner as operation with lead-in wire, by the lower face side configuration mould (support component respectively at lead frame 30, omit in figure), at the upper surface side configuration drift (cutting knife of lead frame 30, omit in figure), carry out pressure processing and cut off lead-in wire 4.
10, singualtion operation:
Figure 23 illustrates to cut off multiple hanging lead respectively on multiple device areas of lead frame, makes semiconductor device become the plane graph of the state of monolithic.
Then, as singualtion operation, shown in Figure 22, cut off the hanging lead 7 linked with frame portion 30b, shown in Figure 23, form monolithic for each device area 30a, obtain multiple semiconductor device 1.Cut off the method for hanging lead 7, cut off in the same manner as operation with above-mentioned lead-in wire, by the lower face side configuration mould (support component respectively at lead frame 30, omit in figure), at the upper surface side configuration drift (cutting knife of lead frame 30, omit in figure), carry out pressure processing and cut off hanging lead 7.
The semiconductor device 1 shown in Fig. 1 ~ Fig. 3 is completed by above each operation.
Then, carry out the necessary inspection such as visual examination, electrical test and test, dispatch from the factory or be installed on the mounting substrates 20 shown in Fig. 4.
(execution mode 2)
In above-mentioned execution mode 1, the example as semiconductor device describes the semiconductor device carrying a semiconductor chip on matrix pad.In the present embodiment, execution mode when using in the semiconductor device that a matrix pad carries the multiple semiconductor chips varied in size is described.In addition, in the present embodiment, be described centered by part different from the embodiment described above, repeat specification is omitted.
Figure 24 is the plane graph of the semiconductor device illustrated as the present embodiment for the semiconductor device variation shown in Fig. 5; Figure 25 is the profile of the H-H line along Figure 24.In addition, Figure 26 is the amplification view of the semiconductor device illustrated as the present embodiment for the semiconductor device variation shown in Fig. 7.
The semiconductor device 40 of the present embodiment shown in Figure 24 ~ Figure 26 is with the difference of the semiconductor device 1 illustrated in above-mentioned execution mode 1, and matrix pad 10 carries multiple semiconductor chip.That is, in semiconductor device 40, matrix pad 10 carries semiconductor chip 3 and semiconductor chip 41 (such as two semiconductor chips 41).
The semiconductor device of SIP (system in encapsulating, SysteminPackage) type is had as carrying the example of multiple semiconductor chip in this wise in an encapsulation.Such as in the present embodiment, semiconductor chip 41 is formed the memory circuit that will store the data of speech or image etc.That is, semiconductor chip 41 is storage chips.On the other hand, the control circuit etc. of the memory circuit that formation control is formed at semiconductor chip 41 on semiconductor chip 3.And, become the semiconductor device of the so-called SIP type of construction system by semiconductor chip 3,41 is electrically connected.The semiconductor device of SIP type such as has the following advantages: as compared to when becoming the encapsulation independently of the control semiconductor device that defines control circuit and the storage semiconductor device defining memory circuit, can reduce erection space.
Semiconductor chip 41 has lower surface (back side) 41b (with reference to Figure 25) of upper surface 41a (interarea, surface) and the side contrary with upper surface 41a, and the flat shape of upper surface 41a is the quadrangle less than the upper surface 3a of semiconductor chip 3.Such as, in the present embodiment, upper surface 41a and lower surface 41b, shown in Figure 24, forms the rectangle that the upper surface 3a of area ratio semiconductor chip 3 is little.
In addition, form multiple electrode pad (bonding welding pad) 41c at the upper surface 41a of semiconductor chip 41, in the present embodiment, the long limit along upper surface 41a forms multiple electrode pad 41c.
In addition, although omit in figure, but semiconductor chip 41 interarea (in more detail, the semiconductor element forming region that the upper surface of the base material of semiconductor chip 41 is arranged) form semiconductor element (circuit element, memory circuit element in the present embodiment), multiple electrode pad 41c is electrically connected via the wiring (omitting in figure) in the wiring layer of inside (in more detail, between upper surface 41a and not shown semiconductor element forming region) being configured at semiconductor chip 41 and this semiconductor element.
In addition, the chip carrying district 10e of matrix pad 10 carries semiconductor chip 41 via die molding material 42.In more detail, shown in Figure 25, utilize the what is called making lower surface 41b carry out carrying to face up mounting means oppositely with the upper surface 10a of matrix pad 10, carry.In addition, in the same manner as carrying the die molding material 2 of semiconductor chip 3, die molding material 42 is adhesivess when carrying out die molding to semiconductor chip 41, in the present embodiment, the die molding material such as containing the metallic be made up of silver (Ag) etc. in epoxies thermosetting resin is used.
In addition, shown in Figure 24, around matrix pad 10, configuration is as the multiple lead-in wires 4 be made up of copper (Cu) in the same manner as matrix pad 10.And the part of the multiple electrode pad 41c formed at the upper surface 41a of semiconductor chip 41 is electrically connected respectively via multiple silk thread (electroconductive component) 5 and the multiple lead-in wires 4 (inner lead 4a) being positioned at sealing resin 6 inside.In addition, a part of multiple electrode pad 3c of semiconductor chip 3 is electrically connected respectively via multiple silk thread (electroconductive component) 5 and the multiple lead-in wires 4 (inner lead 4a) being positioned at sealing resin 6 inside.In addition, another part of multiple electrode pad 3c of semiconductor chip 3 is electrically connected via silk thread (electroconductive component) 5 another part with multiple electrode pad 41c of semiconductor chip 41.That is, semiconductor chip 3 and semiconductor chip 41 are electrically connected by multiple silk thread 5, are electrically connected respectively by silk thread 5 and the multiple lead-in wires 4 as the external connection terminals of semiconductor device 40.
At this, shown in Figure 26, on the chip carrying district 10d of the lift-launch semiconductor chip 3 of semiconductor device 40, in the same manner as the semiconductor device 1 illustrated in above-mentioned execution mode 1, form ditch portion 13.In addition, because the detailed construction in ditch portion 13, optimal way are identical with above-mentioned execution mode 1 with the effect of each mode, so omit.On the other hand, the chip carrying district 10e carrying semiconductor chip 41 does not form ditch portion (ditch).
This is because the overall dimension of semiconductor chip 41 is less than the overall dimension of semiconductor chip 3.As illustrating in above-mentioned execution mode, according to the analysis of present inventor, the value of the stress produced by bight 11 place reducing chip carrying district 10d, can prevent or suppress the stripping of die molding material 2.And if the overall dimension of the overall dimension of semiconductor chip 3 and chip carrying district 10d reduces, then the value of the stress of bight 11 place generation decreases.Such as, in the present embodiment, the overall dimension (in other words, the size of chip carrying district 10e) of semiconductor chip 41 is below half of overall dimension (in other words, the size of chip carrying district 10d) of semiconductor chip 3.Therefore, because the size of chip carrying district 10e is enough little, so the more difficult stripping of die molding material 42 compared with die molding material 2.That is, in the present embodiment, when matrix pad 10 carries the different multiple semiconductor chips of overall dimension 3,41, ditch portion 13 is formed at the chip carrying district 10d of the lift-launch semiconductor chip 3 especially easily peeled off.On the other hand, because the chip carrying district 10e overall dimension of carrying semiconductor chip 41 is very little, be difficult to peel off, so do not form ditch portion 13.
In addition, around chip carrying district 10d, form the ditch portion 14 illustrated in the above-described embodiment.And ditch portion 14 is not formed around the chip carrying district 10e adjacent with chip carrying district 10d.This is because, because the planar dimension of chip carrying district 10e is less than chip carrying district 10d, even if so do not form ditch portion 14 around chip carrying district 10e, also can easily die molding material 42 be spread on whole chip carrying district 10e (central portion and each bight) roughly equably.
In addition, as modified embodiment of the present embodiment, also contemplate the execution mode carrying the roughly equal multiple semiconductor chips of planar dimension.Now, preferably, carry each semiconductor chip chip carrying district each on form ditch portion 13.In addition, now, preferably, formation ditch portion 14 around each chip carrying district.
And, when carrying multiple semiconductor chip that planar dimension varies in size, if the overall dimension of matrix pad is large, then also can be as described above, not only form ditch portion 13,14 in the chip carrying district of carrying the large semiconductor chip of overall dimension, and also form ditch portion 13,14 in the chip carrying district of carrying the little semiconductor chip of overall dimension.Thus, the overall dimension of the matrix pad 10 used is larger than the matrix pad (with reference to Figure 26) only forming ditch portion 13,14 in the chip carrying district of carrying the large semiconductor chip of overall dimension, but the stripping of the semiconductor chip that can overall dimension be suppressed more reliably little, can improve the reliability of semiconductor device.
Above, specifically illustrate based on execution mode the invention that the present inventor completes, but the invention is not restricted to above-mentioned execution mode, can all changes be carried out in the scope not departing from main inventive concept of the present invention.
Such as, in above-mentioned execution mode 1 and 2, describe the lower surface 6b place at sealing resin 6, the semiconductor device of the matrix pad exposed type (contact pin exposed type) that the lower surface 10b of matrix pad 10 exposes from sealing resin 6.But, also go for as the semiconductor device 45 shown in the Figure 27 as the variation for Fig. 6, the lower surface 10b of matrix pad 10 does not expose from sealing resin 6, and is sealed in the semiconductor device of the matrix pad internally-arranged type (contact pin internally-arranged type) in sealing resin 6.
Semiconductor device 45 shown in Figure 27, compared with the semiconductor device 1 shown in Fig. 6, because matrix pad 10 is sealed by sealing resin 6, so the amount of the moisture invaded from outside is few.But, as illustrating in above-mentioned execution mode 1, such as, sometimes moisture is remained in sealing resin 6 inside etc., or moisture invades from the interface of lead-in wire 4 and sealing resin 6 sometimes, if die molding material 2 is peeled off, then moisture can be accumulated in the gap because peeling off formation, becomes the reason of matrix pad 10 corrosion etc.Therefore, by forming the ditch portion 13 illustrated in above-mentioned execution mode 1 at chip carrying district 10d, the development of peeling off or suppressing to peel off can be suppressed, can suppress thus because matrix pad 10 corrodes the decline of the reliability caused.
In addition, such as, in above-mentioned execution mode 1 and 2, as an example of the encapsulation of semiconductor device, the semiconductor device choosing QFP type is illustrated, but the form of encapsulation is not limited to QFP.Also go for, such as, from the lower surface of sealing resin with the QFN (QuadFlatNon-leadedPackage) of multiple outside terminal is exposed in side, the flat shape of sealing resin is rectangle and expose SOP (SmallOutlinePackage), the SON (SmallOutlineNon-leadedPackage) etc. of outside terminal from its long side.
Application in industry
The present invention can be widely used in the manufacturing industry manufacturing semiconductor device.

Claims (8)

1. a semiconductor device, comprising:
Matrix pad, the first ditch comprising first surface, the second surface relative with described first surface and formed on the first surface;
Hanging lead, is connected with described matrix pad; And
Semiconductor chip, is arranged on the described first surface of described matrix pad via die molding material,
Wherein on plan view, the shape of described matrix pad is made up of roughly quadrangle,
Wherein said hanging lead is connected with the bight of described matrix pad,
Wherein on plan view, the shape of described semiconductor chip is made up of roughly quadrangle,
Wherein said semiconductor chip is arranged on the described first surface of described matrix pad, and the limit of described semiconductor chip on plan view is configured along the limit of described matrix pad respectively,
Wherein said first ditch comprises the end between described first surface and described second surface,
Wherein on plan view, described hanging lead extends along first direction substantially,
Wherein on plan view, described first ditch extends along the second direction of intersecting with described first direction, and
Wherein said first ditch comprises Part I and Part II, and this Part I is not covered by described semiconductor chip on plan view, and this Part II covers on plan view between described Part I and by described semiconductor chip.
2. semiconductor device as claimed in claim 1, wherein,
Described matrix pad and described semiconductor chip are sealed by seal, and
Wherein, the described second surface of described matrix pad exposes from described seal.
3. semiconductor device as claimed in claim 1, wherein,
Second ditch is formed on the described first surface of described matrix pad,
Wherein said second ditch comprises the end between described first surface and described second surface,
Wherein on plan view described second ditch along the every of described semiconductor chip while extend,
Wherein on plan view, described second ditch is not overlapping with described semiconductor chip.
4. semiconductor device as claimed in claim 3, wherein,
Described matrix pad and described semiconductor chip are sealed by seal, and
The described second surface of wherein said matrix pad exposes from described seal.
5. a semiconductor device, comprising:
Matrix pad, comprises first surface, the second surface relative with described first surface and forms multiple first ditches on the first surface;
Multiple hanging lead, is connected with described matrix pad; And
Semiconductor chip, is arranged on the described first surface of described matrix pad via die molding material,
Wherein on plan view, the shape of described matrix pad is made up of roughly quadrangle,
Wherein said multiple hanging lead is connected with the bight of described matrix pad respectively,
Wherein on plan view, the shape of described semiconductor chip is made up of roughly quadrangle,
Wherein said semiconductor chip is arranged on the described first surface of described matrix pad, and the limit of described semiconductor chip on plan view is configured along the limit of described matrix pad respectively,
Each of wherein said multiple first ditch comprises the end between described first surface and described second surface,
Wherein on plan view, described multiple hanging lead extends along first direction respectively substantially,
Wherein on plan view, described multiple first ditch extends along the second direction of intersecting with described first direction respectively, and
Each of wherein said multiple first ditch comprises Part I and Part II, this Part I is not covered by described semiconductor chip on plan view, and this Part II covers on plan view between described Part I and by described semiconductor chip.
6. semiconductor device as claimed in claim 5, wherein,
Described matrix pad and described semiconductor chip are sealed by seal, and
The described second surface of wherein said matrix pad exposes from described seal.
7. semiconductor device as claimed in claim 5, wherein,
Second ditch is formed on the described first surface of described matrix pad,
Wherein said second ditch comprises the end between described first surface and described second surface,
Wherein on plan view described second ditch along the every of described semiconductor chip while extend,
Wherein on plan view, described second ditch is not overlapping with described semiconductor chip.
8. semiconductor device as claimed in claim 7, wherein,
Described matrix pad and described semiconductor chip are sealed by seal, and
The described second surface of wherein said matrix pad exposes from described seal.
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US9006871B2 (en) 2015-04-14
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US9324644B2 (en) 2016-04-26
WO2011142006A1 (en) 2011-11-17
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US20130020692A1 (en) 2013-01-24
HK1213690A1 (en) 2016-07-08

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