CN105244321A - Semiconductor device, manufacturing method of semiconductor device and electronic device - Google Patents
Semiconductor device, manufacturing method of semiconductor device and electronic device Download PDFInfo
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- CN105244321A CN105244321A CN201410269703.4A CN201410269703A CN105244321A CN 105244321 A CN105244321 A CN 105244321A CN 201410269703 A CN201410269703 A CN 201410269703A CN 105244321 A CN105244321 A CN 105244321A
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- control gate
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- polar curve
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Abstract
The invention provides a semiconductor device, a manufacturing method of the semiconductor device and an electronic device. The method comprises the steps of providing a semiconductor substrate; forming a plurality of active regions extending along a first direction on the semiconductor substrate; forming a control gate line which spans a plurality of active regions and extends along a second direction above the active regions, wherein the second direction is perpendicular to the first direction; and forming a cutting mask defined with a pattern of a cutting region, carrying out etching on the control gate line in the cutting region, and at least completely removing the control gate line above the active regions. According to the manufacturing method provided by the invention, control for polycrystalline silicon residue after cutting of the control gate line is realized more easily through changing the layout direction of the control gate line and the layout of the cutting mask, occurrence of a problem of word line bridging is avoided, and thus the performance and the yield of the deice are improved.
Description
Technical field
The present invention relates to semiconductor fabrication process, in particular to a kind of semiconductor device and manufacture method thereof and electronic installation.
Background technology
Semiconductor memory system is more and more at large in various electronic installation.For example, nonvolatile semiconductor memory can be used in cellular phone, digital camera, personal digital assistant, mobile computing device, non-moving calculation element and other device.Along with the fast development of electronic industry especially consumer electronics, the development of semiconductor storage more and more becomes one of mark post of electronics technology development.From initial with DRAM (i.e. dynamic random access memory) account for leading till now with FlashMemory (i.e. nonvolatile flash memory memory body) for maximum camp; The development speed of semiconductor memory constantly challenges Moore's Law, and in the twinkling of an eye NANDFlash has come 3X nanometer era, more or even striden into 2X nanometer era.
But in the manufacturing process of 3xnmNAND memory; often can produce a kind of special failure mode---word line bridging (WordLineBridge); word line bridging reason is caused to be; utilize double-pattern technology; after polysilicon control grid polar curve parallel with active area in P2 cutting zone in storage array is cut; a large amount of residual polycrystalline silicon, above isolation structure, causes the dangerous of the appearance of word line bridging problem.
Therefore, need to propose a kind of new manufacture method, to solve the problem.
Summary of the invention
In summary of the invention part, introduce the concept of a series of reduced form, this will further describe in embodiment part.Summary of the invention part of the present invention does not also mean that the key feature and essential features that will attempt to limit technical scheme required for protection, does not more mean that the protection range attempting to determine technical scheme required for protection.
For the deficiencies in the prior art, the invention provides a kind of manufacture method of semiconductor device, comprising:
Semiconductor substrate is provided;
Described Semiconductor substrate is formed with the multiple active areas extended along first direction;
Described active area is formed the control gate polar curve crossed over multiple described active area and extend along second direction, and wherein said second direction is vertical with described first direction;
Form the cutting mask that definition has cutting area pattern, the described control gate polar curve in described cutting area is etched, removes the described control gate polar curve of active region at least completely.
Alternatively, between adjacent described active area, the isolation structure being positioned at described Semiconductor substrate is also formed with.
Alternatively, the material of described control gate polar curve is polysilicon.
Alternatively, described etch process has the high etching selectivity of polysilicon to oxide.
Alternatively, described active area is all formed with floating grid.
Alternatively, between described floating grid and described control gate polar curve, ONO dielectric layer is formed with.
Alternatively, described etching also comprises and etching the cutting of many described control gate polar curves in described cutting area.
The present invention also provides a kind of semiconductor device adopting said method to manufacture.
The present invention also provides a kind of electronic installation in addition, comprises above-mentioned semiconductor device.
In sum, manufacturing method according to the invention, by changing the layout direction of control gate polar curve and cutting the layout of mask, more easily realizes the control to residual polycrystalline silicon after control gate Linear cut, avoid the appearance of word line bridging problem, and then improve performance and the yield of device.
Accompanying drawing explanation
Following accompanying drawing of the present invention in this as a part of the present invention for understanding the present invention.Shown in the drawings of embodiments of the invention and description thereof, be used for explaining principle of the present invention.
In accompanying drawing:
Figure 1A to Fig. 1 D shows the schematic layout figure of the manufacture method for representing the implementation method integated semiconductor memory arrangement according to prior art, wherein, Figure 1A is vertical view, and Figure 1B is the sectional view of the line A-A along Figure 1A, Fig. 1 C is vertical view, and Fig. 1 D is the sectional view of the line A-A along Fig. 1 C;
Fig. 2 A to Fig. 2 D shows the schematic layout figure of the manufacture method for representing the implementation method integated semiconductor memory arrangement according to the embodiment of the present invention one, wherein, Fig. 2 A is vertical view, Fig. 2 B is the sectional view of the line A-A along Fig. 2 A, Fig. 2 C is vertical view, and Fig. 2 D is the sectional view of the line A-A along Fig. 2 C;
Fig. 3 is the flow chart of the step implemented successively according to method in the embodiment of the present invention one.
Embodiment
In the following description, a large amount of concrete details is given to provide more thorough understanding of the invention.But, it is obvious to the skilled person that the present invention can be implemented without the need to these details one or more.In other example, in order to avoid obscuring with the present invention, technical characteristics more well known in the art are not described.
Should be understood that, the present invention can implement in different forms, and should not be interpreted as the embodiment that is confined to propose here.On the contrary, provide these embodiments will expose thoroughly with complete, and scope of the present invention is fully passed to those skilled in the art.In the accompanying drawings, in order to clear, the size in Ceng He district and relative size may be exaggerated.Same reference numerals represents identical element from start to finish.
Be understood that, when element or layer be called as " ... on ", " with ... adjacent ", " being connected to " or " being coupled to " other element or layer time, its can directly on other element or layer, with it adjacent, connect or be coupled to other element or layer, or the element that can exist between two parties or layer.On the contrary, when element be called as " directly exist ... on ", " with ... direct neighbor ", " being directly connected to " or " being directly coupled to " other element or layer time, then there is not element between two parties or layer.Although it should be understood that and term first, second, third, etc. can be used to describe various element, parts, district, floor and/or part, these elements, parts, district, floor and/or part should not limited by these terms.These terms be only used for differentiation element, parts, district, floor or part and another element, parts, district, floor or part.Therefore, do not departing under the present invention's instruction, the first element discussed below, parts, district, floor or part can be expressed as the second element, parts, district, floor or part.
Spatial relationship term such as " ... under ", " ... below ", " below ", " ... under ", " ... on ", " above " etc., here can be used thus the relation of the element of shown in description figure or feature and other element or feature for convenience of description.It should be understood that except the orientation shown in figure, spatial relationship term intention also comprises the different orientation of the device in using and operating.Such as, if the device upset in accompanying drawing, then, be described as " below other element " or " under it " or " under it " element or feature will be oriented to other element or feature " on ".Therefore, exemplary term " ... below " and " ... under " upper and lower two orientations can be comprised.Device can additionally orientation (90-degree rotation or other orientation) and as used herein spatial description language correspondingly explained.
The object of term is only to describe specific embodiment and not as restriction of the present invention as used herein.When this uses, " one ", " one " and " described/to be somebody's turn to do " of singulative is also intended to comprise plural form, unless context is known point out other mode.It is also to be understood that term " composition " and/or " comprising ", when using in this specification, determine the existence of described feature, integer, step, operation, element and/or parts, but do not get rid of one or more other feature, integer, step, operation, element, the existence of parts and/or group or interpolation.When this uses, term "and/or" comprises any of relevant Listed Items and all combinations.
In order to thoroughly understand the present invention, by following description, detailed step is proposed, to explain the technical scheme of the present invention's proposition.Preferred embodiment of the present invention is described in detail as follows, but except these are described in detail, the present invention can also have other execution modes.
The step that the wordline describing the wordline interface zone of a kind of existing implementation method pair and nand-type flash memory devices below in conjunction with accompanying drawing 1A-1D is cut.
As shown in Figure 1A, Semiconductor substrate 100 is provided, described Semiconductor substrate 100 is formed the multiple active areas 101 having extension along first direction, and the isolation structure 102 in Semiconductor substrate and between described active area, and the control gate polar curve 103 that along first direction extend parallel with active area.The material of described control gate polar curve is polysilicon.A described control gate polar curve part is positioned at active region, and a part is positioned at above trench isolations.In figure, rectangular area 104 is P2 cutting area.As shown in Figure 1B, described control gate polar curve 103 part is positioned at above floating grid 105 and ONO dielectric layer 106, and a part is arranged in above Semiconductor substrate 100 isolation structure 102.
As shown in Fig. 1 C-1D, utilize dual patterning technique, after formation definition has the mask of P2 cutting area pattern, control gate polar curve in P2 cutting area is etched, thicker polysilicon is remained above channel separating zone 102, cause control gate polar curve 103 bridge joint problem, and then have impact on reliability and the yield of memory.
Given this, the present invention proposes a kind of new manufacture method, to solve the problems referred to above of appearance.
Embodiment one
Below, with reference to Fig. 2 A-Fig. 2 D and Fig. 3, the detailed step cut the wordline of the wordline interface zone with nand-type flash memory devices is described.
As seen in figs. 2a-2b, there is provided Semiconductor substrate 200, described Semiconductor substrate 200 can be at least one on silicon, silicon-on-insulator (SOI), insulator on stacked silicon (SSOI), insulator in stacked SiGe (S-SiGeOI), germanium on insulator SiClx (SiGeOI) and germanium on insulator (GeOI).
Described Semiconductor substrate 200 is formed the multiple active areas 201 extended along first direction; Each active area 201 includes multiple charge storage cell, such as floating grid 205.Exemplarily, each active area is formed with multiple floating grid extended along first direction.
The material of described floating grid 205 is including but not limited to some metal, metal alloy, metal nitride and metal silicide, and laminate and its compound.The material of floating grid also can comprise the polysilicon of doping and polysilicon-Ge alloy material and polycide material (polysilicon/metal silicide laminated material of doping).The material of floating grid is polysilicon layer in the present embodiment.Any existing technology can be adopted to form described floating grid, and therefore not to repeat here.The step forming floating grid is for a person skilled in the art that the technological means known just is not described in detail at this, and any applicable method can be adopted to form floating grid.
The top of floating grid 205 is formed with ONO dielectric layer 206.Described ONO dielectric layer 206 is generally the three-decker of oxide-nitride-oxide, exemplarily, lower floor's silica of described three-decker can adopt the method for thermal oxidation or chemical vapour deposition (CVD) to be formed, and silicon nitride often adopts such as low-pressure chemical vapor deposition or plasma reinforced chemical vapour deposition method to be formed.Upper strata silica adopts such as chemical gaseous phase depositing process to be formed.
The isolation structure 202 being positioned at described Semiconductor substrate 200 is also formed between adjacent active regions 201.Alternatively, described isolation structure is that shallow trench isolation is from (STI) structure or selective oxidation silicon (LOCOS) isolation structure.In one example, when isolation structure is fleet plough groove isolation structure, the material of described fleet plough groove isolation structure can be silica, silicon oxynitride and/or other existing advanced low-k materials.
Described active area 201 is formed the control gate polar curve 203 crossed over multiple active area and extend along second direction, and wherein said second direction is vertical with described first direction; In one example, the material of described control gate polar curve is polysilicon.
In one example, the method manufacturing the control gate polar curve extended along second direction comprises: formation control grid layer on ONO dielectric layer 206, described control gate layer is polysilicon layer, then form pattern, this pattern comprise in a second direction extend and in a first direction apart from one another by strip part.Use this pattern to etch control gate layer, form the multiple control gate polar curves extended in a second direction.
Due to the layout change of control gate polar curve, accordingly when adopting double-pattern technology to carry out follow-up P2 cutting, then need to carry out layout again to the required cutting mask plate used of P2 cutting, utilize the cutting mask plate after new layout, form the cutting mask of patterning, on described cutting mask, definition has the pattern of P2 cutting area 204, control gate polar curve 203 in P2 cutting zone 204 in Fig. 2 A is etched, floating grid and isolation structure are come out, described etch process can adopt wet etching or dry etching, etch process has the high etching selectivity of polysilicon to oxide.
Alternatively, adopt dry etching to carry out etch process, dry method etch technology includes but not limited to: reactive ion etching (RIE), ion beam milling, plasma etching or laser cutting.
In a specific embodiment of the present invention, with described graphical photoresist layer for mask, adopt dry etch process, under the etching condition passing into hydrogen bromide and chlorine, etch control gate polar curve, reative cell internal pressure can be 5 ~ 20 millitorrs (mTorr); Power: 300-800W; Time: 5-15s; The range of flow of described hydrogen bromide and chlorine can be 0 ~ 150 cc/min (sccm) and 50 ~ 200 cc/min (sccm).It should be noted that above-mentioned engraving method is only exemplary, be not limited to the method, those skilled in the art can also select other conventional methods.
It is worth mentioning that, in order to easy, in figure, merely illustrate the cutting to a control gate polar curve, and P2 cutting also can carry out cutting etching to many control gate polar curves simultaneously.
As shown in figures 2 c-2d, after P2 cutting etching, the control gate polar curve be positioned on cutting area 204 active area is completely removed, and also may remain a small amount of thinner polysilicon on isolation structure 202.In the process etched control gate polar curve, as long as the control gate polar curve ensured on source region 201 is completely removed, namely above floating grid 205 without residual polycrystalline silicon, then the cutting of control gate polar curve is just successfully completed, and can not produce the risk of word line bridging.
With reference to Fig. 3, show the flow chart that control gate polar curve is cut that the present invention proposes, for schematically illustrating the flow process of whole manufacturing process.
In step 301, Semiconductor substrate is provided; Described Semiconductor substrate is formed with the multiple active areas extended along first direction;
In step 302, described active area is formed the control gate polar curve crossed over multiple described active area and extend along second direction, and wherein said second direction is vertical with described first direction;
In step 303, form the cutting mask that definition has cutting area pattern, the described control gate polar curve in described cutting area is etched, removes the described control gate polar curve of active region at least completely.
In sum, manufacturing method according to the invention, by changing the layout direction of control gate polar curve and cutting the layout of mask, more easily realizes the control to residual polycrystalline silicon after control gate Linear cut, avoid the appearance of word line bridging problem, and then improve performance and the yield of device.
Embodiment two
Present invention also offers a kind of semiconductor device, described semiconductor device selects the method described in embodiment one to prepare.In the semiconductor device prepared by the method for the invention there is not word line bridging problem in control gate polar curve, has excellent performance and yield.
Embodiment three
Present invention also offers a kind of electronic installation, comprise the semiconductor device described in embodiment two.Wherein, semiconductor device is the semiconductor device described in embodiment two, or the semiconductor device that the manufacture method according to embodiment one obtains.
The electronic installation of the present embodiment, can be mobile phone, panel computer, notebook computer, net book, game machine, television set, VCD, DVD, navigator, camera, video camera, recording pen, any electronic product such as MP3, MP4, PSP or equipment, also can be any intermediate products comprising described semiconductor device.The electronic installation of the embodiment of the present invention, owing to employing above-mentioned semiconductor device, thus has better performance.
The present invention is illustrated by above-described embodiment, but should be understood that, above-described embodiment just for the object of illustrating and illustrate, and is not intended to the present invention to be limited in described scope of embodiments.In addition it will be appreciated by persons skilled in the art that the present invention is not limited to above-described embodiment, more kinds of variants and modifications can also be made according to instruction of the present invention, within these variants and modifications all drop on the present invention's scope required for protection.Protection scope of the present invention defined by the appended claims and equivalent scope thereof.
Claims (9)
1. a manufacture method for semiconductor device, comprising:
Semiconductor substrate is provided;
Described Semiconductor substrate is formed with the multiple active areas extended along first direction;
Described active area is formed the control gate polar curve crossed over multiple described active area and extend along second direction, and wherein said second direction is vertical with described first direction;
Form the cutting mask that definition has cutting area pattern, the described control gate polar curve in described cutting area is etched, removes the described control gate polar curve of active region at least completely.
2. method according to claim 1, is characterized in that, between adjacent described active area, be also formed with the isolation structure being positioned at described Semiconductor substrate.
3. method according to claim 1, is characterized in that, the material of described control gate polar curve is polysilicon.
4. method according to claim 3, is characterized in that, described etch process has the high etching selectivity of polysilicon to oxide.
5. method according to claim 1, is characterized in that, described active area is all formed with floating grid.
6. method according to claim 5, is characterized in that, between described floating grid and described control gate polar curve, be formed with ONO dielectric layer.
7. method according to claim 1, is characterized in that, described etching also comprises and etching the cutting of many described control gate polar curves in described cutting area.
8. the semiconductor device of the method manufacture adopting one of claim 1-7 described.
9. an electronic installation, comprises semiconductor device according to claim 8.
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| CN201410269703.4A CN105244321B (en) | 2014-06-17 | 2014-06-17 | A kind of semiconductor devices and its manufacturing method and electronic device |
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| CN201410269703.4A CN105244321B (en) | 2014-06-17 | 2014-06-17 | A kind of semiconductor devices and its manufacturing method and electronic device |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN112864152A (en) * | 2019-11-26 | 2021-05-28 | 长鑫存储技术有限公司 | Memory, substrate structure of memory and preparation method of substrate structure |
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| US20070190719A1 (en) * | 2004-11-24 | 2007-08-16 | Macronix International Co., Ltd. | Method of forming a contact on a semiconductor device |
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| CN112864152A (en) * | 2019-11-26 | 2021-05-28 | 长鑫存储技术有限公司 | Memory, substrate structure of memory and preparation method of substrate structure |
| CN112864152B (en) * | 2019-11-26 | 2022-06-24 | 长鑫存储技术有限公司 | Memory, substrate structure of memory and preparation method of substrate structure |
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| CN105244321B (en) | 2018-12-21 |
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