CN105259676A - Array substrate, display panel and manufacturing method of array substrate - Google Patents
Array substrate, display panel and manufacturing method of array substrate Download PDFInfo
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- CN105259676A CN105259676A CN201510796890.6A CN201510796890A CN105259676A CN 105259676 A CN105259676 A CN 105259676A CN 201510796890 A CN201510796890 A CN 201510796890A CN 105259676 A CN105259676 A CN 105259676A
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- film transistor
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- nontransparent
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/0128—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on electro-mechanical, magneto-mechanical, elasto-optic effects
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/3433—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using light modulating elements actuated by an electric field and being other than liquid crystal devices and electrochromic devices
Abstract
The invention discloses an array substrate, a display panel and a manufacturing method of the array substrate. The array substrate comprises multiple pixel units. A first data line and a second data line are respectively arranged on the two sides of each pixel unit. Each pixel unit comprises a first thin film transistor, a second thin film transistor, a transparent reference layer and a non-transparent deformation layer located above the transparent reference layer and insulated from the transparent reference layer, wherein the output ends of the first thin film transistors are electrically connected with the transparent reference layers, the input ends of the first thin film transistors are electrically connected with the corresponding first data lines, and the control ends of the first thin film transistors are electrically connected with corresponding scanning lines. The output ends of the second thin film transistors are electrically connected with the non-transparent deformation layers, the input ends of the second thin film transistors are electrically connected with the corresponding second data lines, and the control ends of the second thin film transistors are electrically connected with corresponding scanning lines. The display panel manufactured by utilizing the array substrate is simple in structure and low in production cost.
Description
Technical field
The embodiment of the present invention relates to display technique field, particularly relates to the method for making of a kind of array base palte, display panel and array base palte.
Background technology
Information can be presented to people owing to having by display device intuitively, makes the transmission of interpersonal information and exchanges more convenient advantage, being widely used in the Working Life of people.
Along with the development of display technique, display device experienced by display frame from black and white to color so far from birth, and from fuzzy to clear, from bulky thick and heavy to frivolous development course, the performance of display device is also constantly promoting.But the various display device of current main flow, the loaded down with trivial details and high in cost of production problem of such as LCD (LiquidCrystalDisplay) liquid crystal display etc., or ubiquity complex structure, manufacture craft,
Summary of the invention
The invention provides the method for making of a kind of array base palte, display panel and array base palte, to solve the problem that in prior art, display device structure is complicated, preparation technology is loaded down with trivial details and cost is high.
First aspect, embodiments provides a kind of array base palte, comprising:
Multiple pixel cell;
Each pixel cell both sides are respectively arranged with the first data line and the second data line;
Each described pixel cell comprises the first film transistor, the second thin film transistor (TFT), transparent reference layer and to be positioned at above described transparent reference layer and the nontransparent deformation layer insulated with described transparent reference layer;
Wherein, the output terminal of described the first film transistor is electrically connected with described transparent reference layer, and input end is electrically connected with corresponding described first data line, and control end is electrically connected with corresponding sweep trace; The output terminal of described second thin film transistor (TFT) is electrically connected with described nontransparent deformation layer, and input end is electrically connected with corresponding described second data line, and control end is electrically connected with corresponding described sweep trace; Described nontransparent deformation layer according to the voltage difference generation elastic deformation of itself and described transparent reference layer, to change described nontransparent deformation layer to the area coverage of described transparent reference layer.
Second aspect, the embodiment of the present invention additionally provides a kind of display panel, comprising:
Color membrane substrates and the arbitrary described array base palte of first aspect, described array base palte and described color membrane substrates are oppositely arranged.
The third aspect, the embodiment of the present invention additionally provides a kind of method for making of array base palte, comprising:
Form the first film transistor of each pixel cell in multiple pixel cell, the second thin film transistor (TFT) and be positioned at the first data line and second data line of each pixel cell both sides;
In each pixel cell, form transparent reference layer successively and to be positioned at above described transparent reference layer and the nontransparent deformation layer insulated with described transparent reference layer;
Wherein, the output terminal of described the first film transistor is electrically connected with described transparent reference layer, and input end is electrically connected with corresponding described first data line, and control end is electrically connected with corresponding sweep trace; The output terminal of described second thin film transistor (TFT) is electrically connected with described nontransparent deformation layer, and input end is electrically connected with corresponding described second data line, and control end is electrically connected with corresponding described sweep trace; Described nontransparent deformation layer according to the voltage difference generation elastic deformation of itself and described transparent reference layer, to change described nontransparent deformation layer to the area coverage of described transparent reference layer.
The present invention by arranging nontransparent deformation layer and transparent reference layer in each pixel cell of array base palte, by the voltage of nontransparent deformation layer described in the first data line, the second data line and sweep trace co-controlling and transparent reference layer, thus control described deformation layer generation deformation in various degree, the object controlling array substrate light emission rate is reached with this, like this can to the control realizing image display without the need to liquid crystal material, simple relative to structure display device of the prior art, not only simplify production technology, also reduce production cost.
Accompanying drawing explanation
The plan structure schematic diagram of a kind of array base palte that Fig. 1 provides for the embodiment of the present invention;
The cross-sectional view along A1-A2 direction in Fig. 1 that Fig. 2 provides for the embodiment of the present invention;
The cross-sectional view along B1-B2 direction in Fig. 1 that Fig. 3 provides for the embodiment of the present invention;
The plan structure schematic diagram of another array base palte that Fig. 4 provides for the embodiment of the present invention;
The cross-sectional view along D1-D2 direction in Fig. 4 that Fig. 5 provides for the embodiment of the present invention;
The cross-sectional view along E1-E2 direction in Fig. 4 that Fig. 6 provides for the embodiment of the present invention;
The structural representation of another array base palte that Fig. 7 provides for the embodiment of the present invention;
The plan structure schematic diagram of another array base palte that Fig. 8 provides for the embodiment of the present invention;
Fig. 9 is the principle schematic of the array base palte shown in Fig. 8;
The plan structure schematic diagram of another array base palte that Figure 10 provides for the embodiment of the present invention;
The structural representation of a kind of display panel that Figure 11 provides for the embodiment of the present invention;
The schematic flow sheet of the method for making of the array base palte that Figure 12 provides for the embodiment of the present invention.
Embodiment
Below in conjunction with drawings and Examples, the present invention is described in further detail.Be understandable that, specific embodiment described herein is only for explaining the present invention, but not limitation of the invention.It also should be noted that, for convenience of description, illustrate only part related to the present invention in accompanying drawing but not entire infrastructure.
The plan structure schematic diagram of a kind of array base palte that Fig. 1 provides for the embodiment of the present invention, the cross-sectional view along A1-A2 direction in Fig. 1 that Fig. 2 provides for the embodiment of the present invention, the cross-sectional view along B1-B2 direction in Fig. 1 that Fig. 3 provides for the embodiment of the present invention.As shown in Figure 1-Figure 3, the array base palte that the embodiment of the present invention provides, mainly comprises following structure:
Multiple pixel cell (not marking in figure), the first data line 130, second data line 140 and sweep trace 150.
Wherein, each described pixel cell comprises: the first film transistor 110, second thin film transistor (TFT) 120, transparent reference layer 161 and to be positioned at above described transparent reference layer 161 and the nontransparent deformation layer 162 insulated with described transparent reference layer 161; Described first data line 130 and the second data line 140 are arranged on the both sides of each described pixel cell, can be particularly each pixel cell respectively correspondence first data line 130 and second data line 140 are set.
Wherein, the output terminal 111 of the first film transistor 110 is electrically connected with transparent reference layer 161, and input end 112 is electrically connected with the first corresponding data line 130, and control end 113 is electrically connected with corresponding sweep trace 150; The output terminal 121 of the second thin film transistor (TFT) is electrically connected with nontransparent deformation layer 162, and input end 122 is electrically connected with the second corresponding data line 140, and control end 123 is electrically connected with corresponding sweep trace 150; Nontransparent deformation layer 162 according to the voltage difference generation elastic deformation of itself and transparent reference layer 161, to change the area coverage of nontransparent deformation layer 162 pairs of transparent reference layer 161.As shown in Figure 1, interval one first data line 130 and one second data line 140 between adjacent two pixel cells, each pixel cell is controlled by the first data line 130 of its both sides and the second data line 140 respectively.
The principle of work of the array base palte that the present embodiment provides is as follows:
See Fig. 1, sweep trace 150 provides sweep signal for the often capable control end 113 of the first film transistor 110 and the control end 123 of the second thin film transistor (TFT) 120, and the first film transistor 110 of this row and the second thin film transistor (TFT) 120 are opened.First data line 130 provides data-signal to input end 112, second data line 140 of the first film transistor 110 to the input end 122 of the second thin film transistor (TFT) 120; Because the output terminal 111 of described the first film transistor 110 is electrically connected with transparent reference layer 161, the output terminal 121 of the second thin film transistor (TFT) 120 is electrically connected with nontransparent deformation layer 162, so the voltage difference controlling between described transparent reference layer 161 and described nontransparent deformation layer 162 by the data-signal of the first data line 130 and the input of the second data line 140; The deformation of nontransparent deformation layer 162 is controlled whether and the degree of deformation by the voltage of nontransparent deformation layer 162 and the polarity of voltage of transparent reference layer 161 and the size of magnitude of voltage.Concrete, such as when the first data line 130 is identical with the data-signal polarity that the second data line 140 inputs, described transparent reference layer 161 is identical with the polarity of described nontransparent deformation layer 162, there is resupinate elastic deformation (as shown in dotted line in Fig. 2 or Fig. 3) in nontransparent deformation layer 162, light can pass through.Control the voltage difference between the voltage of nontransparent deformation layer 162 and transparent reference layer 161 by the data-signal of the first data line 130 and the input of the second data line 140, control nontransparent deformation layer 162 and upwards overturn degree, thus control the percent of pass of light.When the data-signal polarity that the first data line 130 and the second data line 140 input is contrary, described transparent reference layer 161 is contrary with the polarity of described nontransparent deformation layer 162, there is not deformation in nontransparent deformation layer 162, cover surface of insulating layer completely, light not by, therefore, the array base palte that the embodiment of the present invention provides can realize the adjustment to light penetration.
The embodiment of the present invention by arranging nontransparent deformation layer 162 and transparent reference layer 161 in each pixel cell of array base palte, by the first data line 130, the voltage of the second data line 140 and the nontransparent deformation layer 162 of sweep trace 150 co-controlling and transparent reference layer 161, control nontransparent deformation layer 162 and transparent reference layer 161 voltage difference therebetween and the two respective polarity of voltage, and then the deformation degree of nontransparent deformation layer 162 can be controlled, the area coverage conformal range degree of nontransparent deformation layer 162 pairs of transparent reference layer 161 and changing, the transmitance of light is controlled with this, realize the image display of different gray scales, simple relative to display device structure of the prior art, not only simplify production technology, also reduce production cost.
Preferably, see Fig. 2, the array base palte that above-described embodiment provides, at the first film transistor 110, second thin film transistor (TFT) 120 and the first data line be also provided with insulation course 170 between the second data line place rete and described transparent reference layer 161; The output terminal 111 of the first film transistor is electrically connected with transparent reference layer 161 by insulation course via hole 171, and the output terminal 121 of the second thin film transistor (TFT) is electrically connected with nontransparent deformation layer 162 by insulation course via hole 171.
Further, preferably, described insulation course 170 is set to planarization layer 170, the output terminal 111 of the first film transistor is electrically connected with transparent reference layer 161 by planarization layer via hole 171, and the output terminal 121 of the second thin film transistor (TFT) is electrically connected with nontransparent deformation layer 162 by planarization layer via hole 171.Flatness layer 170 can make transparent reference layer 161 be in smooth plane, thus the relative distance size between transparent reference layer 161 and nontransparent deformation layer 162 is more evenly distributed in the horizontal direction, thus transparent reference layer 161 on flatness layer and on transparent reference layer 161 and and voltage's distribiuting between the nontransparent deformation layer 162 that insulate of transparent reference layer 161 more evenly, more effectively can control nontransparent deformation layer 162 and carry out deformation.
The plan structure schematic diagram of another array base palte that Fig. 4 provides for the embodiment of the present invention, the cross-sectional view along D1-D2 direction in Fig. 4 that Fig. 5 provides for the embodiment of the present invention, the cross-sectional view along E1-E2 direction in Fig. 4 that Fig. 6 provides for the embodiment of the present invention.It should be noted that, for convenience of description, structure same as the previously described embodiments in following embodiment still continues to use identical Reference numeral.See Fig. 4, Fig. 5 and Fig. 6, described array base palte comprises: multiple pixel cell, and each described pixel cell comprises the first film transistor 110, second thin film transistor (TFT) 120, transparent reference layer 161 and to be positioned at above described transparent reference layer 161 and the nontransparent deformation layer 162 insulated with described transparent reference layer 161; Be separately positioned on the first data line 130 and the second data line 140 of each pixel cell both sides.Wherein, the output terminal 111 of the first film transistor 110 is electrically connected with transparent reference layer 161, and input end 112 is electrically connected with the first corresponding data line 130, and control end 113 is electrically connected with corresponding sweep trace 150; The output terminal 121 of the second thin film transistor (TFT) 120 is electrically connected with nontransparent deformation layer 162, and input end 122 is electrically connected with the second corresponding data line 140, and control end 123 is electrically connected with corresponding sweep trace 150.
With above-described embodiment unlike, the array base palte shown in Fig. 4, Fig. 5 and Fig. 6 also comprises:
Protective seam 180, described protective seam 180 covers the subregion of described nontransparent deformation layer 162, for described nontransparent deformation layer 162 is fixed on described array base palte.Described nontransparent deformation layer 162 is connected with described array base palte more firm, prevents nontransparent deformation layer 162 from departing from from described array base palte.Optionally; described protective seam 180 can also be cover same with output terminal 121 electrical connection place of described second thin film transistor (TFT) 120 for described nontransparent deformation layer 162; the benefit of such setting is; nontransparent deformation layer 162 can being made when there is deformation, still can ensure that the output terminal 121 of described nontransparent deformation layer 162 and the second thin film transistor (TFT) realizes electrical connection effectively.Optionally, protective seam 180 can be the nonmetallic materials that viscosity is high, can also be the metal material of conduction, such as copper, aluminium etc.
Optionally, see Fig. 7, when described protective seam 180 is metal material, described nontransparent deformation layer 162 can be realize being electrically connected by the output terminal 121 of described protective seam 180 with described second thin film transistor (TFT) 120.
The plan structure schematic diagram of another array base palte that Fig. 8 provides for the embodiment of the present invention, Fig. 9 is the principle schematic of array base palte shown in Fig. 8.See Fig. 8 and Fig. 9, in above-described embodiment, array base palte comprises: multiple pixel cell, and each described pixel cell comprises the first film transistor 110, second thin film transistor (TFT) 120, transparent reference layer 161 and to be positioned at above described transparent reference layer 161 and the nontransparent deformation layer 162 insulated with described transparent reference layer 161; Be separately positioned on the first data line 130 and the second data line 140 of each pixel cell both sides; And sweep trace 150.
With above-described embodiment unlike, the array base palte shown in Fig. 8 and Fig. 9 can also comprise:
Many reference potential line 190 can be described transparent reference layers 161 and described nontransparent deformation layer 162 insulate with described reference potential line 190 and part is overlapping.Transparent reference layer 161 and nontransparent deformation layer 162 form electric capacity C1 and C2 with reference potential line 190 respectively, and to maintain the voltage on the voltage of transparent reference layer 161 and nontransparent deformation layer 162, thus above-mentioned voltage is sustainable remains to next update picture.
The plan structure schematic diagram of another array base palte that Figure 10 provides for the embodiment of the present invention, as shown in Figure 10, described array base palte comprises: multiple pixel cell, and each described pixel cell comprises the first film transistor 110, second thin film transistor (TFT) 120, transparent reference layer 161 and to be positioned at above described transparent reference layer 161 and the nontransparent deformation layer 162 insulated with described transparent reference layer 161; Be separately positioned on the first data line 130 and the second data line 140 of each pixel cell both sides; Sweep trace 150; Cover the protective seam 180 of described nontransparent deformation layer 162 subregion; And reference potential line 190.
With above-described embodiment unlike, described transparent reference layer 161 and described protective seam 180 insulate with described reference potential line 190 respectively and part is overlapping, and protective seam 180 is electrically connected with nontransparent deformation layer 162.The principle of work of the array base palte that the embodiment of the present invention provides is same as above, and when array base palte is in running order, transparent reference layer 161 and reference potential line 190 form electric capacity, to maintain the voltage of transparent reference layer 161; Nontransparent deformation layer 162 forms electric capacity by protective seam 180 and reference potential line 190, and to maintain the voltage on nontransparent deformation layer 162, thus coating-forming voltage is poor between transparent reference layer 161 and nontransparent deformation layer 162.
It should be noted that, above-mentioned the first film transistor 110 and the second thin film transistor (TFT) 120 can be a-Si amorphous silicon structures, low-temperature polysilicon silicon structure, or oxide-semiconductor structure.
Further, on the basis of above-described embodiment, preferably, reference potential line 190 and sweep trace 150 are in same manufacture craft, be made up of same material, the benefit of design is like this in the production run of array base palte, can reduce processing step, only need same step just can realize reference potential line 190 and the making of sweep trace 150, decrease production cost.
The structural representation of a kind of display panel that Figure 11 provides for the embodiment of the present invention.As shown in figure 11, a kind of display panel that the embodiment of the present invention provides, comprising:
Array base palte 12 arbitrary in color membrane substrates 11 and above-described embodiment, array base palte 12 and color membrane substrates 11 are oppositely arranged.
Further, display panel also comprises:
Support component 13, support component 13 is between array base palte and color membrane substrates 11, and when largest deformation occurs nontransparent deformation layer 162, the thickness of support component 13 is greater than the distance of deformation layer peak and array base palte 12 neighbour color membrane substrates 11 side.The shape of support component 13 can be column structure or cube structure or sphere structure or vertebral body structure or terrace with edge structure, does not do concrete restriction at this.
It should be noted that, the display panel that the embodiment of the present invention provides can also be comprise other devices for supporting display panel normally to work, the display panel that the embodiment of the present invention provides, owing to have employed above-mentioned array base palte 12, therefore has the beneficial effect of above-mentioned array base palte 12 equally.
Preferably, display panel in above-described embodiment, also comprises:
Be arranged at the electrostatic prevention transparency conducting layer (not shown) that color membrane substrates 11 deviates from array base palte 12 side, for preventing electrostatic.Electrostatic prevention transparency conducting layer can be ITO (IndiumTinOxide, tin indium oxide) layer.
The schematic flow sheet of the method for making of the array base palte that Figure 12 provides for the embodiment of the present invention.As shown in figure 12, the method for making of the array base palte that the present embodiment provides, mainly comprises the following steps:
S11: form the first film transistor of each pixel cell in multiple pixel cell, the second thin film transistor (TFT) and be positioned at the first data line and second data line of each pixel cell both sides.
S12: form transparent reference layer successively and to be positioned at above described transparent reference layer and the nontransparent deformation layer insulated with described transparent reference layer in each pixel cell.
Wherein, the output terminal of described the first film transistor is electrically connected with described transparent reference layer, and input end is electrically connected with corresponding described first data line, and control end is electrically connected with corresponding sweep trace; The output terminal of described second thin film transistor (TFT) is electrically connected with described nontransparent deformation layer, and input end is electrically connected with corresponding described second data line, and control end is electrically connected with corresponding described sweep trace; Described nontransparent deformation layer according to the voltage difference generation elastic deformation of itself and described transparent reference layer, to change described nontransparent deformation layer to the area coverage of described transparent reference layer.
Optionally, after forming the first film transistor of each pixel cell in multiple pixel cell, the second thin film transistor (TFT) and the first data line being positioned at each pixel cell both sides and the second data line, in each pixel cell, form transparent reference layer successively and to be positioned at above described transparent reference layer and before the nontransparent deformation layer insulated with described transparent reference layer, can also to comprise:
Above described the first film transistor, described second thin film transistor (TFT) and the first data line and the second data line place rete, form insulation course, and form insulation course via hole and expose the output terminal of described the first film transistor and the output terminal of described second thin film transistor (TFT); The output terminal of described the first film transistor is electrically connected with described transparent reference layer by insulation course via hole, and the output terminal of described second thin film transistor (TFT) is electrically connected with described nontransparent deformation layer by insulation course via hole.
Preferably, in above-described embodiment, after forming the first film transistor of each pixel cell in multiple pixel cell, the second thin film transistor (TFT) and the first data line being positioned at each pixel cell both sides and the second data line, in each pixel cell, form transparent reference layer successively and to be positioned at above described transparent reference layer and before the nontransparent deformation layer insulated with described transparent reference layer, can also to comprise:
Above described the first film transistor, described second thin film transistor (TFT) and the first data line and the second data line place rete, form planarization layer, and form planarization layer via hole and expose the output terminal of described the first film transistor and the output terminal of described second thin film transistor (TFT); The output terminal of described the first film transistor is electrically connected with described transparent reference layer by planarization layer via hole, and the output terminal of described second thin film transistor (TFT) is electrically connected with described nontransparent deformation layer by planarization layer via hole.
Optionally, in above-described embodiment, after the described nontransparent deformation layer of formation, can also comprise:
Form protective seam, described protective seam covers the subregion of described nontransparent deformation layer, for described nontransparent deformation layer is fixed on described array base palte.
Optionally, in above-described embodiment, can also comprise:
Form many reference potential line, described transparent reference layer and described nontransparent deformation layer and described reference potential line insulate and part is overlapping, or described transparent reference layer and and described protective seam and described reference potential line insulate and part is overlapping.Optionally, described reference potential line can be formed with sweep trace simultaneously, and the benefit of design like this to reduce processing step, enhances productivity.
Note, above are only preferred embodiment of the present invention and institute's application technology principle.Skilled person in the art will appreciate that and the invention is not restricted to specific embodiment described here, various obvious change can be carried out for a person skilled in the art, readjust and substitute and can not protection scope of the present invention be departed from.Therefore, although be described in further detail invention has been by above embodiment, the present invention is not limited only to above embodiment, when not departing from the present invention's design, can also comprise other Equivalent embodiments more, and scope of the present invention is determined by appended right.
Claims (15)
1. an array base palte, is characterized in that, comprising:
Multiple pixel cell;
Each pixel cell both sides are respectively arranged with the first data line and the second data line;
Each described pixel cell comprises the first film transistor, the second thin film transistor (TFT), transparent reference layer and to be positioned at above described transparent reference layer and the nontransparent deformation layer insulated with described transparent reference layer;
Wherein, the output terminal of described the first film transistor is electrically connected with described transparent reference layer, and input end is electrically connected with corresponding described first data line, and control end is electrically connected with corresponding sweep trace; The output terminal of described second thin film transistor (TFT) is electrically connected with described nontransparent deformation layer, and input end is electrically connected with corresponding described second data line, and control end is electrically connected with corresponding described sweep trace; Described nontransparent deformation layer according to the voltage difference generation elastic deformation of itself and described transparent reference layer, to change described nontransparent deformation layer to the area coverage of described transparent reference layer.
2. array base palte according to claim 1, is characterized in that, at described the first film transistor, described second thin film transistor (TFT) and the first data line be also provided with insulation course between the second data line place rete and described transparent reference layer; The output terminal of described the first film transistor is electrically connected with described transparent reference layer by insulation course via hole, and the output terminal of described second thin film transistor (TFT) is electrically connected with described nontransparent deformation layer by insulation course via hole.
3. array base palte according to claim 1, is characterized in that, at described the first film transistor, described second thin film transistor (TFT) and the first data line be also provided with planarization layer between the second data line place rete and described transparent reference layer; The output terminal of described the first film transistor is electrically connected with described transparent reference layer by planarization layer via hole, and the output terminal of described second thin film transistor (TFT) is electrically connected with described nontransparent deformation layer by planarization layer via hole.
4. array base palte according to claim 1, is characterized in that, described array base palte also comprises:
Protective seam, described protective seam covers the subregion of described nontransparent deformation layer, for described nontransparent deformation layer is fixed on described array base palte.
5. array base palte according to claim 4, is characterized in that, described array base palte also comprises:
Many reference potential line, described transparent reference layer and described nontransparent deformation layer and described reference potential line insulate and part is overlapping, or described transparent reference layer and described protective seam and described reference potential line insulate and part is overlapping.
6. array base palte according to claim 5, is characterized in that, described reference potential line and described sweep trace, in same manufacture craft, are made up of same material.
7. array base palte according to claim 4, is characterized in that, described protective seam is metal material.
8. a display panel, is characterized in that, comprising:
Arbitrary described array base palte in color membrane substrates and claim 1-7, described array base palte and described color membrane substrates are oppositely arranged.
9. display panel according to claim 8, is characterized in that, also comprise:
Support component, described support component is between described array base palte and described color membrane substrates, when described nontransparent deformation layer generation largest deformation, the thickness of described support component is greater than the distance of described deformation layer peak and described array base palte neighbour color membrane substrates side.
10. display panel according to claim 9, is characterized in that, also comprise:
Be arranged at the electrostatic prevention transparency conducting layer that described color membrane substrates deviates from described array base palte side.
The method for making of 11. 1 kinds of array base paltes, is characterized in that, comprising:
Form the first film transistor of each pixel cell in multiple pixel cell, the second thin film transistor (TFT) and be positioned at the first data line and second data line of each pixel cell both sides;
In each pixel cell, form transparent reference layer successively and to be positioned at above described transparent reference layer and the nontransparent deformation layer insulated with described transparent reference layer;
Wherein, the output terminal of described the first film transistor is electrically connected with described transparent reference layer, and input end is electrically connected with corresponding described first data line, and control end is electrically connected with corresponding sweep trace; The output terminal of described second thin film transistor (TFT) is electrically connected with described nontransparent deformation layer, and input end is electrically connected with corresponding described second data line, and control end is electrically connected with corresponding described sweep trace; Described nontransparent deformation layer according to the voltage difference generation elastic deformation of itself and described transparent reference layer, to change described nontransparent deformation layer to the area coverage of described transparent reference layer.
12. methods according to claim 11, it is characterized in that, after forming the first film transistor of each pixel cell in multiple pixel cell, the second thin film transistor (TFT) and the first data line being positioned at each pixel cell both sides and the second data line, in each pixel cell, form transparent reference layer successively and to be positioned at above described transparent reference layer and before the nontransparent deformation layer insulated with described transparent reference layer, also to comprise:
Above described the first film transistor, described second thin film transistor (TFT) and the first data line and the second data line place rete, form insulation course, and form insulation course via hole and expose the output terminal of described the first film transistor and the output terminal of described second thin film transistor (TFT); The output terminal of described the first film transistor is electrically connected with described transparent reference layer by insulation course via hole, and the output terminal of described second thin film transistor (TFT) is electrically connected with described nontransparent deformation layer by insulation course via hole.
13. methods according to claim 11, it is characterized in that, after forming the first film transistor of each pixel cell in multiple pixel cell, the second thin film transistor (TFT) and the first data line being positioned at each pixel cell both sides and the second data line, in each pixel cell, form transparent reference layer successively and to be positioned at above described transparent reference layer and before the nontransparent deformation layer insulated with described transparent reference layer, also to comprise:
Above described the first film transistor, described second thin film transistor (TFT) and the first data line and the second data line place rete, form planarization layer, and form planarization layer via hole and expose the output terminal of described the first film transistor and the output terminal of described second thin film transistor (TFT); The output terminal of described the first film transistor is electrically connected with described transparent reference layer by planarization layer via hole, and the output terminal of described second thin film transistor (TFT) is electrically connected with described nontransparent deformation layer by planarization layer via hole.
14. methods according to claim 11, is characterized in that, after the described nontransparent deformation layer of formation, also comprise:
Form protective seam, described protective seam covers the subregion of described nontransparent deformation layer, for described nontransparent deformation layer is fixed on described array base palte.
15. methods according to claim 14, is characterized in that, also comprise:
Form many reference potential line, described transparent reference layer and described nontransparent deformation layer and described reference potential line insulate and part is overlapping, or described transparent reference layer and and described protective seam and described reference potential line insulate and part is overlapping.
Priority Applications (1)
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| CN111937059A (en) * | 2018-03-30 | 2020-11-13 | 夏普株式会社 | Display device and method for manufacturing display device |
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| WO2012165745A1 (en) * | 2011-06-01 | 2012-12-06 | 한국과학기술원 | Display device |
| CN103926755A (en) * | 2013-12-30 | 2014-07-16 | 厦门天马微电子有限公司 | Display and manufacturing method thereof |
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| US5781331A (en) * | 1997-01-24 | 1998-07-14 | Roxburgh Ltd. | Optical microshutter array |
| US20100053727A1 (en) * | 2008-09-03 | 2010-03-04 | Lee Son-Uk | Display Device |
| CN101726893A (en) * | 2008-10-28 | 2010-06-09 | 乐金显示有限公司 | Horizontal electric field liquid crystal display |
| WO2012165745A1 (en) * | 2011-06-01 | 2012-12-06 | 한국과학기술원 | Display device |
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