CN105336603A - Composite oxide film structure - Google Patents
Composite oxide film structure Download PDFInfo
- Publication number
- CN105336603A CN105336603A CN201410362684.XA CN201410362684A CN105336603A CN 105336603 A CN105336603 A CN 105336603A CN 201410362684 A CN201410362684 A CN 201410362684A CN 105336603 A CN105336603 A CN 105336603A
- Authority
- CN
- China
- Prior art keywords
- film
- oxide
- base
- sih
- lto
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Formation Of Insulating Films (AREA)
Abstract
The invention discloses a composite oxide film structure. According to one aspect of the invention, a manufacturing method of the composite oxide film structure is provided. The method comprises the steps as follows: a first oxide film is deposited on a semiconductor substrate; a cavity structure is formed in the first oxide film and is filled with a pre-filling material; a second oxide film is deposited on the first oxide film; a tap hole is etched at the position above the cavity structure and in the second oxide film; the pre-filling material is removed; and the second oxide film is further deposited, so that the hole is closed by the depositing material. According to the other aspect of the invention, the manufacturing method of the composite oxide film structure is provided. The method comprises the steps as follows: two or more composite sub-layers are sequentially deposited on the semiconductor substrate, wherein each composite sub-layer comprises the first oxide film and the second oxide film; the second oxide film is deposited on the first oxide film; and the material stress of the first oxide film is opposite to that of the second oxide film in direction.
Description
Technical field
The present invention relates to semiconductor fabrication, more specifically, the present invention relates to low-temperature oxidation membrane structure and manufacture method thereof.
Background technology
Along with the large-scale application of 3D encapsulation technology, the research of wafer-class encapsulation (waferlevelpackage, WLP) also reaches its maturity.A kind of wafer-level packaging processes is rear through hole (vialast) technique, and its principal character the forming step of through-hole structure is placed on finally to complete.
Figure 1A-1D shows the schematic process processing wafer according to the rear via process of prior art.For making figure succinct, structure identical in each figure only marks once with Reference numeral.As shown in Figure 1A, the technique of front end is formed and is loaded with the wafer of device and necessary operator guards (be only illustrated object, this wafer is shown as inversion.In actual processing, wafer can be any orientation).Dorsal part grinding (grinding) is carried out to the base part 101 of wafer, obtains the thickness and evenness expected.Subsequently, as shown in Figure 1B, through-hole structure 102 is obtained by dry etch process, and at the bottom deposit contact material (such as, contact layer 103) of through hole 102.Subsequently, as shown in Figure 1 C, with the depositing operation of such as CVD, oxide-film 104 is deposited on wafer surface (comprising in through hole), then the oxide etching of via bottoms is fallen, expose contact layer 103.Finally, as shown in figure ip, by the mode such as sputtered, redistribution layer (RDL) 105 is applied to wafer surface, and utilizes wet-etching technology to obtain the RDL figure expected.
For the consideration of reliability, the prior art shown in Figure 1A-1D, and other similar techniques of this area, when using the deposited oxide films such as CVD and PVD, need to take low temperature process.Such as, for CVD, usually require that temperature is lower than 200 DEG C.LTO film is called as with the oxide-film that low temperature is obtained.On the other hand, have certain thickness requirement for oxide-film, such as, its thickness should reach 20K (20000 dust).But, find in practice, with during the oxide-film that low temperature process deposition is thicker, some problems can occur.
The two kinds of oxide-films often used in IC manufacturing are based on SiH
4the oxide-film obtained and the oxide-film obtained based on TEOS (tetraethoxysilane, TetraEthoxySilane).Industry is also referred to as SiH
4base oxide-film and TEOS base oxide-film.
For SiH
4base oxide-film, its film formation reaction is:
SiH
4+2N
2O→SiO
2+2N
2+2H
2
For TEOS base oxide-film, its film formation reaction is:
Si(C
2H
5O)
4+8O
3→SiO
2+10H
2O+8CO
2
When adopting low temperature process to obtain above-mentioned two kinds of oxide-films, it is correspondingly called SiH
4base LTO film and TEOS base LTO film.
Find in actual production, being applied in wafer-class encapsulation by above-mentioned two kinds of oxide-films has problem to produce.SiH
4the thickness of base oxide-film and stress uniformity are better, but its step coverage is poor, and such as, in the sidewall position, bottom of groove structure, oxide thickness can be solely 60-80nm, may be destroyed in the etching process of such thickness before PVD.The step coverage of TESO base oxide-film is better, but the uniformity of its thickness and stress is poor, produces variable color (discolor) phenomenon in wafer surface.
In view of SiH
4base oxide-film and TEOS base oxide-film all have certain problem separately, consider two kinds of films to combine, and obtain complex oxide film.Such as, 10KTEOS+10KSiH is used
4structure, the ability utilizing TEOS base oxide-film to have good step coverage carries out filling out hole, then grows SiH thereon
4base oxide-film, utilizes the good ability of its thickness evenness to avoid the problem of variable color.
But, because the stress of above-mentioned two kinds of oxide-films there are differences, serious stripping (peeling) problem therefore may be there is in actual applications.Fig. 2 A illustrates exemplary SiH
4the stress test that base oxide-film and example T EOS base oxide-film are done, result show, after with CVD deposited oxide film, TEOS base oxide-film stress ratio SiH
4base oxide-film is high, and two kinds of tress in oxide scale numerical value differences are about 50MPa; After this difference constantly increases in time, and after 48 hours, difference is more than 100MPa.When being formed by SiH with low temperature process
4during the compound LTO film that base LTO film and TEOS base LTO film are formed, the problems referred to above seem more outstanding.Existing process practice surface, after low temperature CVD deposition, TEOS base LTO film and SiH
4the stress difference of base LTO film constantly increases in time, and after 48 hours, difference about reaches 230MPa.
Fig. 2 B illustrates the exemplary SiH under another process conditions
4the stress test that base oxide-film and example T EOS base oxide-film are done, result show, after with CVD deposited oxide film, TEOS base oxide-film stress and SiH
4base oxide-film answers direction contrary, and two kinds of tress in oxide scale numerical value differences are about 220MPa; After this difference constantly increases in time, and after 48 hours, difference is more than 350MPa.
The TEOS base LTO film more than illustrated and SiH
4base LTO membrane stress difference is exemplary.In concrete technology, according to adjustment reaction chamber air pressure, the process conditions such as deposition power, may obtain the various combinations of different stress numerical and stress direction.The common problem that they face is the stripping problem that stress difference causes.
Therefore, industry needs a kind of new semiconductor structure and manufacturing process to solve SiH
4the stripping problem that the stress difference of base oxide-film and TEOS base oxide-film causes.
Summary of the invention
The problems referred to above that the present invention is directed to prior art propose solution, make the stripping problem of complex oxide film be eliminated or improve.
The present invention is to SiH
4the complex oxide film that base oxide-film and TEOS base oxide-film are formed carries out the change of structure.A kind of scheme adds cavity structure in TEOS base oxide-film, makes the stress of TEOS base oxide-film obtain part release.This scheme is applicable to the combination of the various stress parameters of oxide-film.Another kind of scheme forms MULTIPLE COMPOSITE oxide-film, wherein TEOS base LTO film and SiH
4base LTO film stacks gradually, and forms four layers of compound LTO film, the characteristic release stress utilizing adjacent LTO membrane stress direction contrary.This scheme is particularly useful for the contrary situation of the stress of two kinds of oxide-films.
According to an aspect of the present invention, propose a kind of manufacture method of combined oxidation membrane structure, comprising: deposit the first oxide-film on the semiconductor substrate; Cavity structure is formed in described first oxide-film; Pre-filled material is filled in described cavity structure; Depositing second oxide film on described first oxide-film; In described second oxide-film, described cavity structure top position place etching portal; Remove described pre-filled material; And continue described second oxide-film of deposition, make deposition materials close described hole.
According to an aspect of the present invention, in previous building methods, described first oxide-film is TEOS base oxide-film, and described second oxide-film is SiH
4base oxide-film.
According to an aspect of the present invention, in previous building methods, remove described pre-filled material with cineration technics.
According to an aspect of the present invention, in previous building methods, the material stress direction of described second oxide-film is identical with the material stress direction of described first oxide-film.
According to an aspect of the present invention, in previous building methods, under low temperature process condition, deposit described first oxide-film and the second oxide-film.
According to an aspect of the present invention, in previous building methods, described cavity structure comprises the multiple discrete cavities be distributed in described first oxide-film; Preferably, the bore of each discrete cavities is 10-50 μm.
According to an aspect of the present invention, in previous building methods, described pre-filled material is amorphous carbon.
According to an aspect of the present invention, in previous building methods, the step of filling pre-filled material in described cavity structure comprises: deposit the whole surface of pre-filled material to semiconductor chip; The pre-filled material be deposited on beyond cavity structure is removed by flatening process.
According to an aspect of the present invention, in previous building methods, the diameter in described hole is
According to an aspect of the present invention, propose a kind of combined oxidation membrane structure, comprising: the first oxide-film on the semiconductor substrate; And the second oxide-film on described first oxide-film, wherein, in described first oxide-film, be formed with cavity structure.
According to an aspect of the present invention, in aforementioned combined oxidation membrane structure, described first oxide-film is TEOS base oxide-film, and described second oxide-film is SiH
4base oxide-film.
According to an aspect of the present invention, in aforementioned combined oxidation membrane structure, the material stress direction of described second oxide-film is identical with the material stress direction of described first oxide-film.
According to an aspect of the present invention, a kind of manufacture method of combined oxidation membrane structure is proposed, comprise: deposit two or more compound sublayers on the semiconductor substrate successively, wherein each compound sublayer comprises the first oxide-film and is deposited on the second oxide-film on the first oxide-film, and the material stress of wherein said first oxide-film is contrary with the material stress direction of described second oxide-film.
According to an aspect of the present invention, propose a kind of manufacture method of combined oxidation membrane structure, comprising: deposit the first oxide-film on the semiconductor substrate; Depositing second oxide film on the semiconductor substrate; Deposit the 3rd oxide-film on the semiconductor substrate; And deposit the 4th oxide-film on the semiconductor substrate; Wherein, the material stress of described first oxide-film is contrary with the material stress direction of described second oxide-film, and described 3rd oxide-film is identical with the material of described first oxide-film, and described 4th oxide-film is identical with the material of described second oxide-film.
According to an aspect of the present invention, in previous building methods, described first and second oxide-films form the first compound sublayer, and described third and fourth oxide-film forms the second compound sublayer, and the thickness of described first compound sublayer is less than the thickness of described second compound sublayer.
According to an aspect of the present invention, in previous building methods, the thickness of described first compound sublayer accounts for the 25%-50% of complex oxide film total structure thickness.
According to an aspect of the present invention, in previous building methods, described first oxide-film is TEOS base LTO film, and described second oxide-film is SiH
4base LTO film.
According to an aspect of the present invention, in previous building methods, the thickness proportion of described first oxide-film and the second oxide-film is 1:4, and the thickness ratio of described 3rd oxide-film and the 4th oxide-film is 1:4.
According to an aspect of the present invention, propose a kind of semiconductor device comprising combined oxidation membrane structure, it is characterized in that, described combined oxidation membrane structure obtains according to the foregoing method of any one.
Technique effect of the present invention at least comprises: by futuramic combined oxidation membrane structure, reduces the stress of oxide-film, eliminates/improve the stripping problem of oxide-film.
Accompanying drawing explanation
In order to illustrate above and other advantage and the feature of various embodiments of the present invention further, present the description more specifically of various embodiments of the present invention with reference to accompanying drawing.In the accompanying drawings, identical Reference numeral is used in reference to same or similar element in some views or function, and element might not be drawn each other in proportion in accompanying drawing, Individual elements can be exaggerated or reduce to be easier to understand these elements in the context of this description.Be appreciated that exemplary embodiments of the present invention only described by these accompanying drawings, therefore will not be considered to restriction on its scope.
Figure 1A-1D shows the schematic process processing wafer according to the rear via process of prior art.
Fig. 2 A-2B illustrates exemplary SiH
4the result of the stress test that base oxide-film and example T EOS base oxide-film are done.
Fig. 3 illustrates the schematic diagram of the semiconductor structure according to the first embodiment of the present invention.
Fig. 4 A-4F illustrates the schematic process of the deposition complex oxide film according to the first embodiment of the present invention.
Fig. 5 illustrates the example flow of the deposition complex oxide film according to the first embodiment of the present invention.
Fig. 6 illustrates the schematic diagram of semiconductor structure according to a second embodiment of the present invention.
Fig. 7 A gives and takes the example wafer #1 of NEW TYPE OF COMPOSITE LTO structure of the present invention and the stress data of example wafer #2.
Fig. 7 B illustrates the example chart of the Plotting data according to Fig. 7 A.
Fig. 8 A-8D illustrates the schematic process of deposition four layers of compound LTO film according to a second embodiment of the present invention.
Fig. 9 illustrates the example flow of deposition four layers of compound LTO film according to a second embodiment of the present invention.
Embodiment
Detailed description is below with reference to accompanying drawing, and accompanying drawing illustrates the specific embodiment can putting into practice theme required for protection by way of illustration.Fully describe these embodiments in detail, to make those skilled in the art, this theme is dropped into practice.Although be appreciated that each embodiment is different, not necessarily mutually repel.Such as, the special characteristic, structure or the characteristic that describe in conjunction with an embodiment here can realize in other embodiments and not depart from the spirit and scope of theme required for protection.Similarly, in order to the object explained, specific quantity, material and configuration are set forth, to provide the complete understanding to embodiments of the invention.But the present invention can implement when not having specific detail.Should be understood that the position of each key element can revised in each disclosed embodiment or configuration in addition and required by not departing from.
first embodiment: introduce cavity structure in TEOS base oxide-film
Fig. 3 illustrates the schematic diagram of the semiconductor structure according to the first embodiment of the present invention.For succinct object, the various device architecture on wafer and the contact layer of via bottoms are omitted, and what describe emphatically is the special oxide-film structure that rear via process is formed.Exemplarily, the oxide-film in Fig. 3 is the LTO film that low temperature process condition is formed.
As shown in Figure 3, after formation through-hole structure, the oxide-film of deposition is TEOS base LTO film 301 and SiH
4base LTO film 302.Unlike the prior art, the present invention introduces cavity 303 in TEOS base LTO film 301.Due to the introducing of cavity 303, TEOS base LTO film is made to have certain noncontinuity, can the release of the achievement unit component of stress in the position of cavity 303, thus reduce the integrated stress value of this oxide-film, increase the binding ability of two kinds of oxide-films, reduce the possibility that stripping problem occurs.
Cavity 303 is introduced by various suitable technique.The preferred embodiments of the present invention realize the formation of cavity by introducing non-type carbon (AmorphousCarbon, AC).
The detailed process forming cavity is described in detail below in conjunction with Fig. 4 A-4F and Fig. 5.Wherein, Fig. 4 A-4F illustrates the schematic process of the deposition complex oxide film according to the first embodiment of the present invention.For concise and to the point object, structure identical in each figure only marks once with Reference numeral.Fig. 5 illustrates the example flow of the deposition complex oxide film according to the first embodiment of the present invention.
First, as shown in Figure 4 A, (such as, in the dorsal part substrate of wafer making device architecture) deposition (such as with CVD) TEOS base oxide-film 401 (step 501) on wafer.Needing low temperature to make in the manufacturing process (after such as through hole technique) of oxide-film, oxide-film 401 is LTO film.
Subsequent, as shown in Figure 4 B, in TEOS base oxide-film 401, form cavity structure 402 (step 502) with suitable etch process.Cavity structure 402 can be evenly distributed in wafer.Cavity shape can be cylindrical, elliptical cylinder-shape and cube shaped etc.Number of cavities increase can reduce stress in thin film, but should be taken into account that cavity density is crossed conference and caused film strength to decline simultaneously, causes subsiding of upper strata rete.Therefore, the size of cavity structure 402, shape and distribution mode can need be in optimized selection according to actual process.
Subsequent, as shown in Figure 4 C, in cavity structure 402, insert pre-filler (step 503).Exemplarily, amorphous carbon 403 is inserted.The mode inserting amorphous carbon 403 can be: with CVD depositing either amorphous C film, and utilizes flatening process removal to be deposited on cavity structure 402 with the amorphous carbon of exterior domain.Additive method, such as stripping technology (liftoff) are also feasible.
Subsequent, as shown in Figure 4 D, TEOS base oxide-film 401 deposits certain thickness SiH with such as CVD
4base oxide-film 404 (step 504).Needing low temperature to make in the manufacturing process (after such as through hole technique) of oxide-film, oxide-film 404 is LTO film.SiH
4the thickness of base oxide-film 404 should control the SiH for being no more than technique initialization
4base oxide-film gross thickness (such as, 10K).
Subsequent, as shown in Figure 4 E, the SiH above empty cavity position
4405 (steps 505) of portalling are etched in base oxide-film 404.The preferred diameter in hole 405 can be
after obtaining hole 405, then use ashing (asher) technique to be removed (step 506) by amorphous carbon 403, obtain cavity structure 406.
Subsequent, as illustrated in figure 4f, at SiH
4again with such as CVD deposition SiH on base oxide-film 404
4base oxide.By suitable adjusting process condition, the oxide of deposition can be formed at hole 405 place and hang (overhang), thus is closed in hole 405, obtains SiH
4base oxide-film 407 (step 507).Ideally, hole 405 can be filled up by the suspension effect of deposition oxide substantially, obtains result as shown in Figure 3.Under actual process condition, less space may be left at hole 405 place as illustrated in figure 4f.This does not affect effect of the present invention.SiH
4the deposition of base oxide is sustainable, until the thickness of overall complex oxide film reaches the gross thickness needed for technique, and such as 20K.
So far the oxide film with cavity structure has been completed.By the introducing of cavity, make TEOS base oxide-film can the release of the achievement unit component of stress in the position of cavity.The stress of TEOS base oxide-film is higher than SiH
4base oxide-film.By reducing the stress value of TEOS base oxide-film, increasing the binding ability of two kinds of oxide-films, reducing the possibility peeled off and occur.
In the above-described embodiments, by TEOS base oxide-film and SiH
4base oxide-film composition complex oxide film.But the present invention is not limited thereto, but be applicable to the lamination of any two kinds of oxide-films, add cavity in layer oxide film (normally lower-layer oxide film) wherein, make its stress obtain part release.In the above-described embodiments, use amorphous carbon as the pre-filler of cavity.Amorphous carbon applies to sacrifice layer in field of semiconductor manufacture more, and its characteristic is to be discharged by certain high temperature under excess oxygen, than general SiN, SiO
2it is more easy that material is removed.Meanwhile, the hardness of amorphous carbon itself meets again some strength requirement, becomes the good material of cavity pre-filler.It will be understood by those skilled in the art that and the invention is not restricted to use amorphous carbon.Any material utilizing cineration technics to be removed (under the prerequisite not damaging required semiconductor structure) all can be used as cavity pre-filler.
In above-described embodiment, give the concrete technology method forming cavity.But the present invention should contain any complex oxide film utilizing cavity structure to discharge stress, no matter this complex oxide film with which kind of concrete technology obtains.
In the above-described embodiments, at TEOS base oxide-film and SiH
4when the stress direction of base oxide-film consistent (such as shown in Fig. 2 A), because cumulative stress effect is more obvious, the cavity scheme therefore utilizing the present invention to propose effectively can discharge stress.But cavity scheme of the present invention is for TEOS base oxide-film and SiH
4the stress parameters (numerical value, direction) of base oxide-film can not be restricted.More broadly say, as long as the stress of two kinds of oxide-films has difference, cavity scheme of the present invention all can be utilized to discharge the stress of total layer stack.
second embodiment: MULTILAYER COMPOSITE LTO film
Under some process conditions, the TEOS base oxide-film formed and SiH
4base oxide-film has contrary stress direction.Such as, as shown in Figure 2 B, thickness is the SiH of 20K
4the stress of base oxide-film is about-80MPa, and the stress that thickness is the TEOS base oxide-film of 20K is about 150MPa.Therefore, due to adjacent SiH
4the stresses counteract of base oxide-film and TEOS base oxide-film, the net impact of oxide-film composite construction can be controlled in less numerical value (being ideally zero).Based on this, applicant proposes the second embodiment of the present invention.
Fig. 6 illustrates the schematic diagram of semiconductor structure according to a second embodiment of the present invention.For succinct object, the various device architecture on wafer and the contact layer of via bottoms are omitted, and what describe emphatically is the special oxide-film structure that rear via process is formed.Oxide-film in Fig. 6 is such as the LTO film of low temperature process condition formation.
As shown in Figure 6, after formation through-hole structure, the LTO film of deposition is MULTIPLE COMPOSITE structure, is followed successively by from the bottom up: TEOS base LTO film 501, SiH
4base LTO film 502, TEOS base LTO film 503, SiH
4base LTO film 504.For ease of explanation hereinafter, the structure that LTO film 501 and 502 forms is become lower floor LTO, the structure that LTO film 503 and 504 forms is called upper strata LTO.
Facts have proved, this novel MULTIPLE COMPOSITE LTO structure of Fig. 6 serves the positive effect in front for the release of stress.Fig. 7 A gives and takes the stress data of the example wafer #1 of novel MULTIPLE COMPOSITE LTO structure of the present invention and example wafer #2 (measure stress data after often forming a LTO film, each wafer records 4 secondary stress data).For wafer #1, after formation TEOS base LTO film, stress data is+10.4, at formation SiH
4after base LTO film, stress data is-2.6, and after another TEOS base of formation LTO film, stress data is+26.4, at another SiH of formation
4after base LTO film, stress data is-22.6.Often add a LTO film, stress data is just reversed adjustment once, and the numerical value of the stress data therefore finally obtained is controlled as less.Data according to wafer #2 can draw identical conclusion.Fig. 7 B illustrates the example chart of the Plotting data according to Fig. 7 A, shows the situation of change of stress data more intuitively.
The detailed process forming cavity is described in detail below in conjunction with Fig. 8 A-8D and Fig. 9.Wherein, Fig. 8 A-8D illustrates the schematic process of deposition four layers of compound LTO film according to a second embodiment of the present invention.For concise and to the point object, structure identical in each figure only marks once with Reference numeral.The deposition that Fig. 9 illustrates according to a second embodiment of the present invention amasss the example flow of four layers of compound LTO film.
First, as shown in Figure 8 A, (such as, in the dorsal part substrate of wafer making device architecture) deposition (such as with CVD) TEOS base LTO film 801 (step 901) on wafer.
Subsequent, as shown in Figure 8 B, continue deposition SiH
4base LTO film 802 (step 901).
TEOS base LTO film 801 and SiH
4base LTO film 802 forms lower floor LTO.The thickness of lower floor LTO preferably controls comparatively thin (gross thickness relative to LTO composite construction), is beneficial to contact with wafer backside.Such as, for the expectation gross thickness of 20K, the thickness of lower floor LTO can be set to 5-10K.In addition, the Thickness Ratio that can arrange film 801 and 802 reduces the total stress of lower floor LTO as much as possible.Specifically, TEOS base LTO film 801 and the SiH of condition of equivalent thickness is considered
4(stress numerical of TEOS basement membrane 801 compares SiH to the numerical values recited difference of the stress of base LTO film 802
4the stress numerical of basement membrane 802 is large), suitably film thickness can be set, make the little of the Thickness Ratio film 802 of film 801, reach the object of stresses counteract.Exemplarily, can by TEOS basement membrane and SiH
4the thickness proportion of basement membrane is set to about 1:4.
Subsequent, as shown in Figure 8 C, (such as, in the dorsal part substrate of wafer making device architecture) deposition (such as with CVD) TEOS base LTO film 801 (step 903) on wafer.
Subsequent, as in fig. 8d, continue deposition SiH
4base LTO film 802 (step 904).
TEOS base LTO film 803 and SiH
4base LTO film 804 forms upper strata LTO.The thickness of upper strata LTO preferably controls comparatively thick, to reach the gross thickness of four layers of compound LTO film.Such as, for the expectation gross thickness of 20K, the thickness of upper strata LTO can be set to 10-15K.The thickness of film 803 and 804 also suitably can be set, make the little of the Thickness Ratio film 804 of film 803, reach the object of stresses counteract.Example, can by TEOS basement membrane 803 and SiH
4the thickness proportion of basement membrane 804 is set to about 1:4.
So far four layers of compound LTO film have been completed.The introducing of multiple layer stack structure can the release of the achievement unit component of stress, and increase the binding ability of two kinds of oxide-films, reduces to peel off the possibility occurred.
In above-described embodiment, require TEOS base oxide-film and SiH
4base oxide-film is all the LTO film formed under low temperature process.It will be understood by those skilled in the art that and the present invention is not limited thereto, but easily extensible is to any complex oxide film, the first wherein adjacent oxide-film and the stress of the second oxide-film are contrary.
In above-described embodiment, provide the example of four layers of compound LTO film.It will be understood by those skilled in the art that and the invention is not restricted to four layers of composite construction, but more multi-layered compound scheme can be taked.
In above-described embodiment, what first formed is the TEOS base oxide-film of normal stress, but the present invention is not limited thereto.Under some process conditions, and the illustrative situation of Fig. 2 B is contrary, and the stress of TEOS base film is negative, SiH
4the stress of base oxide-film is just, now multi-layer compound structure of the present invention is still applicable.More broadly, for any first oxide-film and the second oxide-film, as long as their stress direction is contrary, multi-layer compound structure of the present invention can be taked to reduce the net impact of general structure.
Although here used various method and system describe and show some example technique, but it will be appreciated by those skilled in the art that can make multiple other amendment and replaceable do not depart from equivalent required theme or its spirit.In addition, many amendments can be made and do not depart from core concept described herein to adapt to the special circumstances of the instruction of required theme.Therefore, be intended to make theme required for protection be not limited only to disclosed particular example, but these claimed themes also can comprise all realizations dropped in appended claims and equivalency range thereof.
Claims (20)
1. a manufacture method for combined oxidation membrane structure, comprising:
Deposit the first oxide-film on the semiconductor substrate;
Cavity structure is formed in described first oxide-film;
Pre-filled material is filled in described cavity structure;
Depositing second oxide film on described first oxide-film;
In described second oxide-film, described cavity structure top position place etching portal;
Remove described pre-filled material; And
Continue described second oxide-film of deposition, make deposition materials close described hole.
2. manufacture method as claimed in claim 1, it is characterized in that, described first oxide-film is TEOS base oxide-film, and described second oxide-film is SiH
4base oxide-film.
3. manufacture method as claimed in claim 1, is characterized in that, removes described pre-filled material with cineration technics.
4. manufacture method as claimed in claim 1, the material stress direction of described second oxide-film is identical with the material stress direction of described first oxide-film.
5. manufacture method as claimed in claim 1, is characterized in that, deposit described first oxide-film and the second oxide-film under low temperature process condition.
6. manufacture method as claimed in claim 1, it is characterized in that, described cavity structure comprises the multiple discrete cavities be distributed in described first oxide-film.
7. method as claimed in claim 6, it is characterized in that, the bore of each discrete cavities is 10-50 μm.
8. manufacture method as claimed in claim 1, it is characterized in that, described pre-filled material is amorphous carbon.
9. manufacture method as claimed in claim 1, it is characterized in that, the step of filling pre-filled material in described cavity structure comprises:
Deposit the whole surface of pre-filled material to semiconductor chip;
The pre-filled material be deposited on beyond cavity structure is removed by flatening process.
10. the method for claim 1, is characterized in that, the diameter in described hole is
11. 1 kinds of combined oxidation membrane structures, comprising:
The first oxide-film on the semiconductor substrate; And
The second oxide-film on described first oxide-film,
Wherein, cavity structure is formed with in described first oxide-film.
12. combined oxidation membrane structures as claimed in claim 11, is characterized in that, described first oxide-film is TEOS base oxide-film, and described second oxide-film is SiH
4base oxide-film.
13. combined oxidation membrane structures as claimed in claim 11, is characterized in that, the material stress direction of described second oxide-film is identical with the material stress direction of described first oxide-film.
The manufacture method of 14. 1 kinds of combined oxidation membrane structures, comprising:
Deposit two or more compound sublayers on the semiconductor substrate successively,
Wherein each compound sublayer comprises the first oxide-film and is deposited on the second oxide-film on the first oxide-film, and the material stress of wherein said first oxide-film is contrary with the material stress direction of described second oxide-film.
The manufacture method of 15. 1 kinds of combined oxidation membrane structures, comprising:
Deposit the first oxide-film on the semiconductor substrate;
Depositing second oxide film on the semiconductor substrate;
Deposit the 3rd oxide-film on the semiconductor substrate; And
Deposit the 4th oxide-film on the semiconductor substrate;
Wherein, the material stress of described first oxide-film is contrary with the material stress direction of described second oxide-film, and described 3rd oxide-film is identical with the material of described first oxide-film, and described 4th oxide-film is identical with the material of described second oxide-film.
16. manufacture methods as claimed in claim 15, it is characterized in that, described first and second oxide-films form the first compound sublayer, and described third and fourth oxide-film forms the second compound sublayer, and the thickness of described first compound sublayer is less than the thickness of described second compound sublayer.
17. manufacture methods as claimed in claim 16, is characterized in that, the thickness of described first compound sublayer accounts for the 25%-50% of complex oxide film total structure thickness.
18. manufacture methods as claimed in claim 16, is characterized in that, described first oxide-film is TEOS base LTO film, and described second oxide-film is SiH
4base LTO film.
19. manufacture methods as claimed in claim 18, it is characterized in that, the thickness proportion of described first oxide-film and the second oxide-film is 1:4, the thickness ratio of described 3rd oxide-film and the 4th oxide-film is 1:4.
20. 1 kinds of semiconductor device comprising combined oxidation membrane structure, is characterized in that, the method for described combined oxidation membrane structure according to any one of claim 1-10,14-19 obtains.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410362684.XA CN105336603A (en) | 2014-07-28 | 2014-07-28 | Composite oxide film structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410362684.XA CN105336603A (en) | 2014-07-28 | 2014-07-28 | Composite oxide film structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN105336603A true CN105336603A (en) | 2016-02-17 |
Family
ID=55287048
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410362684.XA Pending CN105336603A (en) | 2014-07-28 | 2014-07-28 | Composite oxide film structure |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN105336603A (en) |
Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1206935A (en) * | 1997-07-25 | 1999-02-03 | 三星电子株式会社 | Trough isolation method by using composite oxidic film |
| JPH1187500A (en) * | 1997-09-05 | 1999-03-30 | Fujitsu Ltd | Semiconductor device and fabrication thereof |
| US5933746A (en) * | 1996-04-23 | 1999-08-03 | Harris Corporation | Process of forming trench isolation device |
| CN101123204A (en) * | 2006-08-10 | 2008-02-13 | 中芯国际集成电路制造(上海)有限公司 | Method for forming shallow groove separation structure and shallow groove separation structure |
| CN102539033A (en) * | 2012-03-09 | 2012-07-04 | 上海宏力半导体制造有限公司 | Method for making micro electromechanical system pressure sensor |
| CN102714136A (en) * | 2009-09-10 | 2012-10-03 | 奥普特冈有限公司 | A method for reducing internal mechanical stresses in a semiconductor structure and a low mechanical stress semiconductor structure |
| CN103035515A (en) * | 2012-07-18 | 2013-04-10 | 上海华虹Nec电子有限公司 | Filling method of groove |
| US20130161783A1 (en) * | 2011-12-21 | 2013-06-27 | Jeong-Seob OH | Semiconductor device including isolation layer and method for fabricating the same |
-
2014
- 2014-07-28 CN CN201410362684.XA patent/CN105336603A/en active Pending
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5933746A (en) * | 1996-04-23 | 1999-08-03 | Harris Corporation | Process of forming trench isolation device |
| CN1206935A (en) * | 1997-07-25 | 1999-02-03 | 三星电子株式会社 | Trough isolation method by using composite oxidic film |
| JPH1187500A (en) * | 1997-09-05 | 1999-03-30 | Fujitsu Ltd | Semiconductor device and fabrication thereof |
| CN101123204A (en) * | 2006-08-10 | 2008-02-13 | 中芯国际集成电路制造(上海)有限公司 | Method for forming shallow groove separation structure and shallow groove separation structure |
| CN102714136A (en) * | 2009-09-10 | 2012-10-03 | 奥普特冈有限公司 | A method for reducing internal mechanical stresses in a semiconductor structure and a low mechanical stress semiconductor structure |
| US20130161783A1 (en) * | 2011-12-21 | 2013-06-27 | Jeong-Seob OH | Semiconductor device including isolation layer and method for fabricating the same |
| CN102539033A (en) * | 2012-03-09 | 2012-07-04 | 上海宏力半导体制造有限公司 | Method for making micro electromechanical system pressure sensor |
| CN103035515A (en) * | 2012-07-18 | 2013-04-10 | 上海华虹Nec电子有限公司 | Filling method of groove |
Non-Patent Citations (1)
| Title |
|---|
| 刘金声: "《离子束沉积薄膜技术及应用》", 31 January 2003 * |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US9959500B1 (en) | Embedded spin transfer torque memory for cellular neural network based processing unit | |
| US8975152B2 (en) | Methods of reducing substrate dislocation during gapfill processing | |
| JP2010225697A (en) | Method for manufacturing semiconductor device | |
| CN101452875B (en) | Method of forming isolation layer in semiconductor device | |
| US20160079521A1 (en) | Dielectric repair for emerging memory devices | |
| US20120205804A1 (en) | Method to fabricate copper wiring structures and structures formed tehreby | |
| CN110459464B (en) | Preparation method of thick film silicon nitride by regional grooving | |
| CN101490811B (en) | Method for manufacturing semiconductor device | |
| CN102543835A (en) | Opening filling method | |
| TW201234527A (en) | Methods and systems for fabrication of MEMS CMOS devices | |
| CN102082114A (en) | Forming method of dual damascene structure | |
| CN108550525A (en) | Floating boom preparation method | |
| CN116598194B (en) | Hard mask manufacturing method and memory | |
| CN105336603A (en) | Composite oxide film structure | |
| CN100590811C (en) | Method for filling medium between metals in semiconductor wafer fabrication | |
| CN102903613B (en) | Eliminate the method for bridge joint in contact hole technique | |
| CN102586758B (en) | Method for pre-depositing high-density plasma machine platform | |
| KR100465093B1 (en) | Method For Manufacturing Semiconductor Devices | |
| CN105174208B (en) | A kind of manufacture method of MEMS | |
| CN103066093A (en) | Image sensor manufacturing method through adoption of deep groove isolation and image sensor structure | |
| CN102509711A (en) | Method for detecting defect of shallow trench isolation | |
| CN104261346B (en) | A kind of micro mechanical structure sacrifice layer and micro mechanical structure manufacture method | |
| CN102420169A (en) | Double-Damascus process of super-thick top-layer metal by virtue of filling sacrifice material in through hole | |
| CN102832161B (en) | Method for forming through-silicon-via | |
| KR102506953B1 (en) | PVD deposition and annealing of multilayer metallic dielectric films |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20160217 |