CN105374872A - Double polycrystalline silicon power MOS transistor and preparation method thereof - Google Patents

Abstract

The invention discloses a double polycrystalline silicon power MOS transistor and a preparation method thereof. The double polycrystalline silicon power MOS transistor is mainly formed by an N+ substrate, an N-type epitaxial layer, a thick oxidization layer, source polycrystalline silicon, a gate oxidization layer, gate polycrystalline, a body region P, a source region N+, boron-phosphorosilicate glass, a P+ region, a tungsten plug, a source electrode, and a drain electrode. According to the double polycrystalline silicon power MOS transistor and the preparation method thereof, the double-POLY structure (Source Poly and Gate Poly) and the oxidization layers with different thicknesses are employed, the function of MOS devices is satisfied, the capacitance between electrodes is reduced, the capacitances between the Gate and the Drain and between the Gate and the Source are greatly reduced, the charging time during switch-on and switch-off of the Gate is greatly reduced (the gate charge density Qg can be greatly reduced), the switching speed of the MOS transistor is increased, and a deep groove 3D structure is employed so that the influence of the epitaxial thickness on the internal resistance Ron is reduced, and Low Ron is realized.

Description

A kind of dual poly power MOS pipe and preparation method thereof

Technical field

The present invention relates to technical field of semiconductors, be specifically related to a kind of dual poly power MOS pipe and preparation method thereof.

Background technology

Power MOS pipe, when back-pressure is higher, bears back-pressure by epitaxial loayer, and the resistivity of epitaxial loayer is comparatively large, and thickness is thicker, and cause epilayer resistance to account for the ratio of overall conducting resistance maximum, therefore, the effect improving epilayer resistance is the most obvious.Popular method is the three-dimensional 3D structure adopting similar super junction SuperJunction as shown in Figure 1.

The 3D structure of similar SuperJunction reduces epilayer resistance from two aspects.On the one hand, from single vertical direction, vague and general to change into vertical and horizontal both direction vague and general in space charge region, reduces vague and general distance; On the other hand, when ensureing that metal-oxide-semiconductor cut-off time space charged region majority carrier can exhaust, improve epitaxial loayer carrier concentration, then during metal-oxide-semiconductor conducting, the resistivity of epitaxial loayer is just as far as possible little as far as possible.Just diminished at withstand voltage constant situation lower epi layer resistance or overall conducting resistance like this, during power MOS pipe work, heating is just few.But current SuperJunction and 3D structure all exists certain technical difficulty, its core technology all rests in foreign brand name producer and domestic minority supplier hand.

Summary of the invention

Technical problem to be solved by this invention is to provide a kind of dual poly power MOS pipe and preparation method thereof, and it under the prerequisite meeting MOS device function, can reach the object of the electric capacity reducing pole and interpolar, thus improve the switching speed of metal-oxide-semiconductor.

For solving the problem, the present invention is achieved by the following technical solutions:

A kind of dual poly power MOS pipe, primarily of N+ substrate, N-type epitaxy layer, thick oxide layer, source polysilicon, grid oxic horizon, grid polycrystalline silicon, tagma P, source region N+, boron-phosphorosilicate glass, P+ district, tungsten plug, source electrode and drain electrode composition; Wherein N-type epitaxy layer is positioned at directly over N+ substrate; The middle part of N-type epitaxy layer offers the deep trench of longitudinal extension, and thick oxide layer is overlying on the cell wall of deep trench; Source polysilicon is filled in the groove of deep trench being covered with thick oxide layer; The gate trench of longitudinal extension is offered in thick oxide layer between source polysilicon and N-type epitaxy layer, this gate trench is retained in the side of close source polysilicon certain thickness thick oxide layer, and gate trench then digs N-type epitaxy layer place in the side near N-type epitaxy layer; Grid polycrystalline silicon is filled with in gate trench; Grid oxic horizon is positioned at the outside of gate trench, and in longitudinal extension; Tagma P is positioned at the outside of grid oxic horizon; Source region N+ is positioned at the outside of grid oxic horizon, and is in directly over the P of tagma; The outside of source region N+ is provided with tungsten plug; P+ district is positioned at the bottom of tungsten plug, and is in the top in P+ district; Boron-phosphorosilicate glass covers the top of source region N+, thick oxide layer, source polysilicon, grid oxic horizon and grid polycrystalline silicon; Source electrode is positioned at directly over tungsten plug and boron-phosphorosilicate glass; Drain electrode is positioned at immediately below N+ substrate.

A kind of dual poly power MOS pipe and preparation method thereof, comprises the steps:

Step 1, grows N-type epitaxy layer above the N+ substrate of crystal;

Step 2, produces deep trench in the N-type epitaxy layer of crystal, and growth has certain thickness thick oxide layer on the cell wall of deep trench;

Step 3, in the groove of the deep trench of crystal, plated metal or polysilicon are as good conductor; Namely

Step 3.1, has in the groove of the deep trench of thick oxide layer in growth and fills source polysilicon;

Step 3.2, etching crystal upper surface, to form source polysilicon structure;

Step 3.3, gate trench is dug out in thick oxide layer between source polysilicon and N-type epitaxy layer, this gate trench is retained in the side of close source polysilicon certain thickness thick oxide layer, and gate trench then digs N-type epitaxy layer place in the side near N-type epitaxy layer;

Step 3.4, grows the grid oxic horizon of longitudinal extension in the N-type epitaxy layer outside gate trench;

Step 3.5, fills grid polycrystalline silicon in gate trench;

Step 4, spreads knot downwards from the upper surface of crystal, and at formation tagma, the outside P of grid oxic horizon;

Step 5, spreads knot downwards from the upper surface of crystal again, and forms source region N+ directly over the outside of grid oxic horizon, tagma P;

Step 6, at the upper surface deposition boron-phosphorosilicate glass of crystal;

Step 7, makes contact hole by lithography in boron-phosphorosilicate glass and source region N+;

Step 8, injects boron ion in the bottom of contact hole, forms P+ district;

Step 9, above P+ district, the outside of source region N+ fills tungsten plug;

Step 10, carries out evaporation of aluminum operation to crystal, forms source electrode with the upper surface at this crystal;

Step 11, the N+ substrate of thinning crystal, and form drain electrode at thinning N+ substrate lower surface back of the body gold.

Compared with prior art, the present invention utilizes two POLY structure (SourcePoly and GatePoly) to utilize the oxide layer of different-thickness, under the prerequisite meeting MOS device function, reach the object of the electric capacity reducing pole and interpolar, significantly reduce between Gate and Drain and the electric capacity of Gate and Source, thus the charging interval (gate charge density Qg can significantly reduce) when significantly reducing Gate switch, improve the switching speed of metal-oxide-semiconductor, and utilize deep trouth class 3D structure, reduce epitaxial thickness to the impact of internal resistance Ron, realize LowRon.

Accompanying drawing explanation

Fig. 1 is the three-dimensional structure schematic diagram of existing super junction.

Fig. 2 is a kind of two POLY power MOS pipe schematic diagram.

Fig. 3-Figure 18 is the process drawing of a kind of pair of POLY power MOS pipe shown in Fig. 2.

Embodiment

A kind of dual poly power MOS pipe, as shown in Figure 2, it is primarily of N+ substrate, N-type epitaxy layer, thick oxide layer, source polysilicon, grid oxic horizon, grid polycrystalline silicon, tagma P, source region N+, boron-phosphorosilicate glass, P+ district, tungsten plug, source electrode and drain electrode composition.Wherein N-type epitaxy layer is positioned at directly over N+ substrate.The middle part of N-type epitaxy layer offers the deep trench of longitudinal extension, and thick oxide layer is overlying on the cell wall of deep trench.Source polysilicon is filled in the groove of deep trench being covered with thick oxide layer.The gate trench of longitudinal extension is offered in thick oxide layer between source polysilicon and N-type epitaxy layer, this gate trench is retained in the side of close source polysilicon certain thickness thick oxide layer, and gate trench then digs N-type epitaxy layer place in the side near N-type epitaxy layer.Grid polycrystalline silicon is filled with in gate trench.Grid oxic horizon is positioned at the outside of gate trench, and in longitudinal extension.Tagma P is positioned at the outside of grid oxic horizon.Source region N+ is positioned at the outside of grid oxic horizon, and is in directly over the P of tagma.The outside of source region N+ is provided with tungsten plug.P+ district is positioned at the bottom of tungsten plug, and is in the top in P+ district.Boron-phosphorosilicate glass covers the top of source region N+, thick oxide layer, source polysilicon, grid oxic horizon and grid polycrystalline silicon.Source electrode is positioned at directly over tungsten plug and boron-phosphorosilicate glass.Drain electrode is positioned at immediately below N+ substrate.

Its preparation method of above-mentioned dual poly (POLY) power MOS pipe, comprises the steps:

Step 1, grows N-type epitaxy layer above the N+ substrate of crystal; See Fig. 3.

Step 2, produces deep trench in the N-type epitaxy layer of crystal, and the thick oxide layer that growth thickness is thicker on the cell wall of deep trench.

Step 2.1, in the photomask surface groove figure of crystal; See Fig. 4.

Step 2.2, etches deep trench at the middle part of crystal; See Fig. 5.

Step 2.3, the thick oxide layer that growth thickness is thicker on the wall of deep trench; See Fig. 6.

Step 3, in the groove of the deep trench of crystal, plated metal or polysilicon are as good conductor.

Step 3.1, has in the groove of the deep trench of thick oxide layer in growth and fills source polysilicon (SourcePoly); See Fig. 7.

Step 3.2, etching crystal upper surface, to form source polysilicon structure; See Fig. 8.

Step 3.3, gate trench is dug out in thick oxide layer between source polysilicon and N-type epitaxy layer, this gate trench is retained in the side (i.e. inner side) near source polysilicon certain thickness thick oxide layer, and gate trench then digs N-type epitaxy layer place in the side (i.e. outside) near N-type epitaxy layer; See Fig. 9.

Step 3.4, grows the grid oxic horizon of longitudinal extension in the N-type epitaxy layer outside gate trench; See Figure 10.

Step 3.5, fills grid polycrystalline silicon (GatePoly) in gate trench; See Figure 11.

Step 4, spreads knot downwards from the upper surface of crystal, and at formation tagma, the outside P of grid oxic horizon; See Figure 12.

Step 5, spreads knot downwards from the upper surface of crystal again, and forms source region N+ directly over the outside of grid oxic horizon, tagma P; See Figure 13.

Step 6, deposits boron-phosphorosilicate glass (BPSG) to protect grid (Gate) at the upper surface of crystal; See Figure 14.

Step 7, makes contact hole by lithography in boron-phosphorosilicate glass and source region N+; See Figure 15.

Step 8, at the bottom of contact hole low-yield injection boron ion, forms P+ district; See Figure 16.

Step 9, above P+ district, the outside of source region N+ fills tungsten plug; See Figure 17.

Step 10, carries out evaporation of aluminum operation to crystal, forms source electrode with the upper surface at this crystal; See Figure 18.

Step 11, the N+ substrate of thinning crystal, and form drain electrode (Drain) at thinning N+ substrate lower surface back of the body gold; See Fig. 2.

Claims (2)

1. a dual poly power MOS pipe, is characterized in that: primarily of N+ substrate, N-type epitaxy layer, thick oxide layer, source polysilicon, grid oxic horizon, grid polycrystalline silicon, tagma P, source region N+, boron-phosphorosilicate glass, P+ district, tungsten plug, source electrode and drain electrode composition; Wherein N-type epitaxy layer is positioned at directly over N+ substrate; The middle part of N-type epitaxy layer offers the deep trench of longitudinal extension, and thick oxide layer is overlying on the cell wall of deep trench; Source polysilicon is filled in the groove of deep trench being covered with thick oxide layer; The gate trench of longitudinal extension is offered in thick oxide layer between source polysilicon and N-type epitaxy layer, this gate trench is retained in the side of close source polysilicon certain thickness thick oxide layer, and gate trench then digs N-type epitaxy layer place in the side near N-type epitaxy layer; Grid polycrystalline silicon is filled with in gate trench; Grid oxic horizon is positioned at the outside of gate trench, and in longitudinal extension; Tagma P is positioned at the outside of grid oxic horizon; Source region N+ is positioned at the outside of grid oxic horizon, and is in directly over the P of tagma; The outside of source region N+ is provided with tungsten plug; P+ district is positioned at the bottom of tungsten plug, and is in the top in P+ district; Boron-phosphorosilicate glass covers the top of source region N+, thick oxide layer, source polysilicon, grid oxic horizon and grid polycrystalline silicon; Source electrode is positioned at directly over tungsten plug and boron-phosphorosilicate glass; Drain electrode is positioned at immediately below N+ substrate.

2., based on a kind of described in claim 1 preparation method of dual poly power MOS pipe, it is characterized in that comprising the steps:

Step 1, grows N-type epitaxy layer above the N+ substrate of crystal;

Step 2, produces deep trench in the N-type epitaxy layer of crystal, and growth has certain thickness thick oxide layer on the cell wall of deep trench;

Step 3, in the groove of the deep trench of crystal, plated metal or polysilicon are as good conductor; Namely

Step 3.1, has in the groove of the deep trench of thick oxide layer in growth and fills source polysilicon;

Step 3.2, etching crystal upper surface, to form source polysilicon structure;

Step 3.3, gate trench is dug out in thick oxide layer between source polysilicon and N-type epitaxy layer, this gate trench is retained in the side of close source polysilicon certain thickness thick oxide layer, and gate trench then digs N-type epitaxy layer place in the side near N-type epitaxy layer;

Step 3.4, grows the grid oxic horizon of longitudinal extension in the N-type epitaxy layer outside gate trench;

Step 3.5, fills grid polycrystalline silicon in gate trench;

Step 4, spreads knot downwards from the upper surface of crystal, and at formation tagma, the outside P of grid oxic horizon;

Step 5, spreads knot downwards from the upper surface of crystal again, and forms source region N+ directly over the outside of grid oxic horizon, tagma P;

Step 6, at the upper surface deposition boron-phosphorosilicate glass of crystal;

Step 7, makes contact hole by lithography in boron-phosphorosilicate glass and source region N+;

Step 8, injects boron ion in the bottom of contact hole, forms P+ district;

Step 9, above P+ district, the outside of source region N+ fills tungsten plug;

Step 10, carries out evaporation of aluminum operation to crystal, forms source electrode with the upper surface at this crystal;

Step 11, the N+ substrate of thinning crystal, and form drain electrode at thinning N+ substrate lower surface back of the body gold.