CN105513976A - Semiconductor packaging method, packaging body and packaging unit - Google Patents
Semiconductor packaging method, packaging body and packaging unit Download PDFInfo
- Publication number
- CN105513976A CN105513976A CN201510874625.5A CN201510874625A CN105513976A CN 105513976 A CN105513976 A CN 105513976A CN 201510874625 A CN201510874625 A CN 201510874625A CN 105513976 A CN105513976 A CN 105513976A
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- carrier
- packaging
- encapsulation unit
- metal
- packaging body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/568—Temporary substrate used as encapsulation process aid
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
Abstract
The invention provides a semiconductor packaging method, a packaging body and a packaging unit. The packaging method comprises the following steps of providing a packaging body with a plurality of packaging units, wherein the first surface of the packaging body is bonded to a carrier; cutting the packaging body to enable the packaging units to be independent from one another; metalizing the packaging units bonded to the carrier to metalize all metal cut planes that are exposed out of the packaging units; and removing the carrier. According to the technical scheme of the invention, the carrier bonded to the packaging body is utilized. That is to say, the metalizing operation is conducted by an insulating carrier or a conductive carrier of the packaging body itself to realize the completely metalized effect of pins without any additional process. Therefore, the reliable improvement is realized. Moreover, the pins of a frame can be flexibly and conveniently designed.
Description
Technical field
The present invention relates to field of semiconductor package, particularly relate to a kind of method for packaging semiconductor, packaging body and encapsulation unit.
Background technology
See Fig. 1, packaging body is made up of the base island 10 of central authorities and the pin 11 arranged around base island 10 in the bottom in chip package space, chip placement 12 on base island 10, each conductive part on chip 12 is electrically connected with each pin 11 respectively by metal wire 13, all the other encapsulated space filling epoxy resins.For DFN technique, because it only has both sides to have pin, so, after described packaging body plastic packaging, cutting and separating is carried out to packaging body, as shown in Figure 1, after cutting, the cut surface of pin 11 can be exposed to relative two sides (part as indicated by the arrows in the figure) of described packaging body, is unfavorable for the requirement of reliability and solderability like this.
And traditional mode that pin side is electroplated, that conduction rack (or connecting muscle) 14 is set on the other two relative side of packaging body, pin 11 is electrically connected to external frame 15 by described conduction rack 14, form galvanic circle, after first time cutting (being longitudinal cutting in figure), adopt electroplating technology, utilize conduction rack 14 to be exposed to the pin electroplated metal layer 16 of described packaging body two relative side.
After completing plating, carry out second time cutting (transverse direction), conduction rack 14 is separated.
But, four sides are all had to the QFN technique of pin, as shown in Figure 2, upper and lower pin 11 adopts dotted line to indicate, pin 11 on packaging body side cutting conduction rack 14 and this side, conduction rack 14 and pin 11 have tangent plane (in as Fig. 2 arrow indication part) in this side.
There is shortcoming in the method for above-mentioned conventional side pin plated metal: due to first time cut complete after, the two relative side that described packaging body exposes pin tangent plane there is no other structures exist, namely there is not the structure be connected with the pin of other two relative side, therefore, the pin exposed after second time cutting and conduction rack cannot form galvanic circle with external structure, its tangent plane cannot plated metal, can reduce the reliability of packaging body product.
Due to this shortcoming of packaging body, the packaging body making this kind of four sides have pin is unsuitable for the high product of reliability requirement.Therefore, the packaging body product that a kind of reliability is high is badly in need of.
Summary of the invention
Technical problem to be solved by this invention is, provides a kind of method for packaging semiconductor, packaging body and encapsulation unit, and it can realize pin and entirely plate, and improves reliability.
In order to solve the problem, the invention provides a kind of method for packaging semiconductor, comprise the steps: to provide the packaging body with multiple encapsulation unit, the first surface of described packaging body is combined with a carrier; Cutting step is carried out to described packaging body, to make described encapsulation unit independent of one another; Plating step is carried out, to make the metal tangent plane exposing to described encapsulation unit all by plating to described carrier-bound described encapsulation unit; Remove described carrier.
Further, described carrier is conductive carrier, the first surface of described packaging body is the one side that described packaging body has lead frame, and the method for described plating is: carry out energising plating, to make the whole plated metal of metal tangent plane exposing to described encapsulation unit to described encapsulation unit and conductive carrier.
Further, before plating step, deviate from a surface coverage mask of described encapsulation unit at described conductive carrier.
Further, conductive carrier is carbon steel, is the carrier of the lead frame before the encapsulation of described packaging body.
Further, before described packaging body is combined with described carrier, also comprise the step of a preplating, for the bare metal plated metal blocked by follow-up for described packaging body loaded body.
Further, described carrier is insulating carrier, the first surface of described packaging body is the one side of described packaging body away from lead frame, and the method for described plating is: carry out chemical plating to described encapsulation unit, belongs to make the metal tangent plane overgild exposing to described encapsulation unit.
Further, after cutting described packaging body, the cut surface of described encapsulation unit lateral leads and the pin of bottom surface expose, and in electroless plating step, expose to the metal tangent plane of described encapsulation unit all by plating.
Further, described insulating carrier is UV film.
Further, described UV film one side is fixed on a nonmetal supporter, and another side is combined with the first surface of described packaging body.
Further, in the step removing described insulating carrier, the method for irradiating ultraviolet light is adopted to remove described UV film.
The present invention also provides a kind of packaging body, comprises multiple setting on the same vector and encapsulation unit independent of each other, exposes to the metal tangent plane of encapsulation unit described in each all by plating.
Further, described carrier is arranged on described encapsulation unit and has the one side of lead frame or described carrier is arranged on the one side of described encapsulation unit away from lead frame.
The present invention also provides a kind of encapsulation unit, and described encapsulation unit at least has the metal tangent plane that cutting is formed adjacent two sides, all described metal tangent planes are all coated with the coat of metal.
Further, each side of described encapsulation unit is provided with pin, and the metal tangent plane of each pin is all coated with the coat of metal.
Further, each metal tangent plane coat of metal uniformity.
Further, described pin has at least the intersection in two faces to have dividing strip, and the coat of metal of dividing strip both sides has difference characteristic.
Further, described difference characteristic is the thickness difference of the dividing strip both sides coat of metal.
An advantage of the present invention is, utilizes the carrier be combined with packaging body, such as, utilizes the conductive carrier of insulating carrier or packaging body itself to carry out plating, do not need extra processing procedure can realize pin and entirely electroplate, improve reliability; And frame pin can design flexibly and easily.
Accompanying drawing explanation
Fig. 1 is the structural representation of existing packaging body;
Fig. 2 is the schematic cross-section of existing packaging body;
Fig. 3 is the step schematic diagram of method for packaging semiconductor of the present invention;
Fig. 4 is the step schematic diagram of method for packaging semiconductor first embodiment plating of the present invention;
Fig. 5 A ~ Fig. 5 E is the flow chart of method for packaging semiconductor first embodiment of the present invention;
Fig. 6 is the step schematic diagram of method for packaging semiconductor second embodiment plating of the present invention;
Fig. 7 A ~ Fig. 7 D is the flow chart of method for packaging semiconductor second embodiment of the present invention;
Fig. 8 is the structural representation of the first embodiment of packaging body of the present invention;
Fig. 9 is the structural representation of the second embodiment of packaging body of the present invention;
Figure 10 is the structural representation of encapsulation unit made according to the method for the present invention.
Embodiment
Elaborate below in conjunction with the embodiment of accompanying drawing to method for packaging semiconductor provided by the invention, packaging body and encapsulation unit.
See Fig. 3, method for packaging semiconductor of the present invention comprises the steps: step S1, provides the packaging body with multiple encapsulation unit, and the first surface of described packaging body is combined with a carrier; Step S2, cutting step is carried out to described packaging body, to make described encapsulation unit independent of one another; Step S3, carry out plating step to described carrier-bound described encapsulation unit, to make the metal tangent plane exposing to described encapsulation unit all by plating; Step S4, remove described carrier.
In the first embodiment of method for packaging semiconductor of the present invention, described carrier is conductive carrier, and the first surface of described packaging body is the one side that described packaging body has lead frame.See Fig. 4, in the first embodiment of method for packaging semiconductor of the present invention, described method for plating metal comprises the steps: step S40, deviates from a surface coverage mask of described encapsulation unit at described conductive carrier; Step S41, described encapsulation unit and conductive carrier carried out to energising plating, to make the whole plated metal of metal tangent plane exposing to described encapsulation unit.
Fig. 5 A ~ Fig. 5 E is the schematic flow sheet of method for packaging semiconductor first embodiment of the present invention.
See step S1 and Fig. 5 A, provide the packaging body with multiple encapsulation units 31, the first surface 38 of described packaging body is combined with a conductive carrier 32.In this embodiment, two encapsulation units 31 are only schematically enumerated.
Further, described conductive carrier 32 is carbon steel, and the first surface of described packaging body is the one side that described packaging body has lead frame 33.Described conductive carrier 32 is the carrier that lead frame 33 has itself, carries out supporting described lead frame 33 in the process of die bond, routing and encapsulation at lead frame 33.Therefore, described conductive carrier 32 is not add package bottom in this step, but the supporting construction of lead frame 33 itself., to electroplate in advance bottom described lead frame 33, for by follow-up for the described packaging body bare metal electroplated metal layer blocked by conductive carrier 32 before covering conductive carrier 32 when described lead frame 33 makes.
See step S2 and Fig. 5 B, cutting step is carried out to described packaging body, to make described encapsulation unit 31 independent of one another.The cutting of this step does not cut conductive carrier 32, to make conductive carrier 32 can be connected with each encapsulation unit 31, in follow-up plating step, forms plating loop.After this cutting step, metal tangent plane 35 exposes to described encapsulation unit 31, and described metal tangent plane 35 comprises the metal tangent plane of pin, can also comprise the metal tangent plane of other structures of encapsulation unit 31.
See step S40 and Fig. 5 C, deviate from a surface coverage mask 34 of described encapsulation unit 31 at described conductive carrier 32.
Another surface deviating from encapsulation unit 31 due to described conductive carrier 32 does not need plating, in order to save plated material, described mask 34 covers another surface that described conductive carrier 32 deviates from described encapsulation unit 31, is plated with another surface avoiding described conductive carrier 32 to deviate from described encapsulation unit 31.
See step S41 and Fig. 5 D, energising plating is carried out to described encapsulation unit 31 and conductive carrier 32, to make the metal tangent plane 35 all electroplated metal layers 36 exposing to described encapsulation unit 31.In this step, the exposed surface of described conductive carrier 32 is also plated metal level 36, the metal level on described metal tangent plane 35 surface adopts dotted line to illustrate to mark in the drawings, in the step of the described conductive carrier 32 of follow-up removal, described metal level 36 is cut, to retain the metal level on described metal tangent plane 35 surface along this dotted line.
In this embodiment, described metal tangent plane 35 refers to the tangent plane of pin, and in other embodiments, described metal tangent plane 35 comprises the whole metal tangent planes exposing to described encapsulation unit 31.Further, described metal level 36 is identical with the metal material of described encapsulation unit 31 preplating, such as, be metallic gold.
See step S4 and Fig. 5 E, remove described conductive carrier 32, form the encapsulating structure that metal tangent plane 35 plates entirely.Described minimizing technology can adopt the method for stripping, or additive method well known to those skilled in the art.Preferably, described conductive carrier 32 protrudes from described encapsulation unit 31, so that the stripping of described conductive carrier 32.
The conductive carrier that this embodiment makes full use of packaging body framework itself is electroplated, and does not need extra processing procedure can realize metal tangent plane and entirely electroplates, improve reliability; And frame pin can design flexibly and easily.
In the second embodiment of method for packaging semiconductor of the present invention, described carrier is insulating carrier, and the first surface of described packaging body is the one side of described packaging body away from lead frame.See Fig. 6, in the second embodiment of method for packaging semiconductor of the present invention, described method for plating metal comprises the steps: step S60, carries out chemical plating to described encapsulation unit, belongs to make the metal tangent plane overgild exposing to described encapsulation unit; Step S61, remove described insulating carrier, form the encapsulating structure that pin plates entirely.
Fig. 7 A ~ Fig. 7 D is the schematic flow sheet of method for packaging semiconductor second embodiment of the present invention.
See step S1 and Fig. 7 A, provide the packaging body with multiple encapsulation units 71, the first surface 78 of described packaging body is combined with an insulating carrier 72.In this embodiment, two encapsulation units 71 are only schematically enumerated.
Described insulating carrier 72 is UV film, and the first surface of described packaging body is the one side of described packaging body away from lead frame 73.Described insulating carrier 72 one side is fixed on a nonmetal supporter (not indicating in accompanying drawing), and another side is combined with the first surface of described packaging body.In this embodiment, the one side of described insulating carrier 72 is attached in advance has bringing of plastic hoop, to fix and to support described insulating carrier 72.The first surface of described packaging body is attached on insulating carrier 72.
See step S2 and Fig. 7 B, cutting step is carried out to described packaging body, to make described encapsulation unit 71 independent of one another.The cutting of this step does not cut insulating carrier 72, can be connected to make insulating carrier 72 with each encapsulation unit 71.After cutting, the cut surface of the pin of the side of described encapsulation unit 71 and the pin of bottom surface expose.
See step S60 and Fig. 7 C, chemical plating is carried out to described encapsulation unit 71, belong to layer 76 to make metal tangent plane 75 overgild exposing to described encapsulation unit 71.In this embodiment, described metal tangent plane 75 is only the tangent plane of pin, and described pin does not carry out preplating, therefore, described pin exposed in the cut surface of described encapsulation unit 71 and bottom surface all by metal cladding 76.In this embodiment, the metal of chemical plating can be nickel gold.
See step S61 and Fig. 7 D, remove described insulating carrier 72, form the encapsulating structure that pin 75 plates entirely.In this embodiment, if described insulating carrier 72 is UV film, then the method for irradiating ultraviolet light is adopted to remove described insulating carrier 72.
The present invention also provides a kind of packaging body, see Fig. 8, in the first embodiment of packaging body of the present invention, described packaging body comprises multiple being arranged in identical carrier 82 and encapsulation unit independent of each other 81, exposes to the metal tangent plane (unmarked in accompanying drawing) of encapsulation unit 81 described in each all by metal cladding 86.In this embodiment, only schematically enumerating carrier 82 described in two encapsulation units 81 is conductive carrier, and the one side that described conductive carrier 82 has lead frame 83 with described encapsulation unit 81 is connected.Described conductive carrier 82 is the carrier that lead frame 83 has itself, and such as, carbon steel, carries out at lead frame 83 supporting described lead frame 83 in the process of die bond, routing and encapsulation.In this embodiment, the pin covered by conductive carrier 82 of described encapsulation unit 82 bottom surface was plated before being combined with conductive carrier 82.
See Fig. 9, in the second embodiment of packaging body of the present invention, described packaging body comprises multiple being arranged in identical carrier 92 and encapsulation unit independent of each other 91, exposes to the metal tangent plane (unmarked in accompanying drawing) of encapsulation unit 91 described in each all by metal cladding 96.In this embodiment, two encapsulation units 91 are only schematically enumerated.Described carrier 92 is insulating carrier, such as UV film.Described insulating carrier is connected with the one side of described encapsulation unit 91 away from lead frame 93.In this embodiment, the bottom surface of described encapsulation unit 91 and the pin 95 of side are all by metal cladding 96.
See Figure 10, the present invention also provides a kind of encapsulation unit, and described encapsulation unit at least has the metal tangent plane 105 that cutting is formed adjacent two sides, all described metal tangent planes 105 are all coated with the coat of metal 106.In this embodiment, described metal tangent plane 105 is the tangent planes of the multiple pins 103 exposing to described encapsulation unit side.Described encapsulation unit can also comprise plastic-sealed body 100 simultaneously, be placed with the base island 102 of chip 101.Described pin 103 is arranged around described base island 102.Each conductive part on chip 101 is electrically connected with each pin 103 respectively by metal wire 104.Base island 102, chip 101, pin 103 and metal wire 104 plastic packaging in one, all metal tangent planes 105 of all described pins 103 are all coated with coating 106 by described plastic-sealed body 100.In other embodiment of encapsulation unit of the present invention, described metal tangent plane 105 comprises the metal tangent plane of pin, can also comprise the metal tangent plane of other structures of encapsulation unit 31.
In this embodiment, each side of described encapsulation unit is provided with pin 103, and such as, QFN square package, its four sides all have pin, and all metal tangent planes 105 of each pin 103 are all coated with coating 106.Further, coating 106 uniformity of described metal tangent plane 105, as shown in Figure 10, thickness and the material of coating 106 are identical.In other embodiments of encapsulation unit of the present invention, described pin 103 has at least the intersection in two faces to have dividing strip (not indicating in accompanying drawing), and the coating 106 of dividing strip both sides has difference characteristic.Described dividing strip be due at least two faces of pin 103 different time coated coating 106 and producing.Described difference characteristic refers to that the thickness of the coating 106 of dividing strip both sides material that is different or coating 106 is different.
The above is only the preferred embodiment of the present invention; it should be pointed out that for those skilled in the art, under the premise without departing from the principles of the invention; can also make some improvements and modifications, these improvements and modifications also should be considered as protection scope of the present invention.
Claims (17)
1. a method for packaging semiconductor, is characterized in that, comprises the steps:
There is provided the packaging body with multiple encapsulation unit, the first surface of described packaging body is combined with a carrier;
Cutting step is carried out to described packaging body, to make described encapsulation unit independent of one another;
Plating step is carried out, to make the metal tangent plane exposing to described encapsulation unit all by plating to described carrier-bound described encapsulation unit;
Remove described carrier.
2. method for packaging semiconductor according to claim 1, it is characterized in that, described carrier is conductive carrier, the first surface of described packaging body is the one side that described packaging body has lead frame, the method of described plating is: carry out energising plating, to make the whole plated metal of metal tangent plane exposing to described encapsulation unit to described encapsulation unit and conductive carrier.
3. method for packaging semiconductor according to claim 2, is characterized in that, before plating step, deviates from a surface coverage mask of described encapsulation unit at described conductive carrier.
4. the method for packaging semiconductor according to Claims 2 or 3, is characterized in that, described conductive carrier is carbon steel, is the carrier of the lead frame before the encapsulation of described packaging body.
5. the method for packaging semiconductor according to Claims 2 or 3, is characterized in that, before described packaging body is combined with described carrier, also comprises the step of a preplating, for the bare metal plated metal blocked by follow-up for described packaging body loaded body.
6. method for packaging semiconductor according to claim 1, is characterized in that, described carrier is insulating carrier, and the first surface of described packaging body is the one side of described packaging body away from lead frame, and the method for described plating is:
Chemical plating is carried out to described encapsulation unit, belongs to make the metal tangent plane overgild exposing to described encapsulation unit.
7. method for packaging semiconductor according to claim 6, it is characterized in that, after cutting described packaging body, the cut surface of described encapsulation unit lateral leads and the pin of bottom surface expose, in electroless plating step, expose to the metal tangent plane of described encapsulation unit all by plating.
8. method for packaging semiconductor according to claim 6, is characterized in that, described insulating carrier is UV film.
9. method for packaging semiconductor according to claim 8, is characterized in that, described UV film one side is fixed on a nonmetal supporter, and another side is combined with the first surface of described packaging body.
10. method for packaging semiconductor according to claim 8 or claim 9, is characterized in that, in the step removing described insulating carrier, adopts the method for irradiating ultraviolet light to remove described UV film.
11. 1 kinds of packaging bodies, is characterized in that, comprise multiple setting on the same vector and encapsulation unit independent of each other, expose to the metal tangent plane of encapsulation unit described in each all by plating.
12. packaging bodies according to claim 11, is characterized in that, described carrier is arranged on described encapsulation unit and has the one side of lead frame or described carrier is arranged on the one side of described encapsulation unit away from lead frame.
13. 1 kinds of encapsulation units, is characterized in that, described encapsulation unit at least has the metal tangent plane that cutting is formed adjacent two sides, all described metal tangent planes are all coated with the coat of metal.
14. encapsulation units according to claim 13, is characterized in that, each side of described encapsulation unit is provided with pin, and the metal tangent plane of each pin is all coated with the coat of metal.
15. encapsulation units according to claim 13 or 14, is characterized in that, the coat of metal uniformity of each metal tangent plane.
16. encapsulation units according to claim 14, is characterized in that, described pin has at least the intersection in two faces to have dividing strip, and the coat of metal of dividing strip both sides has difference characteristic.
17. encapsulation units according to claim 16, is characterized in that, described difference characteristic is that the thickness of the dividing strip both sides coat of metal is different.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201510874625.5A CN105513976B (en) | 2015-12-02 | 2015-12-02 | Method for packaging semiconductor, packaging body and encapsulation unit |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201510874625.5A CN105513976B (en) | 2015-12-02 | 2015-12-02 | Method for packaging semiconductor, packaging body and encapsulation unit |
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| CN105513976A true CN105513976A (en) | 2016-04-20 |
| CN105513976B CN105513976B (en) | 2018-04-17 |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN106048679A (en) * | 2016-05-30 | 2016-10-26 | 北京首钢微电子有限公司 | Electroplating method of integrated circuit |
| CN110718484A (en) * | 2019-09-24 | 2020-01-21 | 日月光封装测试(上海)有限公司 | Method for separating integrated circuit packages |
| CN113035721A (en) * | 2019-12-24 | 2021-06-25 | 维谢综合半导体有限责任公司 | Packaging process for plating conductive film on side wall |
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| CN110718484A (en) * | 2019-09-24 | 2020-01-21 | 日月光封装测试(上海)有限公司 | Method for separating integrated circuit packages |
| CN113035721A (en) * | 2019-12-24 | 2021-06-25 | 维谢综合半导体有限责任公司 | Packaging process for plating conductive film on side wall |
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| CN105513976B (en) | 2018-04-17 |
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