CN1058109C - 半导体器件 - Google Patents
半导体器件 Download PDFInfo
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- CN1058109C CN1058109C CN96103623A CN96103623A CN1058109C CN 1058109 C CN1058109 C CN 1058109C CN 96103623 A CN96103623 A CN 96103623A CN 96103623 A CN96103623 A CN 96103623A CN 1058109 C CN1058109 C CN 1058109C
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Abstract
一种半导体器件,包括基板,基板上具有安装半导体元件的空腔和在腔的周边上的下降台阶表面,用于在其上边装配片状部件。半导体元件和片状部件易于由导体连到外部电路上。基板上加盖并把密封材料灌注到盖和基板之间的空间中使腔密封,并沿着腔的整个周边延伸的下降台阶表面上使片状部件包封。盖可以包括用于紧靠到下降台阶表面侧壁上的凸出,或者下降台阶表面可包括一个侧壁,侧壁有用于紧靠到盖的周边上的凸出。还可有附加到半导体元件上的散热器。
Description
本发明涉及一种半导体器件,特别涉及具有中空半导体封装半导体器件,在这种封装中,半导体芯片被加盖密封于多层丝焊基板的空腔之内。
图9是用于图示说明现有技术的半导体封装的透视图,图10是图9所示的半导体封装的剖视图。在这些图中,参考标号1是一个半导体芯片,2是铝制或金制细丝,3是用FR4,BT等树脂制作的多层丝焊基板,4是用铅和锡制作的焊球,5是用BT树脂制作的盖、6是用于密封盖5的密封树脂,7是用铜,铜合金等等制作的金属板,8a是一个小电容值的片状陶瓷电容器,8b是一个大电容值的片状电容器,9是用铝、铜等制成的散热片。
在现有的中空式半导体封装中,众多的焊球4在多层丝焊基板3的表面上排列成一个阵列,半导体芯片1和把半导体芯片1与多层丝焊基板3电连起来的金属丝2被放置在多层丝焊基板3中心的空腔内,而且半导体芯片1和金属丝2等等用盖5密封起来。另一方面,在多层丝焊基板3的表面的中心部位上已经形成了用铜、铜合金等等制作的金属板7,用于散发半导体芯片1所产生的热,而金属板7已装附到用铝、铜等制作的散热片9上。
上述讨论过的片状电容器8a和8b对例如消除噪声,为确保超过50MHz的半导体芯片的高速的必不可少的。在现有的半导体器件中,这样的片状电容器,如图10所示,被装配到上面提到过的多层丝焊基板3的表面上。
但是,就如图10所画出的那样,比如说当把一个小电容值的片状电容8a装配到多层丝焊基板3的表面上的时候,不利的是必须把散热片9安装到片状电容器8a的上边,结果作为一个整体半导体器件将形成厚的厚度。当把一个大电容值的片状电容器8b装配到多层丝焊基板3的表面上时,必须把散热片9装配为不和大电容值片状电容器8b冲突,以致于必须把散热片作成小尺寸,故缺点是产生了从半导体芯1上散热不足和散热效率低的问题。此外,如图10所示,当把大电容器值片状电容器8b装配到多层丝焊基板3的表面上时,由于不利的外部环境条件,片状电容器8b可能从多层丝焊基板3上移开。
因此,本发明的主要目的是提供一种消除了现有装置的上述讨论过的缺点的半导体器件。
本发明的另一个目的是提供一种其整体厚度即便是装配上诸如片状电容器的片状部件时也是薄的半导体器件。
本发明的另一个目的是提供一种半导体器件,在这种器件中即便是装配上诸如片状电容器时也可应用尺寸大的散热片。
本发明的再一个目的是提供一种半导体器件,在这种器件中不必担心诸如片状电容器的片状部件从基板上移去。
根据本发明,半导体器件,包括具有一个空腔和一个下降台阶表面的基板,空腔用于在其中装配半导体元件,下降台阶表面在空腔的周边上,用于在其上边装置片状部件;装配在上述空腔中的半导体元件;装配在上述基板上并和上述半导体元件一起工作的片状部件;电连接装置,配置于上述基板上,用于把上述空腔内的上述半导体元件和上述台阶表面上与外部电路有关的上述片状部件电连接;附加到上述基板上的密封装置,用于密封上述空腔内的上述半导体元件,其特征在于:上述片状部件装配到上述基板的上述下降台阶表面上,并由上述密封装置密封。
密封装置可以包括附加到基板上的盖和注入到限定在盖子和基板之间的一空间的密封材料,该材料用于密封空腔和用于包封在下降台阶的表面上的片状部件,上述下降台阶的表面可沿着空腔的整个周边延伸。盖可以包括一个凸出部件,它被用于紧靠下降台阶表面的侧壁上,或者换一种方案,下降台阶表面可以一个侧壁,该侧壁具有用来紧靠盖的周边的凸出部分。导半体器件还包括可以包括附加到半导体元件上去的散热器。
此外,盖还可有一个形成于其中的凹槽,而在基板空腔中的用于把片状部件装配在其上边的下降台阶表面则被定位成与盖的凹槽的平面相对面的位置。
还有一种供选择的方案,基板可以具有已形成于其中的用于在其中装配片状部件的凹部,该凹部被定位于与盖的平面不是对面的位置上。
此外,基板还可以具有已形成于其中的凹部,凹部用于把片状部件装配在其里边,并被定位于基板的空腔之内与盖的平面相对的位置。
在本发明的半导体器件中,片状部件可以是片状电容器。
下边将结合附图详细地说明本发明的最佳实施例,通过下列详细描述本发明就更容易理解了。这些附图是:
图1是本发明的第1实施例的半导体器件的透视图。
图2是本发明的第1实施例的半导体器件的剖视图。
图3是本发明的第2实施例的半导体器件的透视图。
图4是本发明的第2实施例的半导体器件的剖面图。
图5是本发明的第3实施例的半导体器件的透视图。
图6是本发明的第3实施例的半导体器件的剖视图。
图7是一透视图,用于说明本发明的第3实施例的凹部。
图8是本发明的第4实施例的半导体器件的剖视图。
图9是现有技术设计的半导体器件的透视图。
图10是现有技术的半导体器件的剖视图。
图1是本发明的第1实施例的半导体器件的透视图,图2是第1实施例的半导体的剖视图。在这些图中,参考标号1是一个半导体芯片、2是铝丝或金丝,3是例如用FR4或BT树脂制成的多层丝焊基板,4是用铅和锡制作的焊球,5是比如说用BT树脂或陶瓷制作的盖,5a是盖的凸出部分,6是用于包封盖5和片状电容器的密封树脂,6a是使用于盖5的底面上的盖树脂,7是用铜、合金铜等制成的金属板,8b是大电容值的片状陶瓷电容器,9是用铝,铜等制作的散热器或散热片。还有,在这个图中,参考标号10是用诸如金或铜等电导体制成的连接区,它由多层丝焊基板3里边的电源层10a和接地层10b的引线组成,这些连接区10处于下降台阶的表面12上边。下降台阶的表面12是定位于比基板3的顶部表面低一个距离的位置处的基板3的表面,下降距离相当于盖5的厚度与盖5下边粘结剂6a的厚度之和。还有,在该图中,参考标号11是密封部分,用于用密封树脂6把多层丝焊基板3和盖5覆盖起来。
在本实施例中,不带有凸出部分5a的盖5的外侧周边部分,在本发明中相当于盖5的“凹槽”部分。还有,把上边提到过的密封树脂灌注其中的密封部分11和盖5的“凹槽”部分在基板3的厚度的方向上是处于相对立的关系。即,在本实施例中,是用消除盖5的在基板厚度方向上与在其中装配片状电容器8b的区域具有对向关系的那一部分的办法来形成盖5,使得把被消除掉的部分明确表示为“凹槽”。还有,在厚度方向上与在其中装配片状电容器的区域并不处于对向关系的那一部分明确表示为未被开凹槽的凸出部分5a。这些凸出部分5a被用来相对于基板3的空腔精确地定位盖5,用的办法是当盖5被盖上的时候,把它们放在紧靠基板空腔的侧壁表面的地方。
还有,在本实施例中,在把片状电容器装配到其上边的下降台阶的表面上形成了密封部分11,它带有连接区10,连接区10是从多层丝焊基板内部伸展出来的导体。关于把盖5密封到密封部分11上,是将片状电容器8b用一种导电性粘结剂(没有画出来)粘结到降低台阶的表面上边的连接区10上,接着把盖5用盖树脂6a密封,然后片状电容器由密封树脂6包封。在本实施例中,在盖5被密封树脂6包封之前,先用盖树脂6a把盖5密封起来,然后再把片状电容器8b用密封树脂6包封。但是,片状电容器8b也可不用盖树脂6a而用导电性粘结剂(没有画出来)粘结到连接区10上,然后,用密封树脂6把盖5和片状电容器8b包封。
如上所述,根据这个实施例,在基板3的盖5一侧上边装配许多大电容值的片状电容器8b,目的是为使得半导体芯片比如说具有高于50MHz工作频率的足够的速度但半导体封装的多层丝焊基板3的整体尺寸不变大。此外,由于盖5被形成为带有凸出部分5a,盖5相对于基板3易于定位,以防盖5离开正确的位置。再者,由于片状电容器8b完全被密封树脂6覆盖了起来,防止了因外部环境的原因而脱落,增加了可靠性。此外,因为在多层丝焊基板3的表面上不存在与片状部分相冲突的其他部件,故可以使用具有良好的散热效率的大的散热片9。
虽然就如日本专利公报3-225859号(Japanese Patent Laid-Open No.3-225859)所公布的那样,已提出一种在其中片状电容器已形成于基板中的半导体器件,但由于增加了制造基板的工序数目,使这种装置的造价很高。与这样的现有技术的半导体器件相反,作为其目的,本发明关于基板的规定允许在高频工作,在造价方面要和现有技术基板的造价相似。
图3是图示说明本发明的第2实施例的半导体器件的透视图。图4是示于图3的半导体器件的剖视图。这些图中,参考标号1是半导体芯片,2是铝制或金制压焊丝,3是用FR4或BT树脂等制作的多层丝焊基板,4是用铅和锡制作的焊球,5是用BT树脂或陶瓷制作的盖,6是把盖5和片状电容器包封的密封树脂,7是用铜或铜合金制作的金属板、8b是大电容值的陶瓷片状电容器、9中用铝、铜等制作的热沉或者散热片、11是下降台阶表面12的密封部分,在这一部分中,用密封树脂6把多层丝焊基板3和盖5覆盖起来,11a是形成于密封部分11中的凹部或者埋头孔(CounterSink)。在本实施例中,密封部分11是不和盖5的平面对向的部分。在本实施例中,用诸如金、铜等异体制成的连接区10形成于密封部分11的凹部11a之内,所用的方法是把多层丝焊基板3里边的电源层10a和接地层10b的引线延伸过来。
在本实施例中,当把盖5密封到密封部分11上去的时候,首先用导电性粘结剂(没有画出来)把片状电容器8b粘结到连接区10上,之后,把盖5和多个片状电容器8b用密封树脂6覆盖起来。
根据本实施例,像已经讲述过的那样,密封部分11被形成为带有凹部11a而且大电容值的片状电容器8b被装配到这些凹部11a中的连接区10上。因此,就像在第1实施例中那样,可以维持芯片的高速运行(高于50MHz的工作频率),而且半导体封装的多层丝焊基板3的外部形状不变大,此外,由于盖5的形状可以和现有设计的盖的形状相同。故造价不会增加,再者,由于片状电容器8b完全被密封树脂6覆盖了起来,故它们不会由于外力或环境的原因而从基板3上脱落下来。
虽然其上装配有片状电容器8b的连接区10被布置在密封部分11的凹部11a里边,而且这些凹部被形成为这样一种凹部,它从基板3的空腔的中空部分连续延展,但本发明却不受限于这种构造,片状部件所装配到其上的连接区也可以形成于一个凹下去的部分之内,这个凹下去的部分与空腔无关地形成于基板3的盖密封端的表面内。
图5是一透视图,用于图示说明本发明的第3实施例的半导体装置,图6是图5的半导体装置的剖面图。在这些图中,参考标号1是半导体芯片、2是铝制或金制焊丝,3是用FR4或BT树脂等制成的多层丝焊基板,4是用铅和锡制成的焊球,5是用BT树脂或陶瓷制成的盖、6a是用于密封盖5的盖树脂,7是用铜或铜合金制成的金属板、8b是大电容值陶瓷片状电容、9是用铝、铜等制成的散热片,10是用诸如金或铜等导体制成的连接区,11是一密封部分,在这一部分中,多层丝焊基板3和盖5被覆盖了起来。11b是一些凹部或者埋头孔,它们形成于多层丝焊基板3的密封部分11中与盖5平面相对的部分的较低下层表面内。即,如图7所示,这些凹部11b形成于基板3的密封部分11中,作为凹下的部分延伸到基板3的空腔内盖5所装配到的部位的较低下层的地方。
在本实施例中,盖5把用于装配片状电容器8b的整个部位都覆盖起来。片状电容器8b装配到其上的密封部分11带有许多凹部11b,这些凹部延伸到多层丝焊基板3的较低下层上去。密封部分上还配置有连接区10,连接区10是多层丝焊基板3中导体的延伸。连接区10采用把多层丝焊基板3里边的电源层10a和接地层10b的引线延伸出来的办法形成。
当把盖5密封到本实施例的密封部分11上去的时候,首先用导电粘结剂把片状电容器粘结到连接区10上去(粘结剂没画出来),然后用盖树脂6a盖5和多个片状电容器8b覆盖起来。
根据本实施例,像已经讲述过的那样,则密封部分11带有若干凹部11b,这些凹部11b伸展到多层丝焊基板3的较低下层的表面上,片状电容器8b被装配到这些凹部里边。因此,就像在第1实施例中那样,可以维持芯片在高于50MHz的工作频率的高速运作,同时,半导体封装的多层丝焊基板3的外部构造也不会变大。此外,由于盖5的形状可以作得与现有设计的形状相同,故造价也不会增加。再者,由于片状电容器8b完全被盖树脂6a盖了起来,故它们不会因外力或环境而从基板上脱落。
图8图示出了本发明的半导体器件的第4实施例。在图8中,那些和示于图6中的相同或相当的部分都标以相同的参考标号。这在实施例中,用密封树脂6把盖5密封到多层丝焊基板3的盖密封端的表面上。还有,在本实施例中,在基板3的腔内与盖5的平面相向的那一部分已在其中形成了和空腔呈连续状态的凹下部分11c,且在这种凹下部分11c中形成了片状电容器8b所装配在其上的一些连接区(没有画出来)。因为在本实施例中盖5被配置于其板3的表面上边。故基板3可以相应地做得薄些。因此,根据本实施例,像在第3实施例中那样,也可减小半导体器件的整体厚度。
如已经讨论过的那样,根据本发明的半导体器件,由于片状部分被装配到连接区上,这些连接区形成在与凹槽的平面相面向的部分中,这些凹槽是用于基板空腔的盖子的,故盖并不是被设置为超过片状部件,结果使得半导体器件的整体厚度减小。此外,由于片状部件被装配在基板的盖密封端表面上而且并不和设于基板最前端表面上的散热片冲突,故不会由于片状部件的存在而给散热片的大小强行施加什么限制。还有,由于片状部件被装配到比盖和基板的最前端表面还低的高度上,故不会受到外力的影响,增加了可靠性。
此外,根据本发明的半导体器件,由于片状部件装配在那些凹部中,凹部形成于不与基板的盖的平面相对面的部分里,故盖平面不与片状部件相向,使得半导体器件的整体尺寸得以做得不大。另外,由于片状部件装配在基板的盖密封端上且不与配置在基板最前端表面的散热片冲突,故不会由于片状部件的存在而对散热尺寸强行加上什么限制。再者,由于片状部件装在低于盖和基板最前端表面的高度上,故它们被保护为不会掉下来,增加了可靠性。
还有,根据本发明的半导体器件,则由于已装配上的片状部件被盖和围绕着盖的密封树脂密封了起来,故这些片状部件完全受到保护使之不会由于外部环境诸如各种机械力的原因而脱落,从而大大地改善了可靠性。
另外,根据本发明的半导体器件,由于那些片状部件装在下述凹部中:这些凹部形成于基板的空腔中与盖的平面相向的部分里,故片状部件在基板平面的方向上与盖并不是冲突的关系,使得半导体装置的整体厚度尺寸是小的。此外,由于片状部件装配在基板的盖密封端且不和配置于基板的最前端表面一侧的散热片冲突,故不会因片状部件的存在而给散热片的尺寸强加上什么限制。还有,由于片状部件装配在低于盖和基板的最前端表面的高度上,故它们被保护为不会掉下来,增加了可靠性。
还有,根据本发明的半导体器件,由于片状部件可以是用来消除噪声的片状电容器,消噪片状电容器的装配不像现有技术的设计中那样把它们装配到基板的最前端表面上,故不使半导体器件的整体厚度增加。另外,由于片状部件装配在基板的盖密封端且不和配置于基板的最前端表面一侧的散热片冲突,故不会因片状部件的存在而给散热片的大小强行加上什么限制。再有,由于片状部件装配在此盖和基板的最前端表面低的高度上,故它们被保护为不受外力影响,增加了可靠性。
Claims (9)
1.一种半导体器件,包括:
具有一个空腔和一个下降台阶表面的基板,空腔用于在其中装配半导体元件,下降台阶表面在空腔的周边上,用于在其上边装置片状部件;
装配在上述空腔中的半导体元件;
装配在上述基板上并和上述半导体元件一起工作的片状部件;
电连接装置,配置于上述基板上,用于把上述空腔内的上述半导体元件和上述台阶表面上与外部电路有关的上述片状部件电连接;
附加到上述基板上的密封装置,用于密封上述空腔内的上述半导体元件,
其特征在于:上述片状部件装配到上述基板的上述下降台阶表面上,并由上述密封装置密封。
2.如权利要求1的半导体器件,其中上述密封装置包括加到上述基板上的盖和一种密封材料,这种材料被灌注到一个限定于盖和基板之间的空间中去,用于密封上述腔体和用于封包在上述下降台阶表面上的上述片状部件。
3.如权利要求1的半导体器件,其中,上述下降台阶表面沿着上述腔体的整个周边伸展。
4.如权利要求1的半导体器件,其中上述密封装置包括加到上述基板上的盖和充填盖和基板之间限定的空间的密封材料,该种材料用于密封上述空腔和用于包封在上述下降台阶表面上的上述片状部件,上述盖包括一个凸出部分,该凸出部分用于紧靠上述台阶表面的侧壁。
5.如权利要求1的半导体器件,其中上述密封装置包括加到上述基板上的盖和基板之间限定的空间的密封材料,用于密封上述空腔和用于包封在上述下降台阶表面的上述片状部件。
6.如权利要求1的半导体器件,还包括一个附加到上述半导体器件上的散热器。
7.如权利要求1的半导体器件,其中上述盖具有形成于其上的凹槽,而且在基板的空腔中用于把上述片状部件装配在其上的上述下降台阶表面被定位成与上述盖的凹槽的平面相对。
8.如权利要求1的半导体器件,其中在上述基板具有其上形成的用于装配上述片状部件的凹部,该凹部被定位成不与上述盖的平面相对。
9.如权利要求1的半导体器件,其中上述基板具有其上形成的用于把上述片状部件装配在其中的凹部,其位置在上述基板的上述空腔之内与上述盖的平面相对。
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Families Citing this family (19)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH1154658A (ja) * | 1997-07-30 | 1999-02-26 | Hitachi Ltd | 半導体装置及びその製造方法並びにフレーム構造体 |
JPH11186524A (ja) * | 1997-12-24 | 1999-07-09 | Mitsubishi Electric Corp | 半導体装置およびその製造方法 |
US6753922B1 (en) | 1998-10-13 | 2004-06-22 | Intel Corporation | Image sensor mounted by mass reflow |
CN1225786C (zh) * | 1998-12-21 | 2005-11-02 | 英特尔公司 | 带嵌入式框架的窗口式非陶瓷封装 |
US6890798B2 (en) * | 1999-06-08 | 2005-05-10 | Intel Corporation | Stacked chip packaging |
US6798078B2 (en) * | 2000-12-14 | 2004-09-28 | Yamaha Hatsudoki Kabushiki Kaisha | Power control device with semiconductor chips mounted on a substrate |
US20020127771A1 (en) * | 2001-03-12 | 2002-09-12 | Salman Akram | Multiple die package |
SG95637A1 (en) * | 2001-03-15 | 2003-04-23 | Micron Technology Inc | Semiconductor/printed circuit board assembly, and computer system |
US6441483B1 (en) * | 2001-03-30 | 2002-08-27 | Micron Technology, Inc. | Die stacking scheme |
US6879039B2 (en) * | 2001-12-18 | 2005-04-12 | Broadcom Corporation | Ball grid array package substrates and method of making the same |
US7217597B2 (en) | 2004-06-22 | 2007-05-15 | Micron Technology, Inc. | Die stacking scheme |
JP2006339291A (ja) * | 2005-05-31 | 2006-12-14 | Fujifilm Holdings Corp | 中空パッケージとこれを用いた半導体装置及び固体撮像装置 |
US7539022B2 (en) * | 2005-10-04 | 2009-05-26 | Phoenix Precision Technology Corporation | Chip embedded packaging structure |
JP2007135372A (ja) * | 2005-11-14 | 2007-05-31 | Denso Corp | 車両用交流発電機 |
CN100424863C (zh) * | 2005-11-25 | 2008-10-08 | 全懋精密科技股份有限公司 | 芯片埋入基板的封装结构 |
US7323968B2 (en) * | 2005-12-09 | 2008-01-29 | Sony Corporation | Cross-phase adapter for powerline communications (PLC) network |
DE102006032925B8 (de) * | 2006-07-15 | 2008-11-06 | Schott Ag | Elektronische Baugruppe und Verfahren zur Verkapselung elektronischer Bauelemente und integrierter Schaltungen |
CN105210185A (zh) * | 2013-05-17 | 2015-12-30 | 富士通株式会社 | 半导体装置及其制造方法、以及电子设备 |
EP3465780B1 (en) | 2016-06-07 | 2021-12-22 | Plessey Semiconductors Limited | Light-emitting device and method of manufacture |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5091772A (en) * | 1989-05-18 | 1992-02-25 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device and package |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS59175131A (ja) * | 1983-03-24 | 1984-10-03 | Fuji Electric Co Ltd | 混成集積回路 |
JPS62245663A (ja) * | 1986-04-17 | 1987-10-26 | Nec Corp | 半導体装置 |
JPS63260059A (ja) * | 1987-04-16 | 1988-10-27 | Seiko Epson Corp | 密着型イメ−ジセンサのモジユ−ル構造 |
JPH01114061A (ja) * | 1987-10-27 | 1989-05-02 | Nec Corp | 半導体パッケージ |
JPH03225859A (ja) * | 1990-01-30 | 1991-10-04 | Nec Corp | 半導体パッケージ |
JP2795063B2 (ja) * | 1992-06-10 | 1998-09-10 | 日本電気株式会社 | 混成集積回路装置 |
-
1995
- 1995-03-20 JP JP06043495A patent/JP3471111B2/ja not_active Expired - Fee Related
-
1996
- 1996-01-30 US US08/593,965 patent/US5701033A/en not_active Expired - Fee Related
- 1996-02-08 TW TW085101573A patent/TW307909B/zh not_active IP Right Cessation
- 1996-03-08 KR KR1019960006036A patent/KR100190462B1/ko not_active IP Right Cessation
- 1996-03-18 CN CN96103623A patent/CN1058109C/zh not_active Expired - Fee Related
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5091772A (en) * | 1989-05-18 | 1992-02-25 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device and package |
Also Published As
Publication number | Publication date |
---|---|
CN1138215A (zh) | 1996-12-18 |
KR960035993A (ko) | 1996-10-28 |
TW307909B (zh) | 1997-06-11 |
KR100190462B1 (ko) | 1999-06-01 |
US5701033A (en) | 1997-12-23 |
JPH08264674A (ja) | 1996-10-11 |
JP3471111B2 (ja) | 2003-11-25 |
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