CN106276770A - Substrate, chip of micro-electro-mechanical system and preparation method for chip of micro-electro-mechanical system - Google Patents
Substrate, chip of micro-electro-mechanical system and preparation method for chip of micro-electro-mechanical system Download PDFInfo
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- CN106276770A CN106276770A CN201610863804.3A CN201610863804A CN106276770A CN 106276770 A CN106276770 A CN 106276770A CN 201610863804 A CN201610863804 A CN 201610863804A CN 106276770 A CN106276770 A CN 106276770A
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
- B81B1/00—Devices without movable or flexible elements, e.g. microcapillary devices
- B81B1/002—Holes characterised by their shape, in either longitudinal or sectional plane
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
- B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
- B81C1/00015—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems
- B81C1/00023—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems without movable or flexible elements
- B81C1/00087—Holes
Abstract
The present invention relates to a kind of substrate for chip of micro-electro-mechanical system, chip of micro-electro-mechanical system and preparation method, belong to micromechanics field, this substrate being used for chip of micro-electro-mechanical system includes the wafer body with upper and lower surface and at least one cavity being formed in described wafer body, each described cavity includes sub-chamber portion set up and down and lower sub-chamber portion, described sub-chamber portion connects with lower sub-chamber portion, and described sub-cavity is downwardly extending from the upper surface of described wafer body；Described sub-chamber portion is enclosed sets the shape of formation and/or size is enclosed from described lower sub-chamber portion and set the shape of formation and/or size is different；On the lower surface of described wafer body, the frontal projected area in described sub-chamber portion is more than the frontal projected area in described lower sub-chamber portion.
Description
Technical field
The present invention relates to a kind of substrate for chip of micro-electro-mechanical system, chip of micro-electro-mechanical system and the preparation side of this substrate
Method, belongs to micromechanics field.
Background technology
MEMS (MEMS, Micro-Electro-Mechanical System), also referred to as mems
System, micro-system, micromechanics etc., grow up on the basis of microelectric technique (semiconductor fabrication), merged photoetching,
The high-tech electronic mechanical device of the fabrication techniques such as burn into thin film, LIGA, silicon micromachined, non-silicon micromachined and precision optical machinery processing
Part.
Along with the fast development of semicon industry, silicon via etch technology is more and more important, especially at 3D encapsulation and MEMS
Field, body silicon etching is requisite committed step.At present in silicon via etch technical field, Bosch technique that general is and
Non-Bosch technique, in MEMS field, along with the exact requirements of etching angle, Bosch technique is commonly used.But this technique is also
Have certain limitation, general etching angle more vertical (by this kind of etching mode, once form cavity 1, this cavity 1
Cavity wall is vertical plane 11, such as Fig. 1 a), or bottom being formed slightly larger than top inverted trapezoidal pattern (by this kind of etching mode, one
Secondary formation inverted trapezoidal cavity 2, the cavity wall 21 of this cavity 2 is inclined-plane, such as 1b), or form the top trapezoidal shape slightly larger than bottom
Looks (by this kind of etching mode, once form trapezoid cavity 3, the cavity wall 31 of this cavity 3 is inclined-plane, such as 1c).It addition, this kind
Structure service efficiency is low, and the chip volume of made formation is bigger.
Summary of the invention
It is an object of the invention to provide a kind of substrate for chip of micro-electro-mechanical system, micro electronmechanical by using this to be used for
The made chip formed of the substrate of System on Chip/SoC can increase the density that chip stacks at three-dimensional, and shorten between chip is mutual
Line, contributes to reducing the size etc. of chip.
For reaching above-mentioned purpose, the present invention provides following technical scheme: a kind of substrate for chip of micro-electro-mechanical system, bag
Include the wafer body with upper and lower surface and at least one cavity being formed in described wafer body, each described chamber
Body includes that sub-chamber portion set up and down and lower sub-chamber portion, described sub-chamber portion connect with lower sub-chamber portion, described sub-cavity
It is downwardly extending from the upper surface of described wafer body；Described sub-chamber portion is enclosed sets the shape of formation and/or size and institute
State lower sub-chamber portion and enclosed shape and/or the size difference setting formation；On the lower surface of described wafer body, described sub-chamber portion
Frontal projected area more than the frontal projected area in described lower sub-chamber portion.
Further, the axis in described sub-chamber portion is overlapping with the axis in lower sub-chamber portion.
Further, described sub-chamber portion is rounding bench-type structure, and described lower sub-chamber portion is column type.
Present invention also offers a kind of chip of micro-electro-mechanical system, including the above-mentioned substrate for chip of micro-electro-mechanical system.
Present invention also offers the preparation method of a kind of substrate for chip of micro-electro-mechanical system, comprise the steps:
S1: providing wafer body, this wafer body has the upper and lower surface being oppositely arranged；
S2: form sub-chamber portion on the upper surface of described wafer body；
S3: in the formed below lower sub-chamber portion in described sub-chamber portion；The lower sub-cavity of described formation connects with upper sub-cavity；In
On the lower surface of described wafer body, the frontal projected area in described sub-chamber portion is more than the frontal projected area in described lower sub-chamber portion；
Described sub-chamber portion is enclosed to be set the shape of formation and/or size and is enclosed, with described lower sub-chamber portion, shape and/or the size setting formation
Different.
Further, described step S2 specifically includes:
S21: the upper surface at described wafer body coats photoresist；
S22: the photoresist of coating is exposed, develops, to form the first photoresist mask pattern；
S23: according to the first photoresist mask pattern etching wafer body to form upper sub-chamber portion；
S24: remove photoresist；
Further, described step S21 also includes: the lower surface at described wafer body forms etching stop layer.
Further, described step S3 specifically includes:
S31: coat bottom antireflective coating in the upper sub-chamber portion that step S2 is formed；
S32: at the surface-coated photoresist of the bottom antireflective coating formed；
S33: the photoresist of coating is exposed, develops, to form the second photoresist mask pattern；
S34: according to the partial substrate body below the first photoresist mask pattern etching ARC and upper sub-chamber portion
With sub-chamber portion under being formed；
S35: remove photoresist, bottom antireflective coating.
Further, the lower sub-chamber that the axis in the upper sub-chamber portion that described step S2 is formed and described step S3 are formed
The axis in portion is overlapping.
Further, described upper cavity part and the combination of lower sub-chamber portion form cavity, and described sub-chamber portion is rounding bench-type structure,
Described lower sub-chamber portion is column type.
The beneficial effects of the present invention is: owing to the cavity of the substrate for chip of micro-electro-mechanical system of the present invention is by presenting
Lower setting the upper sub-chamber portion connected and lower sub-chamber portion composition, on this sub-chamber portion enclosed set the shape of formation and/or size and under
Sub-chamber portion is enclosed shape and/or the size difference setting formation, and on this, frontal projected area in sub-chamber portion is just being more than lower sub-chamber portion
Projected area, so that applying this to be used for the chip made by the substrate of chip of micro-electro-mechanical system add chip at three-dimensional
The density of stacking, has shortened the interconnection line between chip, contributes to reducing the size of chip；Hinge structure, can be more effective
Realize 3D chip laminate, can produce that structure is more complicated, performance is more powerful, the most cost-efficient chip of micro-electro-mechanical system.
The preparation method of the substrate for chip of micro-electro-mechanical system of the present invention can meet the needs of design diversity, extends
Property strong, may be used in the structures such as silicon via etch, deep silicon hole etching, deep trench comb etching.By by made for this kind of method
After the substrate 40 for chip of micro-electro-mechanical system obtained is applied on chip of micro-electro-mechanical system, chip of micro-electro-mechanical system can be increased and exist
The density of three-dimensional stacking, shortens the interconnection line between chip, reduces the size of chip；Hinge structure, can be more effective
Realize 3D chip laminate, produce that structure is more complicated, performance is more powerful, the most cost-efficient chip and MEMS core
Sheet.
Described above is only the general introduction of technical solution of the present invention, in order to better understand the technological means of the present invention,
And can be practiced according to the content of description, below with presently preferred embodiments of the present invention and coordinate accompanying drawing describe in detail as after.
Accompanying drawing explanation
Fig. 1 a to Fig. 1 c is the structural representation of the substrate for chip of micro-electro-mechanical system of three kinds of prior aries；
Fig. 2 is the structural representation of the substrate for chip of micro-electro-mechanical system shown in one embodiment of the invention；
Fig. 3 is the substrate for chip of micro-electro-mechanical system of deep trench comb；
Fig. 4 is the structural representation of the substrate for chip of micro-electro-mechanical system shown in another embodiment of the present invention；
Fig. 5 is the technological process of the preparation method of the substrate for chip of micro-electro-mechanical system shown in one embodiment of the invention
Figure.
Detailed description of the invention
Below in conjunction with the accompanying drawings and embodiment, the detailed description of the invention of the present invention is described in further detail.Hereinafter implement
Example is used for illustrating the present invention, but is not limited to the scope of the present invention.
The chip of micro-electro-mechanical system of the present invention includes the substrate for chip of micro-electro-mechanical system, refers to Fig. 2, and the present invention one
A kind of substrate 40 for chip of micro-electro-mechanical system shown in preferred embodiment includes having upper surface 41a's and lower surface 41b
Wafer body 41 and at least one cavity 42 being formed in described wafer body 41.Each described cavity 42 includes presenting to be divided into
The upper sub-chamber portion 421 put and lower sub-chamber portion 422, described sub-chamber portion 421 connects with lower sub-chamber portion 422, described sub-cavity 42
Being downwardly extending from the upper surface 41a of described wafer body 41, described sub-chamber portion 421 is enclosed the shape setting formation with described
Lower sub-chamber portion 422 is enclosed the shape difference setting formation.On the lower surface 41b of described wafer body 41, described sub-chamber portion 421
Frontal projected area more than the frontal projected area in described lower sub-chamber portion 422.In the present embodiment, described wafer body 41 can be adopted
With silicon chip (Si).Being provided with one layer of etching stop layer on the lower surface 41b of described wafer body 42, this etching stop layer is two
Silicon oxide (SiO2).The cavity 42 of the present embodiment is through-silicon via structure.Owing to this is for the substrate 40 of chip of micro-electro-mechanical system
Cavity 42 includes that on this, sub-chamber portion 421 is enclosed and sets formation in setting up and down and upper sub-chamber that is that connect portion 421 and lower sub-chamber portion 422
Shape enclosed from lower sub-chamber portion 422 that to set the shape of formation different, and on this frontal projected area in sub-chamber portion 421 more than lower sub-chamber
The frontal projected area in portion 422, so that applying this chip being used for made by the substrate of chip of micro-electro-mechanical system 40 to add core
The density that sheet stacks at three-dimensional, has shortened the interconnection line between chip, contributes to reducing the size of chip；The most existing skill
Art, can more effectively realize 3D chip laminate, can produce that structure is more complicated, performance is more powerful, the most cost-efficient microcomputer
Electricity System on Chip/SoC.Really, when expanded application, the structure of this cavity 42 can also deep silicon hole, deep trench comb (such as Fig. 3) etc. its
His structure.
Described sub-chamber portion 421, lower chamber 42 can be any one in column type, polygonal, rounding bench-type structure,
Wherein, for the ease of manufacturing, this is polygonal be set to regular prism-shaped.On the lower surface 41b of described wafer body 41, son on this
The orthographic projection in sub-chamber portion 422 under the orthographic projection covering in chamber portion 421.In the present embodiment, the axis in described sub-chamber portion 421 with
The axis in lower sub-chamber portion 422 is overlapping.In the present embodiment, the concrete structure of this cavity 42 is: the vertical cross-section shape of this cavity 42
Becoming in bolt arrangement, on it, sub-chamber portion 421 is rounding bench-type structure, and lower sub-chamber portion 422 is column type.Described lower sub-chamber portion 422
Side 423 range of grade be 65-85 degree.
In other embodiments, sub-chamber portion can be made to be enclosed shape and/or the size setting formation as the case may be
Size is enclosed from lower sub-chamber portion sets the shape of formation and/or size is different.Such as: refer to Fig. 4, described sub-chamber portion
421 ' are enclosed the shape setting formation is enclosed with lower sub-chamber portion 422 ' that to set the shape of formation identical, and upper sub-chamber portion 421 ' is enclosed sets formation
Size enclosed from lower sub-chamber portion 422 ' that to set the size of formation different；On the lower surface (non-label) of described wafer body, its
The frontal projected area in upper sub-chamber portion 421 ' is more than the frontal projected area in described lower sub-chamber portion 422 '.Sub-chamber portion 421 ' and lower son on this
Chamber portion 422 ' is six prisms.
Referring to Fig. 5 and combine Fig. 2, a kind of preparation method for the substrate 40 of chip of micro-electro-mechanical system of the present invention includes
Following steps:
S1: providing wafer body 41, this wafer body 41 has the upper surface 41a and lower surface 41b being oppositely arranged；This reality
Executing in example, this substrate is silicon chip (Si).
S2: form sub-chamber portion 421 on the upper surface 41a of described wafer body 41；
S3: in the formed below lower sub-chamber portion 422 in described sub-chamber portion；On the lower surface 41b of described wafer body 41, institute
The orthographic projection stating the orthographic projection in sub-chamber portion 421 and lower sub-chamber portion 422 is least partially overlapped, and described sub-chamber portion 421 is just
Projected area is more than the frontal projected area in described lower sub-chamber portion 422；The lower sub-cavity 42 of described formation connects with upper sub-cavity 42.
Described sub-chamber portion 421 is enclosed the shape setting formation and is enclosed from described lower sub-chamber portion 422 that to set the shape of formation different.Described step
The axis in the lower sub-chamber portion 422 that the axis in the upper sub-chamber portion 421 that S2 is formed is formed with described step S3 is overlapping.Separately
Outward, upper cavity part and the combination of portion 422, lower sub-chamber form cavity 42, and described sub-chamber portion 421 is rounding bench-type structure, described lower sub-chamber
Portion 422 is column type.Under this, side 423 range of grade in sub-chamber portion 422 is 65-85 degree.
Really, in described step S3, can according to the actual requirements, upper sub-chamber portion 421 is enclosed set formation shape and/
Or size enclosed from lower sub-chamber portion 422 and set the shape of formation and/or size is arranged to different.Sub-chamber portion 421 on this,
Lower chamber 42 can be any one in column type, polygonal, rounding bench-type structure.It addition, when expanded application, this cavity
The structure of 42 can also deep other structures such as silicon hole, deep trench comb (such as Fig. 3).
When concrete operations, the upper sub-chamber portion 421 that above-mentioned steps S2, S3 are formed, lower sub-chamber portion 422 can be by any
Technique realizes, and in the present embodiment, on this, sub-chamber portion 421 and portion 422, lower sub-chamber concrete methods of realizing are as follows:
Described step S2 specifically includes:
S21: coat photoresist at the upper surface 41a of described wafer body 41；
S22: the photoresist of coating is exposed, develops, to form the first photoresist mask pattern；
S23: according to the first photoresist mask pattern etching wafer body 41 to form upper sub-chamber portion 421；In the present embodiment,
This etching mode uses RIE (Reactive Ion Etching, reactive ion etching) dry etching.
S24: remove photoresist；
Described step S3 specifically includes:
S31: coat bottom antireflective coating (BARC) in the upper sub-chamber portion 421 that step S2 is formed；
S32: at the surface-coated photoresist of the bottom antireflective coating formed；
S33: the photoresist of coating is exposed, develops, to form the second photoresist mask pattern；
S34: use the anti-lithographic technique of PR (BARC ETCH) to anti-carve erosion ARC according to the first photoresist mask pattern
With the partial substrate body 41 used below the upper sub-chamber portion 421 of inductively coupled plasma (ICP) deep silicon etching process etching with
Sub-chamber portion 422 under formation；
S35: remove photoresist, bottom antireflective coating.
In above-mentioned steps, by using the RIE dry etching adjustable Si etching selection ratio to PR in step S23,
Reach required etching angle, thus realize certain controllability.
In the present embodiment, described step S21 also includes: form etch-stop at the lower surface 41b of described wafer body 41
Only layer.This etching stop layer is silicon dioxide (SiO2).Really, in other embodiments, etching stop layer can be formed without.
Above-mentioned technique can meet the needs of design diversity, and extensibility is strong, may be used on silicon via etch, deep silicon hole is carved
In the structures such as erosion, deep trench comb etching.By the substrate 40 being used for chip of micro-electro-mechanical system obtained by this kind of method is answered
After using on chip of micro-electro-mechanical system, the density that chip of micro-electro-mechanical system stacks at three-dimensional can be increased, shorten between chip
Interconnection line, reduce chip size；Hinge structure, can more effectively realize 3D chip laminate, produce structure more multiple
Miscellaneous, performance is more powerful, the most cost-efficient chip and chip of micro-electro-mechanical system.
Each technical characteristic of embodiment described above can combine arbitrarily, for making description succinct, not to above-mentioned reality
The all possible combination of each technical characteristic executed in example is all described, but, as long as the combination of these technical characteristics is not deposited
In contradiction, all it is considered to be the scope that this specification is recorded.
Embodiment described above only have expressed the several embodiments of the present invention, and it describes more concrete and detailed, but also
Can not therefore be construed as limiting the scope of the patent.It should be pointed out that, come for those of ordinary skill in the art
Saying, without departing from the inventive concept of the premise, it is also possible to make some deformation and improvement, these broadly fall into the protection of the present invention
Scope.Therefore, the protection domain of patent of the present invention should be as the criterion with claims.
Claims (10)
1. the substrate for chip of micro-electro-mechanical system, it is characterised in that: include there is the substrate of upper and lower surface originally
Body and at least one cavity being formed in described wafer body, each described cavity include sub-chamber set up and down portion and
Lower sub-chamber portion, described sub-chamber portion connects with lower sub-chamber portion, described sub-cavity from the upper surface of described wafer body to downward
Stretch formation；Described sub-chamber portion enclosed set the shape of formation and/or size enclosed with described lower sub-chamber portion set formation shape and/
Or size is different；On the lower surface of described wafer body, the frontal projected area in described sub-chamber portion is more than described lower sub-chamber portion
Frontal projected area.
2. the substrate for chip of micro-electro-mechanical system as claimed in claim 1, it is characterised in that the axis in described sub-chamber portion
Line is overlapping with the axis in lower sub-chamber portion.
3. the substrate for chip of micro-electro-mechanical system as claimed in claim 1 or 2, it is characterised in that described sub-chamber portion is
Rounding bench-type structure, described lower sub-chamber portion is column type.
4. a chip of micro-electro-mechanical system, it is characterised in that include as described in any one in claim 1 to 6 for
The substrate of chip of micro-electro-mechanical system.
5. the preparation method for the substrate of chip of micro-electro-mechanical system, it is characterised in that described preparation method includes as follows
Step:
S1: providing wafer body, this wafer body has the upper and lower surface being oppositely arranged；
S2: form sub-chamber portion on the upper surface of described wafer body；
S3: in the formed below lower sub-chamber portion in described sub-chamber portion；The lower sub-cavity of described formation connects with upper sub-cavity；In described
On the lower surface of wafer body, the frontal projected area in described sub-chamber portion is more than the frontal projected area in described lower sub-chamber portion；Described
Upper sub-chamber portion is enclosed sets the shape of formation and/or size is enclosed from described lower sub-chamber portion and set the shape of formation and/or size is different.
6. the preparation method of the substrate for chip of micro-electro-mechanical system as claimed in claim 5, it is characterised in that described step
S2 specifically includes:
S21: the upper surface at described wafer body coats photoresist；
S22: the photoresist of coating is exposed, develops, to form the first photoresist mask pattern；
S23: according to the first photoresist mask pattern etching wafer body to form upper sub-chamber portion；
S24: remove photoresist.
7. the preparation method of the substrate for chip of micro-electro-mechanical system as claimed in claim 6, it is characterised in that described step
S21 also includes: the lower surface at described wafer body forms etching stop layer.
8. the preparation method of the substrate for chip of micro-electro-mechanical system as described in any one in claim 5 to 7, it is special
Levying and be, described step S3 specifically includes:
S31: coat bottom antireflective coating in the upper sub-chamber portion that step S2 is formed；
S32: at the surface-coated photoresist of the bottom antireflective coating formed；
S33: the photoresist of coating is exposed, develops, to form the second photoresist mask pattern；
S34: according to the partial substrate body below the first photoresist mask pattern etching ARC and upper sub-chamber portion with shape
Sub-chamber portion under one-tenth；
S35: remove photoresist, bottom antireflective coating.
9. the preparation method of the substrate for chip of micro-electro-mechanical system as claimed in claim 5, it is characterised in that described step
The axis in the lower sub-chamber portion that the axis in the upper sub-chamber portion that S2 is formed is formed with described step S3 is overlapping.
10. the preparation method of the substrate for chip of micro-electro-mechanical system as described in claim 5 or 9, it is characterised in that described
Upper cavity part and the combination of lower sub-chamber portion form cavity, and described sub-chamber portion is rounding bench-type structure, and described lower sub-chamber portion is column type.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106449397A (en) * | 2016-10-09 | 2017-02-22 | 苏州工业园区纳米产业技术研究院有限公司 | Etching method for forming nut-shaped through-silicon via |
| CN109956446A (en) * | 2019-03-08 | 2019-07-02 | 武汉耐普登科技有限公司 | A kind of step structure and its manufacturing method |
| CN111473805A (en) * | 2020-04-17 | 2020-07-31 | 江苏多维科技有限公司 | Micro-electro-mechanical environment sensor and preparation method thereof |
Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0268021A2 (en) * | 1986-11-17 | 1988-05-25 | Motorola, Inc. | Sloped contact etch process |
| US4984039A (en) * | 1985-05-03 | 1991-01-08 | Texas Instruments Incorporated | Tapered trench structure and process |
| US6818564B1 (en) * | 2001-12-20 | 2004-11-16 | Analog Devices, Inc. | Method for etching a tapered bore in a silicon substrate, and a semiconductor wafer comprising the substrate |
| WO2004112119A1 (en) * | 2003-06-13 | 2004-12-23 | Sumitomo Precision Products Co., Ltd. | Method and apparatus for etching silicon and etched silicon body |
| JP2007080982A (en) * | 2005-09-13 | 2007-03-29 | Hitachi High-Technologies Corp | Etching method, etching device and method of manufacturing semiconductor device |
| JP2012033580A (en) * | 2010-07-28 | 2012-02-16 | Sumitomo Electric Device Innovations Inc | Semiconductor device and method of manufacturing the same |
| CN103247569A (en) * | 2012-02-14 | 2013-08-14 | 联华电子股份有限公司 | Preparation and structure of TSV (through silicon via) |
| CN105590843A (en) * | 2014-11-17 | 2016-05-18 | 北京北方微电子基地设备工艺研究中心有限责任公司 | Method for etching inclined hole |
| CN206126834U (en) * | 2016-09-29 | 2017-04-26 | 苏州工业园区纳米产业技术研究院有限公司 | A substrate and micro -electro -mechanical system chip for micro -electro -mechanical system chip |
-
2016
- 2016-09-29 CN CN201610863804.3A patent/CN106276770A/en not_active Withdrawn
Patent Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4984039A (en) * | 1985-05-03 | 1991-01-08 | Texas Instruments Incorporated | Tapered trench structure and process |
| EP0268021A2 (en) * | 1986-11-17 | 1988-05-25 | Motorola, Inc. | Sloped contact etch process |
| US6818564B1 (en) * | 2001-12-20 | 2004-11-16 | Analog Devices, Inc. | Method for etching a tapered bore in a silicon substrate, and a semiconductor wafer comprising the substrate |
| WO2004112119A1 (en) * | 2003-06-13 | 2004-12-23 | Sumitomo Precision Products Co., Ltd. | Method and apparatus for etching silicon and etched silicon body |
| JP2007080982A (en) * | 2005-09-13 | 2007-03-29 | Hitachi High-Technologies Corp | Etching method, etching device and method of manufacturing semiconductor device |
| JP2012033580A (en) * | 2010-07-28 | 2012-02-16 | Sumitomo Electric Device Innovations Inc | Semiconductor device and method of manufacturing the same |
| CN103247569A (en) * | 2012-02-14 | 2013-08-14 | 联华电子股份有限公司 | Preparation and structure of TSV (through silicon via) |
| CN105590843A (en) * | 2014-11-17 | 2016-05-18 | 北京北方微电子基地设备工艺研究中心有限责任公司 | Method for etching inclined hole |
| CN206126834U (en) * | 2016-09-29 | 2017-04-26 | 苏州工业园区纳米产业技术研究院有限公司 | A substrate and micro -electro -mechanical system chip for micro -electro -mechanical system chip |
Non-Patent Citations (1)
| Title |
|---|
| 格迪斯: "《MEMS材料与工艺手册》", 31 March 2014 * |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106449397A (en) * | 2016-10-09 | 2017-02-22 | 苏州工业园区纳米产业技术研究院有限公司 | Etching method for forming nut-shaped through-silicon via |
| CN109956446A (en) * | 2019-03-08 | 2019-07-02 | 武汉耐普登科技有限公司 | A kind of step structure and its manufacturing method |
| CN111473805A (en) * | 2020-04-17 | 2020-07-31 | 江苏多维科技有限公司 | Micro-electro-mechanical environment sensor and preparation method thereof |
| CN111473805B (en) * | 2020-04-17 | 2021-09-21 | 江苏多维科技有限公司 | Micro-electro-mechanical environment sensor and preparation method thereof |
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