CN106611714A - 半导体装置及其制造方法 - Google Patents

半导体装置及其制造方法 Download PDF

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Publication number
CN106611714A
CN106611714A CN201610494987.6A CN201610494987A CN106611714A CN 106611714 A CN106611714 A CN 106611714A CN 201610494987 A CN201610494987 A CN 201610494987A CN 106611714 A CN106611714 A CN 106611714A
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China
Prior art keywords
insert
reinforcement feature
semiconductor die
primer
semiconductor packages
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CN201610494987.6A
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CN106611714B (zh
Inventor
金阳瑞
杜旺朱
李吉弘
张民华
金东和
李旺求
黄金良
崔美京
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Imark Technology Co
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Imark Technology Co
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Priority to CN202211499517.0A priority Critical patent/CN115719711A/zh
Publication of CN106611714A publication Critical patent/CN106611714A/zh
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Abstract

半导体装置及其制造方法。一种半导体封装及一种其制造方法，所述半导体封装及其制造方法能够减小所述半导体封装的大小并且提高产品可靠性。在非限制性实例实施例中，所述方法可以包括在晶片上形成插入件，在所述插入件上形成至少一个加固部件，将至少一个半导体裸片耦合且电连接到所述插入件，用底胶填充所述半导体裸片与所述插入件之间的区域，并且使用包封物包封所述插入件上的所述加固部件、所述半导体裸片和所述底胶。

Description

半导体装置及其制造方法
相关申请/以引用的方式并入的申请的交叉引用
本申请引用、主张2015年10月22日在韩国知识产权局递交的且标题为“用于制造半导体封装的方法以及使用所述方法的半导体封装(METHOD FOR FABRICATINGSEMICONDUCTOR PACKAGE AND SEMICONDUCTOR PACKAGE USING THE SAME)”的第10-2015-0147395号韩国专利申请的优先权并主张所述韩国专利申请的权益，所述韩国专利申请的内容在此以全文引入的方式并入本文中。
技术领域
本发明涉及半导体装置及其制造方法。
背景技术
当前用于形成感测器装置(例如，指纹感测器装置)的半导体封装和方法并不适当，例如，会导致感测准确性和/或装置可靠性不足、可制造性问题、装置比需要的更厚、装置难以整合到其它产品中和/或整合到其它产品中的成本高、等等。通过比较常规和传统方法与如在本申请的其余部分中参考图式阐述的本发明，所属领域的技术人员将显而易见此类方法的另外的限制和缺点。
发明内容
本发明的各种方面提供一种半导体封装及一种其制造方法，所述半导体封装及其制造方法能够减小半导体封装的大小并且能够提高产品可靠性。在非限制性实例实施例中，所述方法可以包括在晶片上形成插入件，在插入件上形成至少一个加固部件，将至少一个半导体裸片耦合且电连接到插入件，用底胶填充半导体裸片与插入件之间的区域，并且使用包封物包封插入件上的加固部件、半导体裸片和底胶。
附图说明
图1是示出根据本发明的实施例的用于制造半导体封装的方法的流程图；
图2A到2K是示出图1中所示的用于制造半导体封装的方法的横截面图；
图3是示出根据本发明的另一实施例的用于制造半导体封装的方法的流程图；
图4A到4C是示出图3中所示的用于制造半导体封装的方法的横截面图；
图5是示出在根据本发明的用于制造半导体封装的方法中形成加固部件的步骤的另一实施例的平面图；以及
图6是示出在根据本发明的用于制造半导体封装的方法中形成加固部件的步骤的又另一实施例的平面图。
具体实施方式
以下论述通过提供实例来呈现本发明的各种方面。此类实例是非限制性的，并且由此本发明的各种方面的范围应不必受所提供的实例的任何特定特征限制。在以下论述中，短语“例如”和“示例性”是非限制性的且通常与“借助于实例而非限制”、“例如且不加限制”等等同义。
如本文中所使用，“和/或”意指通过“和/或”联结的列表中的项目中的任何一个或多个。作为一实例，“x和/或y”意指三元素集合{(x),(y),(x,y)}中的任何元素。换句话说，“x和/或y”意指“x和y中的一个或两个”。作为另一实例，“x、y和/或z”意指七元素集合{(x),(y),(z),(x,y),(x,z),(y,z),(x,y,z)}中的任何元素。换句话说，“x、y和/或z”意指“x、y和z中的一个或多个”。
本文中所使用的术语仅出于描述特定实例的目的，且并不意图限制本发明。如本文中所使用，除非上下文另外明确指示，否则单数形式也意图包含复数形式。将进一步理解，术语“包括”、“包含”、“具有”等等当在本说明书中使用时，表示所陈述特征、整体、步骤、操作、元件和/或组件的存在，但是不排除一个或多个其它特征、整体、步骤、操作、元件、组件和/或其群组的存在或添加。
将理解，虽然术语“第一”、“第二”等可在本文中用于描述各种元件，但这些元件不应受这些术语限制。这些术语仅用于将一个元件与另一元件区分开来。因此，例如，在不脱离本发明的教示内容的情况下，下文论述的第一元件、第一组件或第一部分可被称为第二元件、第二组件或第二部分。类似地，各种空间术语，例如“上部”、“下部”、“侧部”等等，可以用于以相对方式将一个元件与另一元件区分开来。然而，应理解，组件可以不同方式定向，例如，在不脱离本发明的教示内容的情况下，半导体装置可以侧向转动使得其“顶部”表面水平地朝向且其“侧部”表面垂直地朝向。
在图式中，为了清楚起见可以放大层、区域和/或组件的厚度或大小。相应地，本发明的范围应不受此类厚度或大小限制。另外，在图式中，类似参考标号可以在整个论述中指代类似元件。
此外，应理解，当元件A被提及为“连接到”或“耦合到”元件B时，元件A可以直接连接到元件B或间接连接到元件B(例如，可以在元件A与元件B之间放置插入元件C(和/或其它元件))。
本发明的某些实施例涉及一种用于制造半导体封装的方法以及一种使用所述方法的半导体封装。
近来，例如蜂窝式电话或智能电话等移动通信终端，或例如平板电脑、MP3播放器或数码相机等小型电子装置已经发展为尺寸更小且重量更轻。随着这种趋势，构成小型电子装置的半导体封装正变得更小且更轻。
为了适应各种半导体裸片并且获得高密度再分布层(或结构)，半导体封装采用插入件(或衬底)。由于插入件通常包含穿过硅衬底的硅直通孔(TSV)，因此制造过程可能变得复杂且可能增加制造成本。另外，由于插入件与半导体裸片之间以及插入件与包封物之间的热膨胀系数差别可能导致出现翘曲现象。
本发明提供一种用于制造半导体封装的方法以及使用所述方法的半导体封装，其能够减小半导体封装的大小并且能够提高产品可靠性。
将在优选实施例的以下描述中描述或从以下描述中清楚本发明的上述和其它目的。
根据本发明的方面，提供一种用于制造半导体封装的方法，所述方法包含在晶片上形成插入件，在插入件上形成至少一个加固部件，将至少一个半导体裸片附接到插入件裸片上以使所述至少一个半导体裸片电连接到插入件，用底胶填充半导体裸片与插入件之间的区域，并且使用包封物包封插入件上的加固部件、半导体裸片和底胶。
根据本发明的方面，提供一种半导体封装，所述半导体封装包含：插入件；在插入件上形成的至少一个加固部件；在插入件上形成的待电连接到插入件的至少一个半导体裸片；填充半导体裸片与插入件之间的区域的底胶；以及包封插入件上的加固部件、半导体裸片和底胶的包封物。
如上文所描述，在根据本发明的用于制造半导体封装的方法和使用所述方法的半导体封装中，由于加固部件可以形成于插入件上以防止填充插入件与半导体裸片之间的区域的底胶流至插入件的侧面，由此减小了半导体封装的大小并且提高了产品可靠性。
另外，在根据本发明的用于制造半导体封装的方法和使用所述方法的半导体封装中，由于加固部件和底胶形成于插入件上，因此有可能抑制由于插入件与半导体裸片之间以及插入件与包封物之间的热膨胀系数差别而导致出现翘曲现象。
现将详细参考本发明的当前实施例，在附图中说明所述实施例的实例。
本发明的各种方面可以许多不同形式实施且不应理解为受限于在本文中所阐述的实例实施例。实际上，提供本发明的这些实例实施例是为了使本发明将为充分且完整的，并且将向所属领域的技术人员传达本发明的各种方面。
在图式中，为了清楚起见而放大了层和区域的厚度。此处，类似参考标号通篇指代类似元件。如本文中所使用，术语“和/或”包含相关联的所列项目中的一个或多个的任何和所有组合。
另外，本文中所使用的术语仅仅是出于描述特定实施例的目的而并不意图限制本发明。如本文中所使用，除非上下文另外明确指示，否则单数形式也意图包含复数形式。将进一步理解，术语“包括”当在本说明书中使用时，表示所陈述特征、数目、步骤、操作、元件和/或组件的存在，但是不排除一个或多个其它特征、数目、步骤、操作、元件、组件和/或其群组的存在或添加。
图1是示出根据本发明的实施例的用于制造半导体封装的方法的流程图，并且图2A到2K是示出图1中所示的用于制造半导体封装的方法的横截面图。
如图1所示，根据本发明的实施例的用于制造半导体封装的方法包含以下步骤：形成插入件(S1)、形成加固部件(S2)、附接半导体裸片(S3)、用底胶进行填充(S4)、包封(S5)、形成导电凸块(S6)以及形成屏蔽层(S7)。现将参考图2A到2K详细地描述图1的各个步骤。
在形成插入件(S1)时，在晶片10上形成插入件110。如图2A所示，插入件110包含多层再分布层111(或再分布结构)和覆盖再分布层111的钝化层112。具体来说，如图2B(图2B是图2A的部分A的放大视图)所示，在形成插入件(S1)时，在晶片10上形成第一再分布层111a(或导电层)并且由第一钝化层112a(或介电层)覆盖第一再分布层111a的一部分。接着，进一步形成电连接到第一再分布层111a的第二再分布层111b(或导电层)，并且由第二钝化层112b(或介电层)覆盖第二再分布层111b的一部分。另外，进一步形成电连接到第二再分布层111b的第三再分布层111c(或导电层)，并且由第三钝化层112c(或介电层)覆盖第三再分布层111c的一部分，由此完成实例插入件110。此处，第三再分布层111c暴露于插入件110的顶表面。虽然在图2A到2C中示出了具有三层的再分布层111，但是再分布层111的层的数目可以多于或少于三个。另外，晶片10可以由硅(Si)、玻璃或金属制成，但本发明的各方面并不限于此。
可以通过无电电镀、电镀和/或溅镀由选自由铜、铝、金、银、钯及其等效物组成的群组中的一种材料制成再分布层111(或其导电层)，但本发明的各方面并不限于此。另外，可以使用一般光刻胶通过光刻法执行再分布层111(或其导电层)的图案化或布线，但本发明的各方面并不限于此。
钝化层112(或介电层)可以由选自由聚合物(例如聚酰亚胺、苯并环丁烯、或聚苯并恶唑，及其等效物)组成的群组的一种材料制成，但本发明的各方面并不限于此。另外，可以通过选自由旋涂、喷涂、浸涂、棒涂及其等效物组成的群组的一种方法形成钝化层112，但本发明的各方面并不限于此。
另外，可以通过在晶片10的制造过程(或工厂)期间供应形成于晶片10上的再分布层111的一部分并且在封装过程(或工厂)期间另外在所述一部分上形成再分布层111来完成插入件110。因此，由于插入件110实现较细线宽(小于100μm)和较细间距互连，所以可以实现高密度互连。这种类型的插入件110可以(例如)被称为无硅集成模块(SLIM)插入件。另外，可以通过在晶片10的制造过程(或工厂)期间仅供应晶片10并且在封装过程(或工厂)期间在晶片10上形成再分布层111(或再分布结构)来制造插入件110。这种类型的插入件110可以(例如)被称为硅晶片集成扇出技术(SWIFT)插入件。又例如，插入件110可以是印刷电路板(PCB)。
在形成加固部件(S2)时，在插入件110上形成加固部件120。如图2C所示，加固部件120为柱形或壁形，安置为大体上垂直于插入件110并且形成于插入件110的边缘处。加固部件120可以由具有高电导率和热导率的导电材料(例如，选自铜(Cu)或其等效物的一种材料)或具有高热导率的塑料材料制成，但本发明的各方面并不限于此。
如图2D所示，可以在使用晶片10的过程期间以矩阵配置在晶片10上形成加固部件120。具体来说，在用于锯切晶片10以形成单个的半导体封装的锯切线上形成加固部件120。因此，实例加固部件120形成为完全包围插入件110的边缘，由此形成安装有(稍后将描述的)半导体裸片130的接纳空间S(或裸片空间或组件空间)。
在附接半导体裸片(S3)时，将半导体裸片130附接到插入件110上。首先，如图2E所示，在附接半导体裸片(S3)时，在暴露于插入件110的顶表面的再分布层111上形成导电垫131。因此，导电垫131电连接到再分布层111(或再分布结构)。另外，可以在形成插入件(S1)之前形成导电垫131或可以在形成加固部件(S2)时与加固部件120一起形成导电垫131。导电垫131可以由选自由铜、铝、金、银、钯及其等效物组成的群组中的一种材料制成，但本发明的各方面并不限于此。另外导电垫131可以通过溅镀、真空沉积或光刻法形成，但本发明的各方面并不限于此。
接着，如图2F所示，在附接半导体裸片(S3)时，将半导体裸片130电连接到导电垫131。例如，将半导体裸片130的导电凸块132通过焊料133电连接到导电垫131。例如，可以使用质量回流工艺、热压工艺或激光粘结工艺将半导体裸片130电连接到导电垫131。可以使用选自金属材料(例如，铅/锡(Pb/Sn)或无铅Sn及其等效物)的一种材料形成焊料133，但本发明的各方面并不限于此。
另外，半导体裸片130可以包含(例如)电路，例如数字信号处理器(DSP)、微处理器、网络处理器、功率管理处理器、音频处理器、RF电路、无线基带片上系统(SoC)处理器、传感器或专用集成电路(ASIC)。
在用底胶进行填充(S4)时，底胶140填充插入件110与半导体裸片130之间的区域。如图2G所示，底胶140填充插入件110的顶表面与半导体裸片130的底表面之间的区域，接着进行固化。底胶140保护凸块粘结部分在半导体封装制造过程期间免受例如机械冲击或腐蚀等外来因素影响。此处，底胶140可以由选自由以下组成的群组的一种材料制成：环氧树脂、热塑性材料、热可固化材料、聚酰亚胺、聚氨酯、聚合材料、填充环氧树脂、填充热塑性材料、填充热可固化材料、填充聚酰亚胺、填充聚氨酯、填充聚合材料、熔剂底胶，及其等效物，但本发明的各方面并不限于此。
另外，底胶140完全覆盖插入件110的顶表面并且被设置为与加固部件120的一个侧表面接触。因此，底胶140可以借助于加固部件120而不流至插入件110的侧面。也就是说，加固部件120可以充当阻挡层以用于在用底胶140进行填充时防止底胶140流动。
另外，由于底胶140形成于插入件110与半导体裸片130之间同时完全覆盖插入件110的顶表面，因此有可能抑制由于插入件110与半导体裸片130之间以及插入件110与包封物150之间的热膨胀系数差别而导致出现翘曲现象。
在包封(S5)时，使用包封物150包封插入件110的顶部。如图2H所示，在包封(S5)时，使用包封物150包封安装在插入件110上的加固部件120、半导体裸片130和底胶140。包封物150完全包封加固部件120、半导体裸片130和底胶140，由此保护加固部件120、半导体裸片130和底胶140免受因外部冲击和氧化而导致损坏。包封物150可以由选自由以下组成的群组的一种材料制成：用于一般传递模塑的热可固化环氧模塑化合物、用于调剂的室温可固化包封胶，及其等效物，但本发明的各方面并不限于此。此处，包封物150与插入件110的顶表面间隔开而不与插入件110的顶表面直接接触。
虽然未示出，但是可以通过磨削将包封物150的顶表面的不必要的部分去除掉预定厚度。此处，可以使用例如金刚石磨削机或其等效物执行磨削，但本发明的各方面并不限于此。
在形成导电凸块(S6)时，移除置于插入件110下的晶片10并且在插入件110下形成导电凸块160。首先，如图2I所示，在形成导电凸块(S6)时，移除置于插入件110下的晶片10。例如，可以通过一般磨削过程移除晶片10。因此，再分布层111(例如，第一再分布层或导电层)暴露于插入件110的底表面。接着，如图2J所示，在形成导电凸块(S6)时，在暴露于插入件110的底表面的再分布层111上形成导电凸块160。此处，可以在暴露于插入件110的底表面的再分布层111上形成凸点下金属(UBM)并且可以在所述UBM上形成导电凸块160。UBM可以通过防止在导电凸块160与再分布层111之间形成金属间化合物来提高导电凸块160的板级可靠性。
导电凸块160可以由选自但不限于以下的材料制成：共晶焊料(例如，Sn37Pb)、具有高熔点的高铅焊料(例如，Sn95Pb)、无铅焊料(例如，SnAg、SnCu、SnZn、SnZnBi、SnAgCu和SnAgBi)，及其等效物。
接着，虽然未示出，但是执行锯切过程以形成由至少一个半导体裸片130和对应于安置在接纳空间S(或裸片空间或组件空间)中的所述至少一个半导体裸片的加固部件120组成的单一单元，由此制造根据本发明的实施例的半导体封装100。此处，可以使用锯切设备(例如，钢锯条或激光束)执行锯切过程。
在形成屏蔽层(S7)时，在包封物150的表面上形成屏蔽层170。在形成屏蔽层(S7)时，如图2K所示，形成屏蔽层170以覆盖包封物150的整个表面和加固部件120的至少一部分。例如，可以通过使用喷涂或溅镀在包封物150的表面上涂布混合导电金属粉末的导电浆料来形成屏蔽层170，但本发明的各方面并不限于此。
此处，当形成屏蔽层170时，加固部件120可以由导电金属制成，同时其一端优选地接地。因此，可以通过屏蔽层170屏蔽由包封物150中的至少一个半导体裸片130产生的电磁波以免散射到外部，并且也可以通过屏蔽层170屏蔽外部施加的电磁波以免穿透到包封物150中的至少一个半导体裸片130中。
图3是示出根据本发明的另一实施例的用于制造半导体封装的方法的流程图，并且图4A到4C是示出图3中所示的用于制造半导体封装的方法的横截面图。
参考图3，根据本发明的另一实施例的用于制造半导体封装的方法包含以下步骤：形成插入件(S11)、形成加固部件(S12)、附接半导体裸片(S13)、用底胶进行填充(S14)、包封(S15)、形成模具直通孔(S16)以及形成导电凸块(S17)。现将参考图4A到4C详细地描述图3的各个步骤。
步骤S11、S12、S13、S14和S15与图1的步骤S1、S2、S3、S4和S5相同，并且示出对应的步骤S11、S12、S13、S14和S15的各图与图2A到2H相同，因此将不进行所述各图的详细描述。
在形成模具直通孔(S16)时，在包封物150中形成模具直通孔(TMV)280。如图4A所示，在形成模具直通孔(TMV)(S16)时，TMV 280穿过介于包封物150的顶表面到插入件110的顶表面的范围内的区域。TMV 280形成于半导体裸片130与加固部件120之间。具体来说，通过以下步骤形成TMV 280：通过(例如)激光钻孔过程形成穿过包封物150的通孔；在通孔的内壁表面上电镀具有高电导率和热导率的导热金属，例如铝(Al)或铜(Cu)；且接着用例如金属浆料等导电材料填充通孔。因此，根据本发明的半导体封装可以容易地通过TMV 280散发由插入件110产生的热量。另外，可以在TMV 280上进一步电堆叠半导体裸片或半导体封装。
在形成导电凸块(S17)时，移除置于插入件110下的晶片10并且在插入件110下形成导电凸块160。首先，如图4B所示，在形成导电凸块(S17)时，移除置于插入件110下的晶片10。例如，可以通过一般磨削过程移除晶片10。因此，再分布层111(例如，第一再分布层或导电层)暴露于插入件110的底表面。接着，如图4C所示，在形成导电凸块(S17)时，在暴露于插入件110的底表面的再分布层111上形成导电凸块160。此处，可以在暴露于插入件110的底表面的再分布层111上形成凸点下金属(UBM)并且可以在所述UBM上形成导电凸块160。UBM可以通过防止在导电凸块160与再分布层111之间形成金属间化合物来提高导电凸块160的板级可靠性。
导电凸块160可以由选自但不限于以下的材料制成：共晶焊料(例如，Sn37Pb)、具有高熔点的高铅焊料(例如，Sn95Pb)、无铅焊料(例如，SnAg、SnCu、SnZn、SnZnBi、SnAgCu和SnAgBi)，及其等效物。
接着，虽然未示出，但是执行锯切过程以形成由至少一个半导体裸片130和对应于安置在接纳空间S(或裸片空间或组件空间)中的所述至少一个半导体裸片的加固部件120组成的单一单元，由此制造根据本发明的另一实施例的半导体封装200。此处，可以使用锯切设备(例如，钢锯条或激光束)执行锯切过程。
图5是示出在根据本发明的用于制造半导体封装的方法中形成加固部件的步骤的另一实施例的平面图。
参考图5，在形成加固部件时，在晶片10上形成加固部件220。在用于锯切晶片10以形成单个的半导体封装的锯切线的拐角处形成加固部件220。因此，加固部件220可以包含彼此间隔开的四个部件。加固部件220可以形成为大体上‘L’形配置，并且包含第一加固部件部分221和垂直于第一加固部件部分221的第二加固部件部分222。此处，第一加固部件部分221形成为垂直于锯切线中的一条线。另外，加固部件220的对应部件形成为彼此间隔开以形成安装有半导体裸片的接纳空间(或裸片空间或组件空间)。在锯切晶片10之后，加固部件220在单一半导体封装的每个拐角处支撑插入件的顶表面，由此防止在半导体制造过程期间出现扭动或翘曲。
图6是示出在根据本发明的用于制造半导体封装的方法中形成加固部件的步骤的又另一实施例的平面图。
参考图6，在形成加固部件时，在晶片10上形成加固部件320。在用于通过锯切晶片10形成单一半导体封装的锯切线的每个拐角处形成加固部件320。因此，加固部件320可以包含彼此间隔开的四个部件。加固部件320可以形成为大体上箭头形配置，并且包含第一加固部件部分321、垂直于第一加固部件部分321的第二加固部件部分322、以及置于第一加固部件部分321与第二加固部件部分322之间的第三加固部件部分323。此处，第一加固部件部分321形成为垂直于锯切线中的一条线。另外，加固部件320的对应部件形成为彼此间隔开以形成安装有半导体裸片的接纳空间S(或裸片空间或组件空间)。在锯切晶片10之后，加固部件320在单一半导体封装的每个拐角处支撑插入件的顶表面，由此防止在半导体制造过程期间出现扭动或翘曲。
虽然已经参考某些支持实施例描述了根据本发明的各种方面的用于制造半导体封装的方法以及使用所述方法的半导体封装，但是所属领域的技术人员应理解，本发明不限于所公开的特定实施例，而是本发明将包含落入所附权利要求书的范围内的所有实施例。
本文中的论述包含展示电子装置的各个部分及其制造方法的众多示意图。为了清楚地示意，这些图并未展示每个实例组合件的所有方面。本文中提供的任何实例组合件和/或方法可以与本文中提供的任何或全部其它组合件和/或方法共享任何或全部特征。
综上所述，本发明的各种方面提供一种半导体封装及一种其制造方法，所述半导体封装及其制造方法能够减小半导体封装的大小并且能够提高产品可靠性。在非限制性实例实施例中，所述方法可以包括在晶片上形成插入件，在插入件上形成至少一个加固部件，将至少一个半导体裸片耦合且电连接到插入件，用底胶填充半导体裸片与插入件之间的区域，并且使用包封物包封插入件上的加固部件、半导体裸片和底胶。虽然已经参考某些方面和实例描述了以上内容，但是所属领域的技术人员应理解，在不脱离本发明的范围的情况下，可以进行各种修改并可以替代等效物。另外，在不脱离本发明的范围的情况下，可以进行许多修改以使特定情况或材料适应本发明的教示。因此，希望本发明不限于所公开的特定实例，而是本发明将包含落入所附权利要求书的范围内的所有实例。

Claims (20)

1.一种用于制造半导体封装的方法，所述方法包括：
在晶片上形成插入件；
在所述插入件上形成至少一个加固部件；
将至少一个半导体裸片耦合且电连接到所述插入件；
用底胶填充所述半导体裸片与所述插入件之间的区域；以及
使用包封物包封所述插入件上的所述加固部件、所述半导体裸片和所述底胶。
2.根据权利要求1所述的方法，其中所述形成所述至少一个加固部件包括在所述插入件的边缘处形成所述至少一个加固部件以形成安装有所述半导体裸片的组件空间的边界。
3.根据权利要求2所述的方法，其中所述至少一个加固部件中的每一个加固部件分别地形成在所述组件空间的对应拐角处，并且包括第一加固部件部分和垂直于所述第一加固部件部分的第二加固部件部分。
4.根据权利要求3所述的方法，其中所述至少一个加固部件中的每一个加固部件包括置于所述第一加固部件部分与所述第二加固部件部分之间的第三加固部件部分。
5.根据权利要求1所述的方法，其中所述至少一个加固部件中的每一个加固部件由导电材料制成。
6.根据权利要求1所述的方法，其中对所述区域进行填充包括用所述底胶完全覆盖所述插入件的顶表面，并且使所述至少一个加固部件的侧表面与所述底胶接触，其中所述至少一个加固部件防止所述底胶流至所述插入件的外侧。
7.根据权利要求1所述的方法，其中所述包封物并不直接接触所述插入件的所述顶表面。
8.根据权利要求1所述的方法，包括在所述包封之后：
将所述晶片从所述插入件移除，并且在所述插入件的与所述半导体裸片相对的一侧上形成导电凸块且将所述导电凸块电连接到所述插入件；以及
锯切所述插入件以形成单个的半导体封装。
9.根据权利要求8所述的方法，包括在所述形成所述导电凸块之后：形成包围所述包封物并且电连接到所述加固部件的屏蔽层。
10.根据权利要求1所述的方法，包括在所述包封之后形成模具直通孔，所述模具直通孔穿过介于所述包封物的顶表面到所述插入件的所述顶表面的范围内的区域。
11.一种半导体封装，包括：
插入件；
至少一个加固部件，在所述插入件上形成；
至少一个半导体裸片，耦合到所述插入件且电连接到所述插入件；
底胶，填充所述半导体裸片与所述插入件之间的区域；以及
包封物，包封所述插入件上的所述加固部件、所述半导体裸片和所述底胶。
12.根据权利要求11所述的半导体封装，其中所述至少一个加固部件置于所述插入件的边缘处以形成安装有所述半导体裸片的组件空间的边界。
13.根据权利要求12所述的半导体封装，其中所述至少一个加固部件中的每一个加固部件分别地形成在所述组件空间的对应拐角处，并且包括第一加固部件部分和垂直于所述第一加固部件部分的第二加固部件部分。
14.根据权利要求13所述的半导体封装，其中所述至少一个加固部件中的每一个加固部件包括置于所述第一加固部件部分与所述第二加固部件部分之间的第三加固部件部分。
15.根据权利要求11所述的半导体封装，其中所述至少一个加固部件中的每一个加固部件由导电材料制成。
16.根据权利要求11所述的半导体封装，其中所述底胶完全覆盖所述插入件的顶表面并且接触所述至少一个加固部件的侧表面，其中所述至少一个加固部件防止所述底胶流至所述插入件的外侧。
17.根据权利要求11所述的半导体封装，其包括包围所述包封物并且电连接到所述加固部件的屏蔽层。
18.根据权利要求11所述的半导体封装，其包括模具直通孔，所述模具直通孔穿过介于所述包封物的顶表面到所述插入件的所述顶表面的范围内的区域，其中所述模具直通孔置于所述半导体裸片与所述加固部件之间。
19.根据权利要求11所述的半导体封装，其进一步包括导电凸块，所述导电凸块在所述插入件的与所述半导体裸片相对的一侧上并且电连接到所述插入件。
20.一种用于制造半导体封装的方法，所述方法包括：
将至少一个半导体裸片耦合且电连接到晶片上的插入件，其中所述插入件包括至少一个加固部件；
用底胶填充所述半导体裸片与所述插入件之间的区域；以及
使用包封物包封所述插入件上的所述加固部件、所述半导体裸片和所述底胶。
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