CN1071525A - 微处理机2倍磁心设计 - Google Patents
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Abstract
一微处理机能有选择地以总线的速度,或者以数
倍总线的速度操作。此微处理机包含有一锁相回路,
以产生微处理机内部操作用的时钟信号和总线上传
送数据操作用的总线时钟信号。本发明使得微处理
机磁心能以与地址/数据总线相同的频率或者为其
二倍的频率运行。
Description
本发明涉及数字计算机中的微处理机的速度领域,具体说,是使得微处理机磁心部分能有选择地以地址/数据母线输入时钟的倍频运行。
一般一计算机系统都包含有微处理机,母线以及其他外围设备。微处理机在计算机系统中对数据进行逻辑操作。母线被微处理机和外围设备用来传输数据、地址及控制信号。外围设备是存储装置,或者输入/输出(I/O)装置等。通常计算机系统中每一组成部分均以同一频率运行(即周波型)。
微处理机具有处理数据的磁心单元。此磁心由中央处理单元(CPU),高速存储器等组成。微处理机利用母线控制器来进行与母线的通讯。因为计算机系统的全部操作均是以相同频率进行的,所以该磁心部分所执行的逻辑操作与计算机系统母线上数据、地址及控制信号的传输均是在同样频率下进行的。母线控制器以对母线产生控制信号来保证这种定时。
磁心单元所执行的一些逻辑操作,如算术运算,需要多个周期才能完成。在进行这些多周期的操作期间,母线保持闲置状态。本发明使磁心单元能以较母线快的速度运行。这样做母线就能较频繁地被用来传送数据,从而使母线的闲置状态减到最小,操作就能进行得较迅速。
在将微处理机改变成以较快速度操作时,这种改变最好能使计算机系统的其余部分尽可能少地变动。这样的话,就仅仅只要将新的微处理机插入计算机系统,而无需更改任何其他的系统硬件(亦即无需全部重新设计印制板)。最好也能最小限度地改进硬件,从而使已有的计算机的利用能由不需新的系统部件即可更新其计算机系统中得到改善,由此避免了巨大的耗费。
为了实现这些要求,本发明提供了一种即能以总线速度运行的、也能比总线速度更快的速度运行的微处理机。本发明使总线的定时规格能在两种模式下均保持相同。用这种方法,对整个计算机系统的改变将最小。
本发明较之先有技术的优点是它能够改变微处理机的设计,使其磁心部分能以母线频率的倍频运行而仅作非常少量设计上的变化。这极大地减小了设计时间。此外采用这种技术,大多数的总线控制逻辑(近似99%)能被设计在仍仅仅以总线速度运行。这种方法也能附加选择逻辑以使得由一单连接插座在快速及慢速运行模式之间作选择。因此,这一单模片的设计就可以通过利用对该选择逻辑插座的布线连接配置,来满足多种型式微处理机的要求。
现在来描述一种能选择以总线速度运行或以比总线速度更快的速度运行的微处理机。该微处理机包括一既能产生用于对微处理机磁心部分运行计时的磁心时钟信号,也能产生用于在计算机总线上对数据传送计时的总线时钟信号。一个开关被连接到时钟发生器,用来把微处理机从正常模式转换到快速模式,及作相反转换。在正常模式下,微处理机以与总线相同的频率运行。在快速模式下,微处理机以成倍于总线频率的速度运行。在现在这一优选实施方案中,该微处理机能以二倍频的快速模式运行。
该微处理机还包括一执行计算机系统数据操作和管理的磁心单元,和一按照总线时钟信号驱动总线上的数据的总线控制器。
在本优选实施方案中,时钟发生器为一个4×锁相环。此锁相环利用一脉冲吸收电路来在快速模式期间对时钟信号作隔一的屏蔽。这就使得能产生频率为磁心时钟信号频率一半的总线时钟信号。在本优选实施例中,该脉冲吸收电路为一与除二电路相结合使用的“与门”。
本发明还包含有一闭锁信号发生器,在总线控制器中产生一闭锁信号。此闭锁信号用来在快速模式中使一信号被屏蔽,以阻止总线控制器执行其在正常模式下的规律性周期转换。
本发明将从下面的详细说明及本发明的优选实施例的附图中将会有较全面的理解。不过不应将本发明局限于这一具体的实施例,而具体实施例仅是用于解释和理解。
图1为对计算机系统结构的说明;
图2为本发明的优选实施方案的微处理机的方框图;
图3为本发明优选实施方案的时钟发生器的电路图;
图4及图5为对本发明优选实施方案的时钟发生器所产生的定时信号的说明。
现在描述一有选择地以与地址/数据线相同频率或较快频率运行的微处理机。在下面的叙述中,为了能彻底了解本发明,对例如信号和门电路等的序号均按数码进行详细说明。但对于熟悉本技术领域的人来说,将很明显,无需这样详细论述亦可实现本发明。在其他情况下,大家熟悉的计算机的操作及组成部件均未作详细说明,以避免造成对本发明的不必要的误解。
首先看图1,其中以方框图表现出本发明的计算机系统的全貌。应看到,虽然图1可用来给予本发明的计算机系统作整体说明,但系统的许多细节并未都列出。在为揭示本发明所需要时,说明书中其他一些图中的另外的细节将用作参照。此外本发明是对照其优选实施例加以说明的;其他所有能为本技术领域一般熟悉人员所理解的实施方案,均为看作是处于后面权利要求的范围之内的。
如图1所示,一可为本发明的优选实施方案所采用的计算机系统,通常包含有:用于信息通讯的总线或其他通讯装置101;与总线101连接用于处理信息的处理装置102;与总线101连接,用于存储所述处理装置102的信息和指令的随机存取存储器(RAM)或其他动态存储装置104(一般称之为主存储器);与总线101连接,用于所述处理装置102存储静态信息和指令的只读存储器(ROM)或其他静态存储装置106;与所述母线101连接用于存储信息和指令的数据存储装置107,例如磁盘和磁盘驱动器;与总线101连接用于向计算机用户显示信息的设备121,例如阴极射线管,液晶显示器等;与总线101连接,用于对所述处理器102传递信息和命令选择,以及用于控制光标运动的包含有字符数码及其他键的字符数码输入设备122。最后,系统还包含有用于提供计算机图像的直观图表的硬拷贝设备123,例如绘图仪或post script打印机。硬拷贝设备123通过总线101与处理机102,主存储器104,静态存储器106及海量存储设备107相连接。
当然,本发明的有些实施方案和应用可能不需要也不包括所有上述部件。例如,在某些实施方案中,可能无需给系统输入信息的键盘及光标控制装置。在另一些实施方案中,可能不必有显示信息的显示设备。
图2示出微处理机的方块图,即本发明优选实施方案所采用的处理器200。处理器200最好采用金属氧化物半导体(MOS)工艺制造的集成电路。处理器200通常包括用来处理数据的磁心单元210,用来控制处理器200与计算机系统(图1)总线通讯的控制器220,及用来提供基本定时及处理器200的内部操作频率的时钟发生器230。
在现在的优选实施方案中,磁心单元210,可以有选择地在计算机系统内以一倍或两倍于总线频率的速度运行。磁心单元210包括用以收集和存储数据值的寄存器211,用来解释逐个指令(从存储器取出)以确定操作单元210的操作的指令译码器212,以及为了执行诸如加、求补、比较、移位、传送等指令操作的算术逻辑单元(ALU)213。此外磁心单元210还包含为了跟踪正在执行程序内目前位置的程序计数器214。通常程序计数器214在执行每一个指令以后加“1”。不过在“跳越”或“转移”指令后,它可能到达一个新值。堆栈指针215和标志位216(进位,零,符号)包含用于作条件转移测试的状态信息。高速缓冲存储器217为快速存取保留最新由存储器取出的数值。这些部分的操作细节,在本技术领域内是众所周知的。
时钟发生器230产生用于处理器200及计算机系统总线运行的时钟信号。也可采用磁心时钟信号和总线时钟信号分开的各自的时钟信号发生器。在本发明的现行优选实施方案中,时钟发生器可有选择地产生为总线频率的一倍(1X)或两倍(2X)的磁心时钟频率。然而,利用本发明的技术也能产生其他倍数总线时钟信号频率的时钟信号。
磁心时钟信号对磁心单元210及总线控制器220执行的操作进行定时控制。在现行优选实施例中,所产生的磁心时钟信号具有相位1(PH1)及相位2(PH2)。总线时钟信号控制计算机系统总线上数据的传送。数据传送以两时钟相位进行。在输出相位时,把数据传送到总线上,而当输入相位时则把数据从总线传送到处理器200内。在现行优选实施例中,时钟发生器230产生的总线时钟信号对应于输出和输入相位的分别为CLKOUT及CLKIN。
在现行优选实施例中,2X磁心时钟信号频率是66MHz,而1X磁心时钟信号频率是33MHz。这些磁心时钟信号控制磁心单元210(图2)及总线控制器220(图2)运行。因此,在当现行优选实施例的2X模式下磁心单元210及总线控制器230以66MHz频率运行。仅仅总线控制器220的一小部分使总线在以33MHz的频率运行。
在1X模式时,总线时钟信号CLKOUT及CLKIN均与磁心时钟信号PH1和PH2相同(仅有很小延迟)。在现行的优选实施例中,所有的信号均是33MHz。在2X模式时,总线时钟信号CLKOUT及CLKIN是33MHz时钟信号,占空比是其周期的1/4,分别与每间隔一个的PH1和PH2磁心时钟信号同步。因为这些被同步的总线时钟信号送到决定总线的全部的运行速度的控制器220,而这些总线时钟信号是磁心时钟信号频率的一半,所以总线就以一半的频率运行。
在本发明现行优选的实施方案中,时钟发生器230接收一个输入时钟信号CLK及一个选择信号SELECT。CLK信号是计算机系统的外部时钟信号。所有的外部定时参数均由对应于CLK信号的上升沿确定。在现行优选实施方案中,CLK是一个33MHz信号。SELECT信号指定要通过时钟发生器230发生的磁心时钟信号的频率。在现行的优选实施例中,SELECT指明通过时钟发生装置产生的磁心时钟信号频率是一倍或两倍总线时钟信号的频率。在现行优选实施例中SELECT信号是从一连接选件取得的。这种可选择性就可以从单一模片利用选择逻辑连接插座的连接线配置来满足多种型号微处理机的要求。
总线控制器220控制处理器200与计算机系统母线之间数据的传送(图1)。由于1X模式总线时钟信号CLKOUT和CLKIN是利用的2X模式磁心相位PH1和PH2的原始相位作周期的,故这些总线时钟信号的相位与2X磁心时钟信号的起始和结尾相对准,因而就使得为驱动半速总线的电路减到最少。
当操作磁心单元210以二倍总线速度运行时,总线控制器220趋向于由老周期的起点转变为老周期的末尾。为了防止这一点,总线控制器220产生一闭锁信号。此闭锁信号重新规定总线控制器的总线状态。利用一等待状态使得总线时钟信号偏离1X周期起始部分的起点和1X周期结束部分的终点。这就使得定时可以是相同的。因此,本发明为在2X模式中处理器200与计算机母线接口,即无需另外增加输出驱动器和输入锁存。
闭锁信号由闭锁发生器221产生。闭锁发生器221给CLKOUT信号增加二个相位的延迟来产生此闭锁信号。这样来防止总线控制器220的过早变换。此闭锁发生器利用SELECT信号启动。当处理机200处于1X模式时,一“与”门接收SELECT信号,输出一逻辑0信号。此逻辑0输出关闭此闭锁发生器221。
在本发明现在的优选实施例中,时钟发生器是一锁相回路(PLL)300,如图3示。PLL300产生磁心时钟信号PH1和PH2以及总线时钟信号CLKOUT和CLKIN。在本优选实施例中,PLL300是一个4X锁相回路,它产生一倍或二倍总线时钟信号频率的磁心时钟信号。
参看图3,PLL300包括有:输入缓冲器301a和301b,频率相位检测器302,供给泵303,环路滤波器304,压控振荡器(VCO)305,除二电路306,延迟器307a~d及312,D触发器308,“或”门309,以及PH2/PH1电路314。
输入缓冲器301a及b缓冲存放其输入端的信号,并将这些信号反相输出。这些缓冲器的作用是对准他们输入信号的上升沿,以使频率相位检测器302能确定此二信号间的相位差。相位检测器302仅只测量这些信号被缓存的下降边沿。输入缓冲器301a的输入连接到输入时钟CLKIN。在本发明优选实施例中,CLK是一由外部时钟发生器输入到处理机的33MHZ信号。缓冲器301a的输出连接到频率相位检测器302的Refclk输入端。输入缓冲器301b的输入端连接到延迟器312。此输入表示PLL300的反馈信号。缓冲器301b的输出端连接到频率相位检测器302的Feed back(反馈)输入端。
相位检测器302对由输入缓冲器301a及b输入的频率进行比较,产生一表征这些信号间的相位差的输出。相位检测器302具有二个输出端。ADJUP输出端连接到供给泵303的一个输入端。ADJDWN输出端连接到供给泵303的另一个输入端。当反馈信号的边沿滞后或超前CLK信号的边沿时,分别产生ADJUP或ADJDWN输出。
供给泵303连接到环路滤波器304及压控振荡器(VCO)305的VCNTL输入端。供给泵303响层ADJUP或ADJDWN脉冲分别产生一充电或放电电流,供给环路滤波器304的电容元件。这一电流使得环路滤波器304的电容元件充电或放电,产生一控制电压。此控制电压表明CLK信号的输入频率与反馈信号之间的相差程度。此控制电压被送到VCO305的VCNTL输入端。
VCO305接收此控制信号和一启动信号EN,产生VCOUNT。VCO305的此VCOUNT输出连接到除二电路306的CLK输入端。当计算机系统接通电源时,VCO305即被启动。启动后VCO即响应该控制电压产生一频率VCOUNT。如果CLK信号的频率不等于反馈信号的频率,VCO305所产生的频率即向CLK信号的频率方向偏移。
除二电路306产生两个输出PA和PB。这些输出均为VCO305的输出VCOUNT的一半频率,并为无重叠脉冲。输出PA和PB分别连接到延迟器307b及d。在本优选实施例中,延迟器307b及d均包括反相器。延迟器307b的输出连接到延迟器307a、“与”门310a的输入端之一、D触发器308的时钟输入端,以及反相器313的输入。延迟器307d的输出连接到延迟器307c的输入和“与”门310b的输入之一。
延迟器307a及c在本优选实施例中均由反相器组成。延迟器307a的输出连接到PH1/PH2电路的EPH2输入端。延迟器307c的输出连接到PH1/PH2电路314的EPH1输入。
D触发器308以经延迟器307b缓冲的除二电路306的PA输出信号作为时钟触发而产生输出Q。
Q输出连接到D触发器308的输入D。D触发器308的输出连接到“或”门309的输入之一。“或”门309的另一输入连接MODE信号。在本优选实验中,此MODE信号指明时钟发生器300应产生的磁心时钟信号到底应为总线时钟信号的频率的一倍(1X)还是二倍(2X)。“或”门309的输出连接到“与”门310a及310b的另一输入端。“与”门310b的输出为CLKOUT信号。“与”门310a的输出连接到“与”门311的输出之一。“与”门311的另一输入连接到反相器313的输出。“与”门311的输出为CLKIN信号。“与”门311的输出还连接到延迟器312的输入。在本优选实施例中,延迟器312由一系列反相器组成。延迟器312的输出经反相后连接到缓冲器301b的输入。
PH1/PH2电路314接受EPH2及EPH1作为输入产生磁心时钟相位2信号PH2及磁心时钟相位1信号PH1。参看图3,EPH2输出连接到反向器314f的输入及PnP晶体管314a的栅极。晶体管314a的源极连接Vcc。晶体管314a的漏极连接到PnP晶体管314b的栅极,晶体管314d的漏极及晶体管314c的源极。晶体管314d的栅极连接Vcc,源极连接到PH1输出。晶体管314c的栅极接地,其漏极连接到PH1输出。晶体管314b的源极连接Vcc,而其漏极连接到PH2输出及npn晶体管314e的漏极。晶体管314e的栅极连接到反相器314f的输出。晶体管314e的源极接地。EPH1输入连接到反相器314L的输入及pnp晶体管314g的栅极。晶体管314g的源极接Vcc。晶体管314g的漏极接到pnp晶体管314n的栅极,晶体管314j的漏极及晶体管314i的源极。晶体管314j的栅极连接Vcc,源极连接到PH2输出。晶体管314i的栅极接地,其漏极接到PH2输出。晶体管314h的源极接Vcc,其漏极连接到PH1输出及npn晶体管314k的漏极。晶体管314k的栅极连接到反相器314L的输出。晶体管314k的源极接地。电路314的目的是为了保证PH2和PH1信号不重叠。从功能上,电路314使得一个信号能在另一信号成为高之前变为低。实现这一过程是技术领域所公知的。
在本优选实施例中,PLL300根据一输入CLK信号产生磁心时钟信号PH2和PH1,以及总线时钟信号CLKIN和CLKOUT。此CLK信号进入处理机200的时钟发生器230(图2)。此信号经输入缓冲器301a缓存,并与缓冲器反馈信号(也经过缓存)一起进入相位检测器302。相位检测器302输出一上调信号ADJUP或者一下调信号ADJDWN。供给泵303接收这些信号,产生充电或放电电流,并将其送到环路滤波器304的电容元件。这一电流使环路滤波器304的电容元件充电或者放电产生一控制电压。所产生的控制电压被送到VCO305的VCNTL输入。
此控制信号激励VCO305输出。当控制电压增加时,VCO305输出的频率升高。当此控制电压减小时VCO305输出的频率降低。VCO310的输出被输入进除二电路306。此除二电路306将VCO305的输出频率对分,以产生两个输出PA和PB,为此CLK信号的每一上升沿均为输出信号产生一边沿,上升和下降。这些输出均为VCO305的输出VCOUNT的频率的一半,而且为没有重叠的脉冲。
PA及PB信号分别为磁心时钟的相位2,PH2信号,及相位1,PH1信号的激励信号。PA信号经延迟器307b及307a延迟后输入到电路314的EPH2输入端。PB输出信号经延迟器307d延迟后由输入端EPH1输入进电路314。电路314的输出即磁心时钟信号PH2和PH1。
PA输出,亦即由延迟器307b输出的PH2信号,经过“与”门310a和311以及延迟器312,为PLL300产生反馈信号。此反馈信号即为由PLL300所产生的CLKIN信号。“与”门310a的作用是取决于它的来自“或”门309的输入,或者“吞掉”此反馈信号,或者让其通过。在2X模式下,“与”门310a(以及“与”门310b)屏蔽掉每隔一个时钟信号。因而输入进“与”门311的反馈信号,在2X模式时,为反馈信号亦即PH2磁心时钟信号频率1/2。反相器313为“与”门311的另一输入,它使得在当经过延迟器307d缓存的由除二电路306的PB输出端得到的PH1信号为低时,该反馈信号能通过“与”门311。这时保证了磁心时钟信号与总线时钟信号之间的正确定时关系。
“与”门311的输出为CLKIN信号。在1X模式,因为反馈信号可以通过“与”门310a,此CLKIN信号与PH2磁心时钟信号同频。在2X模式,因为每相隔一个反馈信号被屏蔽掉,CLKIN信号的频率即为PH2磁心时钟信号的1/2。在由“与”门310b输出的CLKOUT信号与PH1磁心时钟信号之间的关系也是如此。
CLKIN信号,亦即反馈信号,经延迟器312延迟并由输入缓冲器301b反馈回PLL300。在2X模式,由于此反馈信号为输入CLK信号的一半,供给泵303及环路滤波器304产生较大电压以补偿CLK与CLKIN信号之间大的频率差。这样产生的大控制电压使得VCO305产生较高的频率。305的较高频率就产生较高的PH1及PH2磁心时钟信号。这样,本发明就得到了2倍(2X)CLK信号频率的磁心时钟信号PH1和PH2。
“或”门309控制“与”门301a的操作。有较高位MODE信号将PLL300置于1X模式,而有效低位则将PLL300转换到2X模式。因此,当PLL处于1X模式时,“或”门309的输出总是逻辑1。因而反馈信号不会被屏蔽而通过“与”门310b。在这一状态下,CLKOUT及CLKIN信号与PH1及PH2磁心时钟信号同频。从而总线(图1)即以与磁心单元210(图2)相同的频率运行。
当PLL转换到2X模式时,“或”门309的输出取决于D触发器308的输出。如果D触发器308的输出为逻辑1,“与”门301a端出现逻辑1而允许反馈信号通过。如果D触发器308的输出为逻辑0,“与”门310a端出现逻辑0,“与”门310a将反馈信号屏蔽,从而阻止其通过该门电路,而且,在D触发器308输出为逻辑0时,“与”门310b还将输出CLKOUT信号屏蔽掉。
增加D触发器308作为第二个除二电路。D触发器308被接于主要路径之外,以延迟器307b的输出作为其触发时钟。因而延时器307b的输出时钟脉冲每间隔一个即由D触发器308产生出一个逻辑1。这样当PLL处于2×模式时,延时器307b的输出时钟脉冲每间隔一个即由“或”门309产生一逻辑1输出,以使“与”门310a阻止反馈信号通过“与”门310a。另外,在这种情况下“与”门310b还阻止PH1信号通过它作为CLKOUT信号。因而310b还阻止PH1信号通过它作为CLKOUT信号。因而CLKOUT及CLKIN信号均因为一半信号脉冲被屏蔽而成为PH1及PH2磁心时钟信号的频率的1/2。不过,虽然它们均为1/2,但信号的定时时序仍是严格相同的,因为总线时钟信号CLKIN及CLKOUT的上升和下降沿均是分别与磁心时钟信号PH2及PH1的上升和下降沿对准的。这就使得磁心单元210(图2)能以总线速度的二倍操作而不改变定时时序。
本优选实施例的PLL300在1X模式时产生的定时信号如图4中所示。图4中作出了输入时钟信号CLK。此CLK信号是一由外部产生的33MHZ1X输入。PH1及PH2分别由PH2/PH1电路314输出的33MHZ磁心时钟相位1及相位2时钟信号。CLKOUT及CLKIN信号为分别与每间隔一个PH1及PH2磁心时钟信号同步的、同样是33MHZ的总线时钟信号。
图4还示出了本发明计算机系统在1X模式时的总线状态(BUSSTATE)。总线周期开始于T1,即当CLKOUT信号变成高电位,地址被驱动到计算机系统母线上之际。而后总线控制器220利用逻辑电路在T1的PH2磁心时钟信号期间,进行由T1到T2的转变。在T2的起始,如果该周期是一写周期的话,当CLKOUT信号变为高电平时数据就被驱送到计算机系统母线上;否则在CLKOUT为高电平状态时将无任何操作。在T2期间数据在CLKIN阶段由计算机系统返回。如果就绪信号表明数据有效,即利用该数据。在这种状态下,总线控制器220根据周期的类型,可转变为或者新的T2,或一新的T1,或闲置状态。
本优选实施例PLL300在2X模式下所产生的定时信号如图5中所示。图5中列出了输入时钟信号CLK。CLK信号为由外部产生的33MHZ1X输入。PH1及PH2是由PH2/PH1电路314输出的、分别为磁心时钟相位1及相位2的66MHZ时钟信号。CLKOUT信号CLKIN信号为分别与每间隔一PH1及PH2磁心时钟信号相同步的1/4占空比为33MHZ总线时钟信号。
图5还示出了本发明计算机系统的BUS STATE(总线状态)。总线周期起始于T1 ADDRESS,即当CLKOUT信号转变为高电平状态地址被传送到计算机系统总线上之际。应注意到T1被分成两个状态,T1 ADDRESS和T1 END。实际上这给T1增加了一个等待周期,因为在T1 ADDRESS状态期间,总线控制器220的状态部件不知道它是处于T1时期。在T1结束(END)时,总线控制器220确定其为T1。而后总线控制器220利用逻辑电路在T1 END的PH2磁心时钟信号期间进行由T1到T2的转换。在T2的起始,如果该周期是一写周期的话,即在CLKOUT转变为高电平时,将数据传送到计算机系统母线上;否则在CLKUT为高电平状态期间无操作进行。在T2 END期间,数据在CLKIN阶段由计算机系统总线返回。如果就绪信号指明数据有效,即利用该数据。在这种状态下,总线控制器220根据周期的类型,可转换到或者新的T2,或者一新的T1,或者一闲置状态。
Claims (20)
1、用于一具有总线的计算机系统的微处理机,所述总线用来传送数据,其特征在于所述微处理机包括有:
用于产生磁心时钟信号及总线时钟信号的时钟发生装置,所述磁心时钟信号可以为第一或第二频率,所述总线时钟信号为所述第一频率,所述第二频率快于所述第一频率;
响应所述磁心时钟信号以处理所述数据的磁心单元;和
响应所述总线时钟信号以驱动所述总线上的数据的总线控制器。
2、如权利要求1所述的微处理机,其特征在于还进一步包括有一连接到所述时钟发生装置的转换装置,所述转换装置用来转换所述时钟发生装置,当所述转换装置处于第一位置时,所述时钟发生器产生所述第一频率的所述磁心时钟信号;当所述转换装置处于第二位置时产生所述第二频率的所述磁心时钟信号。
3、如权利要求1所述的微处理机,其特征在于所述总线时钟信号的脉冲宽度与所述磁心的时钟信号相同。
4、用于一具有总线的计算机系统的微处理机,所述总线用来传送数据,其特征在于所述微处理机包括有:
用于产生磁心时钟信号及总线时钟信号的时钟发生装置,所述磁心时钟信号可以为第一或第二频率,所述总线时钟信号为所述第一频率,所述第二频率较所述第一频率快;
连接到所述时钟发生装置的转换装置,所述转换装置用于转换所述时钟发生装置,当所述转换装置处于第一位置时,所述时钟发生装置产生所述第一频率的所述磁心时钟信号;当所述转换装置处于第二位置时,所述磁心时钟信号为所述第二频率;
响应所述总线时钟信号以驱动所述总线上的数据的总线控制装置。
5、如权利要求4所述的微处理机,其特征在于还包括有闭锁发生装置,用以产生阻止所述总线控制装置进行由旧周期启始向旧周期结束转换的闭锁信号。
6、如权利要求5所述的微处理机,其特征在于所述转换装置在通常模式中禁止所述闭锁发生装置。
7、如权利要求1所述的微处理机,其特征在于所述时钟发生装置包括有:
磁心时钟信号发生装置,用于响应系统时钟信号产生磁心时钟信号,以使得所述磁心时钟信号的频率高于该系统时钟信号的频率;和
连接到所述磁心时钟信号发生装置的总线时钟信号发生装置,用于接收磁心信号并响应所述磁心时钟信号以产生总线时钟信号,其中所述总线时钟信号发生装置对所述磁心时钟信号进行屏蔽以产生所述总线时钟信号,而使所述磁心信号不受影响。
8、如权利要求1和7所述的微处理机,其特征在于所述第二频率为第一频率的二倍。
9、如权利要求7所述的微处理机,其特征在于所述时钟发生器包括有一锁相回路。
10、如权利要求9所述电路,其特征在于所述磁心时钟发生装置包括一锁相回路,它由下列部分组成:
一相位检测装置,用于接收所述系统时钟信号及一反馈信号,并根据表征所述系统时钟信号和所述反馈信号间的相位差的量来产生第一信号;
一电压产生装置,根据所述第一信号来产生电压控制信号;
一压控振荡装置,根据所述电压控制信号产生磁心信号,所述磁心信号的频率随所述反馈电压的大小改变;和
一分频装置,根据所述磁心时钟信号产生所述反馈信号,所述反馈信号具有所述磁心时钟信号数倍的频率,使得所述振荡装置产生一所述系统时钟信号频率的N倍的信号。
11、如权利要求10所述电路,其特征在于所述分频装置由下列部件组成:
根据至少一个所述磁心信号来产生一屏蔽信号的第一逻辑装置,所述屏蔽信号为第一状态或为第二状态;
第二逻辑装置,根据所述磁心信号及所述屏蔽信号产生所述反馈信号,而当所述屏蔽信号为所述第一状态时,所述第二逻辑装置产生所述反馈信号,而当所述屏蔽信号为所述第二状态时,则屏蔽所述反馈信号。
12、如权利要求10所述的电路,其特征在于所述分频装置产生所述总线时钟信号。
13、在一以一系统时钟信号作为时钟工作的微处理机中,一使得所述微处理机的磁心能以地址和数据总线频率的N倍运行的电路,其特征在于所述电路包括有:
一相位检测装置,接收所述系统时钟信号和一反馈信号,并根据表征所述系统时钟信号与所述反馈信号间相位差的量产生一第一信号;
一电压发生装置,根据所述第一信号产生一压控信号;
一压控振荡装置,根据所述压控信号产生磁心信号,所述磁心信号的频率随所述反馈电压的大小改变;
第一逻辑装置,根据至少一所述磁心信号产生一屏蔽信号,所述屏蔽信号为第一状态或者为第二状态;和
第二逻辑装置,根据所述一磁心信号和所述屏蔽信号产生所述总线时钟信号,当所述屏蔽信号为所述第一状态时所述第二逻辑装置产生所述总线时钟信号;而当所述屏蔽信号为所述第二状态时则屏蔽所述总线控制信号,所述总线控制信号具有所述磁心时钟信号数倍的频率,所述总线控制信号之一为所述反馈信号,从而该所述振荡装置产生频率为所述系统时钟信号N倍的磁心时钟信号。
14、如权利要求13所述的电路,其特征在于所述第二逻辑装置产生的屏蔽信号屏蔽每间隔一个的所谓总线控制信号,而使所述反馈信号驱动所述振荡装置产生二倍所述系统时钟信号频率的磁心时钟信号。
15、如权利要求13和14所述的电路,其特征在于进一步包括有使所述磁心在正常模式和快速模式间转换的转换装置。
16、如权利要求13和14所述的电路,其特征还包括有闭锁产生装置,产生一阻止总线控制装置由旧周期起始段向旧周期结束段转变的闭锁信号。
17、如权利要求16所述的电路,其特征在于所述转换装置在正常模式下,禁止所述闭锁装置。
18、在一具有传送数据的总线的计算机系统中应用的微处理机,其特征在于包括:
一个磁心,用于处理所述数据;和
总线控制装置,用于驱动所述总线上的所述数据,其中所述磁心以比所述总线快的速度运行,使总线能容纳下较之所述磁心处理的更多的数据。
19、如权利要求18所述的微处理机,其特征在于所述总线频率的时钟脉冲的脉冲宽度与所述磁心频率的时钟脉冲的脉冲宽度相等。
20、如权利要求19所述的微处理机,其特征在于总线时钟信号的占空比为1/4。
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-
1992
- 1992-08-28 GB GB9218302A patent/GB2260631B/en not_active Expired - Lifetime
- 1992-09-30 CN CN92112046A patent/CN1130646C/zh not_active Expired - Lifetime
- 1992-10-08 IT ITMI922317A patent/IT1255851B/it active IP Right Grant
- 1992-10-15 FR FR9212340A patent/FR2682785A1/fr active Granted
- 1992-10-15 KR KR1019920018958A patent/KR100265218B1/ko not_active IP Right Cessation
- 1992-10-16 DE DE4235005A patent/DE4235005C2/de not_active Expired - Fee Related
- 1992-10-19 JP JP4304486A patent/JPH05233275A/ja active Pending
-
1993
- 1993-03-24 US US08/036,441 patent/US5537581A/en not_active Expired - Lifetime
- 1993-03-24 US US08/036,470 patent/US5481731A/en not_active Expired - Lifetime
- 1993-03-25 US US08/037,711 patent/US5634117A/en not_active Expired - Lifetime
-
1995
- 1995-10-16 US US08/543,523 patent/US5630146A/en not_active Expired - Lifetime
-
1997
- 1997-04-09 US US08/838,393 patent/US5884068A/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
GB9218302D0 (en) | 1992-10-14 |
US5634117A (en) | 1997-05-27 |
ITMI922317A1 (it) | 1993-04-18 |
DE4235005C2 (de) | 2002-11-28 |
KR930008647A (ko) | 1993-05-21 |
GB2260631A (en) | 1993-04-21 |
FR2682785B1 (zh) | 1995-02-17 |
FR2682785A1 (fr) | 1993-04-23 |
US5537581A (en) | 1996-07-16 |
KR100265218B1 (ko) | 2000-09-15 |
US5884068A (en) | 1999-03-16 |
CN1130646C (zh) | 2003-12-10 |
ITMI922317A0 (it) | 1992-10-08 |
GB2260631B (en) | 1995-06-28 |
DE4235005A1 (de) | 1993-04-22 |
JPH05233275A (ja) | 1993-09-10 |
IT1255851B (it) | 1995-11-17 |
US5481731A (en) | 1996-01-02 |
US5630146A (en) | 1997-05-13 |
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