CN1102274A - 具有异型掺杂岛的半导体器件耐压层 - Google Patents

具有异型掺杂岛的半导体器件耐压层 Download PDF

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CN1102274A
CN1102274A CN93115356A CN93115356A CN1102274A CN 1102274 A CN1102274 A CN 1102274A CN 93115356 A CN93115356 A CN 93115356A CN 93115356 A CN93115356 A CN 93115356A CN 1102274 A CN1102274 A CN 1102274A
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withstand voltage
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CN1035294C (zh
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陈星弼
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3d Semiconductor Ltd By Share Ltd
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University of Electronic Science and Technology of China
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Abstract

本发明介绍了具有异型掺杂岛的半导体功率器 件的耐压层，其特征是在耐压层中引入异型掺杂岛代 替以往的一种导电类型的耐压层。耐压层中的异型 掺杂岛是与衬底平行排列，异型掺杂岛可以是单层或 多层，相邻两层异型掺杂岛是重迭排列或交错排列，其耐压层导通电阻与击穿电压的关系Ron＝0.83×10-8VB 2.5/n1.5(Ω.cm2)。同时本发明还提供了一些半导体高压功率器件的新结构，采用本发明可得到性能更优良的各类新结构的半导体高压功率器件。

Description

本发明属于半导体功率器件。
现有的半导体功率器件的耐压是靠一层较轻掺杂的单一导电类型的半导体材料（可以是外延或其它技术制成），这里称它为耐压层或漂移区。对于高压功率器件，导通电阻（或正向压降）主要是由这耐压层决定，耐压层的耐压能力与它的掺杂浓度及厚度有关，浓度愈低、厚度愈大，则耐压愈高，导通电阻（或正向压降）则愈大。在一般VDMOS或SIT的漂移区中，或双极型结型晶体管的轻掺杂集电区中等，当最大电场强度达到击穿临界电场强度EC＝8.2·V-0.2 B[V/cm]时，发生雪崩击穿，击穿临界电场强度EC几乎是常数。图1-1示出一个VDMOS的结构，图1-2示出在VDS＝VB时的电场强度分布。其中VDS为漏源电压，VB为器件的击穿电压，W为耐压层（n-外延层的一部分）的厚度。
由图可见，对于一个高击穿电压VB，耐压层的厚度W应该大，而掺杂浓度ND应该低。由于单位面积的导通电阻Ron正比于W/ND，因此器件高的击穿电压VB总是伴随着一个高的导通电阻Ron，它们之间的关系是：对n型耐压层
Ron＝0.83·10-8V2.5 B[Ω·cm2]……（1）
一些研究工作者，例如：
（1）C.Hu，IEEE  Trans.Electron  Devices
Vol.ED-2  No.3.P243（1979）
（2）V.A.K  Temple，et  al.IEEE  Trans，Electron  Devices，
Vol-ED  27，No.2.  P243（1980）
（3）X.B  Chen（陈星弼），C.Hu，IEEE  Trans，Electron  Dev-ices
Vol-ED  29  No.6  PP985-987（1982）
曾试图揭示，如果耐压层（n-外延层）掺杂的浓度分布是非均匀的，则击穿电压VB与导通电阻的关系是否会改善得好一些，其结果表明没有明显的改进。
本发明的目的在于提供一种具有异型掺杂岛结构的耐压层（或漂移区），在这层耐压层上再制作高压功率器件，以得到性能更优良的各类新结构的高压功率器件。其击穿电压与导通电阻的极限关系将建立在一个新的基础上，从而可以大大缓解导通电阻（或正向压降）与器件击穿电压的矛盾。
为了实现以上的目的，本发明的具体方案是：在耐压层内（即外延层内），引入异型掺杂岛以代替以往的单一导电类型的耐压层，它的结构如图2所示。
其结构特征为：
（1）P（或n）岛被n-（或P-）的外延层所包围;
（2）耐压层（外延层）中的P（或n）岛与n+（或P+）衬底平行排列;
（3）P（或n）岛在耐压层中可是单层（n＝2），也可是多层（n＝3、n＝4……），当P（或n）岛将整个耐压层分成几个“亚层”时，各亚层的厚度相等，对单层P（或n）岛，n＝2（n是亚层数）即将整个耐压层分成两个“亚层”，此时P（或n）岛位于耐压层厚度二分之一处如图2-1所示，对两层P（或n）岛，n＝3，即将整个耐压层分成三个“亚层”，此时，P（或n）岛位于耐压层三分之一及三分之二处如图2-2、图2-3所示;
（4）P（或n）岛在耐压层中可以是重迭排列，或交错排列，图2-2所示为两层P（或n）岛重迭排列，图2-3所示为两层P（或n）岛交错排列;
（5）P（或n）岛应置于纵向导电型功率器件的耐压层中对导电几乎没有贡献的区域，在垂直导电的功率MOST中，P（或n）岛位于源极下方，在双极型晶体管中，P（或n）岛位于基极电极条下方。
根据本发明提供的具有异型掺杂岛结构的耐压层（或漂移区），制作出性能优良的各类新结构的功率器件，列举如下：
本发明用于MOST结构的功率器件。
具有单层P（或n）岛，n＝2的MOST结构。图3-1示出n＝2的MOST功率器件结构图，各部分的导电类型P型或n型在图中括弧内外各相互对应。图3-1中标号，1为P（或n）岛、2为n-（或P-）外延层、3为n+（或P+）衬底、4为P（或n）阱、5为n+（或P+）源区，现以单层P岛的MOST功率器件为例，当在截止状态时，该结构中在P岛中的空穴被源极抽出，而n-外延层中的电子被漏极抽出。P岛下面正电荷的电力线极大部分终止于耗尽了的P岛内的负电荷，故电场强度不在整个耐压层内积累，在击穿附近的电场强度分布如图3-2所示。
假定整个耐压层内有n个“亚层”，每一“亚层”能维持VB/n电压，其中VB为整个耐压层的击穿电压，于是很明显，导通电阻是每一区域的n倍。
即 Ron＝n·0.83×10-8（VB/n）2.5＝0.83×10-8V2.5 B/n1.5……（2）
（Ron的实际值是要比上式得到的计算值略高一些）
对比（1）（2）式，可以看出，新发明的具有P岛耐压层结构的MOST功率器件，其Ron在高压范围内要比传统VDMOS的Ron小得多。
具有两层P（或n）岛n＝3的MOST结构。图3-3示出具有两层交错排列P（或n）岛MOST功率器件（也可是重迭排列）图3-3标号，1为P（或n）岛、2为n-（或P-）外延层、3为n+（或P+）衬底、4为P（或n）阱、5为n+（或P+）源区。以具有两层P岛的MOST功率器件为例，当它的击穿电压与单层P岛的MOST功率器件击穿电压VB相同时，其导通电阻Ron要比图3-1单层P岛的MOST的导通电阻更小。从关断时间来看，图3-1和图3-3所示结构的开启瞬态类似IGBT的关断瞬态，器件的电压变化有一个很快的衰减阶段，其时间常数几乎与VDMOS的开启时间相同。并有一个像IGBT被关断时的电流尾部。
在IGBT衬底（n-外延层位于薄重掺杂n层上，n层又位于P衬底上）MOST结构。图3-4示出在IGBT衬底上具有单层P（或n）岛的MOST功率器件。图3-5示出在IGBT衬底上具有两层P（或n）岛的交错排列MOST功率器件（也可以是重迭排列），图3-4、图3-5标号，1为P（或n）岛、2为n-（或P-）外延层、4为P（或n）阱、5为n+（或P+）源区，6为P（或n）衬底、7为n（或P）缓冲层。以在IGBT衬底上具有P岛的MOST结构为例，该结构从衬底向耐压层注入少量空穴，就可以使图3-1、图3-3MOST结构的开启尾部缩短，从而减小开启时间。若注入效率γ很小，则在器件中仍是少子起主导作用，这样就不会影响关断时间，于是整个开启时间比0.1μs小得多，因此能使其开启过程与关断过程与传统MOST一样快。
具有单层异型掺杂岛耐压层的R-MOST结构功率器件。图4示出具有单层P（或n）岛耐压层的R-MOST功率器件。其中标号，1为P（或n）岛、2为n-（或P-）外延层、3为n+（或P+）衬底、4为P（或n）阱、5为n+（或P+）源区。
本发明用于双极型功率器件。
图5示出具有单层P（或n）岛耐压层的双极型功率晶体管。其中标号1为P（或n）岛、2为n-（或P-）外延层、3为n+（或P+）衬底、4为P（或n）内基区、5为n+（或P+）发射区、9为P+（或n+）外基区。
图2所示结构在P+和n+两面制作两个金属电极，即形成具有异型掺杂岛耐压层的高压二极管，这种结构的二极管在速度方面比高压PIN二极管更好。
本发明用于静电诱导晶体管（SIT）。
该晶体管其栅可以采用埋栅，也可以是表面栅，图6示出具有单层P（或n）岛耐压层的表面栅静电诱导晶体管。其中标号1为P（或n）岛、2为n-（或P-）外延层、3为n+（或P+）衬底、5为n+（或P+）源区、9为P+（或n+）栅。
根据上述列举在新发明的耐压层上制作出的功率器件，具有耐压高、导通电阻（或正向压降）小、开启与关断时间快等优点。同时本发明在理论上研究出导通电阻Ron与击穿电压VB的一个新关系Ron＝0.83×10-8V2.5 B/n1.5。由此可见本发明大大的缓解了高压功率器件导通电阻Ron（或正向压降）与击穿电压VB的矛盾，在改善导通电阻与器件耐压方面有着重要的突破。
本发明的附图说明：
图1是现有技术VDMOS的示意图。其中图1-1为结构图;图1-2为电场分布图。
图2是本发明耐压层结构，其中图2-1为单层异型掺杂岛;图2-2为两层重迭排列的异型掺杂岛;图2-3为两层交错排列的异型掺杂岛。
图3是采用本发明制作的具有P（或n）岛的MOST结构功率器件。其中图3-1为具有单层P（或n）岛;图3-2是图3-1结构在击穿附近的电场强度分布图;图3-3为两层交错排列的P（或n）岛;图3-4是在IGBT衬底上的单层P（或n）岛;图3-5是在IGBT衬底上的两层交错排列的P（或n）岛。
图4是采用本发明制作的具有单层P（或n）耐压层的R-MOST功率器件。
图5是采用本发明制作的具有单层P（或n）岛耐压层的双极型功率晶体管。
图6是采用本发明制作的具有单层P（或n）岛表面栅静电诱导晶体管。
下面结合附图通过实施例进一步说明本发明。
为了制作本发明具有P岛的耐压层，其设计方法是：从要求的击穿电压VB出发（下面数据可作为本发明耐压层设计的参考数据），然后再作模拟计算，以得出精确的数据。
耐压层厚度W＝0.024V1.2 B微米（VB以伏计）
n层掺杂浓度ND＝n·2.2·1018V-1.4 B[1/cm3]
（当式中n＝2时为单层P岛，n＝3时为两层P岛）
在单位面积中，每层P岛掺杂总量为NT
NT＝3.53×1012（VB）-0.2[1/cm2]
设计参数确定后，现结合附图3制作四种MOST功率器件为例说明制造耐压层的工艺过程。
第一步：对于图3-1、图3-3所示的MOST功率器件，从<100>晶向的n+硅片着手，对于图3-4、图3-5所示的MOST功率器件则在<100>晶向P衬底上具有薄n外延层的硅片着手。
第二步：掺杂n-外延，形成20微米厚、3[Ω-cm]n-型外延层。
第三步：氧化，随后开出3微米的窗口。
第四步：通过窗口进行硼离子注入。
第五步：重复第二步形成P岛。当需要形成多层P岛，则重复第二步到第五步若干次。
第六步：剩下的步骤与传统制作VDMOS相同。

Claims (8)

1、一种具有异型掺杂岛的半导体器件耐压层，包含有一层较轻掺杂的单一导电类型的半导体材料，其特征在于耐压层内(即外延层内)，引入P(或n)岛，P(或n)岛被n(或P)的外延层所包围，外延层(耐压层)中的P(或n)与n+(或P+)衬底平行排列。
2、根据权项1所述的的耐压层，其特征在于P（或n）岛在耐压层中是单层或多层，P（或n）岛将整个耐压层分成n个“亚层”时，各“亚层”的厚度相等。
3、根据权项1所述的耐压层，其特征在于多层P（或n）岛在耐压层中是重迭排列、或交错排列。
4、根据权项1所述的耐压层，其特征在于P（或n）岛置于纵向导电型功率器件的耐压层中对导电没有贡献的区域。
5、根据权项4所述的耐压层，其特征在于在垂直导电功率器件MOST中P（或n）岛位于源极下方，在双极型晶体管中，P（或n）岛位于基极电极条下方。
6、根据权项1所述的耐压层，其特征在于当耐压要求为VB（伏），耐压层厚度W＝0.024V1.2 B微米，n层掺杂浓度ND＝n·2.2×1018V-1.4 B[1/cm3]，单位面积每层P岛掺杂总量NT＝3.53×1012（VB）-0.2[1/cm2]。
7、根据权项1或6所述的耐压层，其特征在于当耐压要求为VB，有n个“亚层”，导通电阻Ron＝0.83×10-8V2.5 B/n1.5。
8、根据权项1所述的耐压层，其特征在于在MOST结构功率器件中P（或n）岛在外延层n-（或P-）中是单层排列、或两层交错排列、或两层重迭排列，在IGBT衬底上P（或n）岛在外延层n-（或P-）中是单层排列、或两层交错排列、或两层重迭排列。
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CN103151392A (zh) * 2013-02-07 2013-06-12 电子科技大学 一种带有p型氮化镓埋层的垂直氮化镓基异质结场效应晶体管
CN109659359A (zh) * 2013-07-11 2019-04-19 英飞凌科技股份有限公司 双极晶体管以及制造双极晶体管的方法
CN104810408A (zh) * 2014-01-24 2015-07-29 无锡华润华晶微电子有限公司 一种超势垒整流器件及其制造方法
WO2015109929A1 (zh) * 2014-01-24 2015-07-30 无锡华润华晶微电子有限公司 一种超势垒整流器件及其制造方法
CN104167442A (zh) * 2014-08-29 2014-11-26 电子科技大学 一种具有P型GaN岛的垂直氮化镓基异质结场效应晶体管
CN106298974B (zh) * 2015-05-22 2019-07-05 朱江 一种半导体结装置
CN106298974A (zh) * 2015-05-22 2017-01-04 朱江 一种半导体结装置
CN105390536A (zh) * 2015-09-30 2016-03-09 深圳市可易亚半导体科技有限公司 绝缘栅双极型晶体管及其制备方法
CN105720089A (zh) * 2016-02-16 2016-06-29 上海华虹宏力半导体制造有限公司 超级结及其制造方法
CN105720089B (zh) * 2016-02-16 2018-10-26 上海华虹宏力半导体制造有限公司 超级结及其制造方法
CN106340535A (zh) * 2016-08-01 2017-01-18 苏州捷芯威半导体有限公司 一种半导体器件及其制造方法
CN110212015A (zh) * 2019-04-30 2019-09-06 上海功成半导体科技有限公司 超结器件结构及其制备方法
CN110224017A (zh) * 2019-04-30 2019-09-10 上海功成半导体科技有限公司 超结器件结构及其制备方法
CN111370469A (zh) * 2020-04-30 2020-07-03 上海华虹宏力半导体制造有限公司 超级结器件结构及其制造方法
CN114220848A (zh) * 2022-02-22 2022-03-22 浙江大学 一种快速开通的浮岛器件及其制造方法
CN114220848B (zh) * 2022-02-22 2022-05-10 浙江大学 一种快速开通的浮岛器件及其制造方法

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