CN1103206A - 带有含漏扩展区的most的高压半导体器件 - Google Patents

带有含漏扩展区的most的高压半导体器件 Download PDF

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CN1103206A
CN1103206A CN94108139A CN94108139A CN1103206A CN 1103206 A CN1103206 A CN 1103206A CN 94108139 A CN94108139 A CN 94108139A CN 94108139 A CN94108139 A CN 94108139A CN 1103206 A CN1103206 A CN 1103206A
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A·W·鲁迪胡策
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Koninklijke Philips NV
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Abstract

本发明涉及到一种半导体(1)中含有一个第一导 电类型表面区(3)的半导体器件，此表面区邻接于一 个表面且其中形成有一个场效应晶体管，此场效应晶 体管包含一个沟道区(7)，其上有栅电极(8)、一个源 区(4)、一个漏区(5)和一个漏扩展区(6)。漏扩展区 包含一些第二导电类型区域，这些区域从沟道区向漏 区延伸，其宽度和掺杂浓度要使表面区和漏扩展区之 间的阻塞PN结上的电压差上升时，在发生漏击穿之 前，漏扩展区至少局部地完全耗尽。

Description

本发明涉及到一种半导体中含有一个第一导电类型表面区的半导体器件，此表面区邻接于表面且其中形成有一个场效应晶体管，而场效应晶体管带有隔离栅、在表面区中带有与第一导电类型相反的第二导电类型的源区和漏区以及一个第二导电类型的漏扩展区（它邻接于漏区和表面，掺杂浓度比漏区低并沿源区的方向纵向延伸）、有一个位于漏扩展区和源区之间的第一导电型沟道区、并且有一个位于沟道区之上而用隔离层同沟道区分开的栅电极。
这种半导体器件作为高压开关元件是特别有用的，例如在汽车、电视机和音频功率放大器中的应用。
欧洲专利60429号在开始部分公布了一种器件。在这种器件中，在栅极和相对地重掺杂的漏区之间形成了一个导电类型与重掺杂的漏区相同但掺杂浓度比重掺杂漏区低的漏扩展区。表面区与源区电互连。从某一漏电压（即源区与漏区之间的电压）开始，当表面区和漏扩展区之间的pn结被阻塞时，由于耗尽区从被阻塞的pn结扩大，漏扩展区被夹断，从而使漏区一侧处的表面场强降低而源区和漏区之间发生击穿电压）升高。
虽然用此法可获得高的漏击穿电压，但在实践中，高的击穿电压伴随着较高的源--漏电阻，即晶体管的导通电阻Ron高。这是因为漏扩展区的掺杂较轻会导致漏扩展区的充分耗尽。然而轻掺杂导致漏扩展区的高电阻。而且在实践中为了在漏扩展区中形成所希望的轻掺杂，附加的掺杂步骤常常是必须的。这种附加掺杂步骤使工艺流程更为复杂和昂贵，因而是不希望的。
本发明的特别目的是提供一种半导体器件，它的漏击穿电压和导通电阻可在宽范围内变化，特别好的是不必附加的工艺步骤。
本发明基于这样一种认识，即赋予漏扩展区一个不同的几何形状就可达到上述目的。根据本发明，为此目的的器件的特征是：漏扩展区包含许多第二导电类型的区域，这些区域从沟道区延伸到漏区，且其宽度和掺杂浓度要做到当表面区和漏扩展区之间的被阻塞的pn结上的电压差升高时，在发生漏击穿之前，漏扩展区至少要局部地完全耗尽。
根据本发明的方法，使选择区域的数目和宽度作为器件的附加参数成为可能。人们惊奇地发现本发明的器件能够具有用连续性漏扩展区无法实现的漏击穿电压和导通电阻值。可以认为本发明器件中区域的耗尽是从垂直方向的区域下侧和横向方向的区域侧面二个方向发生的。由于这一所谓的多维耗尽，甚至在各个区域掺杂水平较高的情况下也能够发生完全的耗尽，以致靠近漏扩展区处的电场保持较弱，从而获得较高的漏击穿电压。由于各区域中掺杂较重，器件的导通电阻较低。
各个区域可用较简单的方法来制作而不需附加的工艺步骤，其中在漏扩展区掺杂步骤中形成一个带有很多区域的漏扩展区以取代连续性漏扩展区。通过制作各区域过程中掺杂原子的横向和纵向扩散，可以获得较低的掺杂水平。这一低的掺杂水平提高了漏击穿电压，从而提供了仍利用标准掺杂步骤来获得击穿电压较高的器件的另一些可能性（在标准掺杂步骤中，较大量的掺杂原子被离子注入）。器件的导通电阻只轻微地受扩散的影响。
在第一实施例中，各区的宽度约等于漏扩展区的深度，而掺杂浓度从各区的中心向边缘下降。这种区域可用简单方法制作，例如通过离子注入和随后的扩散来提供掺杂原子。从注入区域的扩散则导致掺杂浓度向区域边缘下降。通常，各个区域的位置基本上彼此相靠。在这种漏扩展区形状中，半导体的表面区得到了最佳的利用。较小的区域间距已导致多维耗尽和漏击穿电压的改善。
在另一实施例中，区域的宽度从沟道区向漏区增加。这一实施例提供了下述优点，即比之区域宽度恒定的情况，漏击穿电压提高了。由于区域宽度从沟道区向漏区增加，电场分布得更为均匀，以致降低了电场的最大值因而在更高的电压下才发生漏击穿。还有一个优点是：由于区域宽度的增加使各区域的电阻小于宽度恒定的各区域的电阻，晶体管的导通电阻变小了。
在另一个实施例中，各区域由邻接沟道区的那部分漏扩展区中的第二导电型区域实行互连。这样，沟道区就成为一个连续性区域，即电流可在沟道的整个宽度内而不仅是在各区域处从源流向漏扩展区，这就造成一个更陡的晶体管。为实现高的漏击穿电压，可能希望使用另一些方法来耗尽邻接于沟道区的漏扩展区。在这部分漏扩展区之上用一个场极电极就可达到这一目的，此场极电极绝缘于漏扩展区且电连接于源区域栅电极。在衬底和表面区之间的边界上形成一个第一导电类型重掺杂层，也可以耗尽这部分漏扩展区。这一重掺杂层则延伸到邻接沟道区的那部分漏扩展区之下。邻接沟道区的漏扩展区部分就从重掺杂区被额外地耗尽，以致在这部分漏扩展区将不出现过早的击穿。
在另一个实施例中，各区域由邻接于漏区域那部分漏扩展区中的第二导电型区域实行互连。漏扩展区和漏区的过渡更为缓慢，以致在电场中不出现尖峰因而能够实现更高的漏击穿电压。
在另一个实施例中，各区域中的掺杂原子的数量约为6×1012原子/cm2。这种数量使得有可能采用对CMOS（互补MOS）中称之为阱掺杂的工艺来对漏扩展区的各区域进行掺杂，并仍然获得较高的漏击穿电压。
以下将参照一些实施例的附图，用举例的方法来更详细地解释本发明，在这些附图中：
图1是本发明半导体器件的平面图。
图2是图1沿Ⅰ-Ⅰ的半导体器件剖面图。
图3和4是图1沿Ⅱ-Ⅱ的不同实施例半导体器件的剖面图。
图5和6是本发明半导体器件另一实施例的平面图。
这些图纯粹是示意性的，并未按比例绘制。各图中的相应部分一般加以相同的参考号。为简洁起见，在平面图2、5和6中省略了表面上的引线图。
图1是本发明半导体器件的平面图，图2和3分别是本发明半导体器件沿图1中Ⅰ-Ⅰ和Ⅱ-Ⅱ的剖面图。半导体器件包含一个半导体1，在此例中是硅，它有一个第一导电类型（此例中为n型）的邻接表面2的表面区3，其中形成了一个带有绝缘栅的场效应晶体管。场效应晶体管在表面区3中包含相反的第二导电类型（此例中为p型）的源区4和漏区5。它还包含一个第二导电类型（p型）掺杂浓度低于漏区5的漏扩展区6，并邻接于漏区5和表面2。漏扩展区6沿原区4的方向纵向延伸。构成表面3一部分的第一导电类型（n型）沟道区7位于漏扩展区6和源区4之间。场效应晶体管的栅电极8在沟道区之上方，用绝缘层（此例中为厚70nm的氧化硅层9）同沟道区7分开。此例中的栅电极8由多晶硅构成，但也可用其它材料如金属来构成。
在由p型半导体衬底构成的半导体10上的n型外延层，构成了表面区3。表面区3在侧向与由从表面2向下延伸到衬底10的一个p型分隔区12相连接。
邻近源区4有一个n+型区，即背栅接触区13，是用来连接表面区3的。在源区4和背栅接触区13之上方，形成了一个导电体14用作源电极，它同时还经由背栅接触区13将源区4与表面区3短路。漏电极15在漏区5上，而衬底的连接电极19形成在半导体1的底侧。
如本例中的半导体器件，是一个带有漏扩展区的p沟道MOST晶体管，也称为EPMOS。掺杂浓度为5×1014原子/cm3的p型硅衬底10（电阻率约为30Ω·cm）用作半导体。表面区3包括一个外延形成于半导体上的掺杂浓度为3×1015原子/cm3而厚度为9μm（电阻率约为1.5Ωcm）的n型层。背栅接触区13的n型掺杂浓度为5×1015原子/cm2而源区4和漏区5的p型掺杂浓度为2×1015原子/cm2。漏扩展区6的掺杂浓度为6×1012原子/cm2。分隔区12的p型掺杂浓度为1×1015原子/cm2。沟道区7的宽度为50μm而长度为8μm。漏扩展区6的长度为18μm而宽度为50μm。
这种半导体器件特别适用于高压开关元件，例如汽车、电视机和音频功率放大器的应用。可以采取各种各样的方法来改善场效应晶体管的漏击穿电压，用以降低有雪崩击穿危险的那些位于表面或邻近表面处的电场强度。
这种导电类型与重掺杂漏区5相同而掺杂浓度低于漏区5的漏扩展区6，如上所述是形成在半导体器件中的栅电极8和较重掺杂的漏区5之间的。当相对于源和栅电极14和8，向漏电极15上加以高压时，靠近沟道区7边缘的电场被漏扩展区6降低。由于这一降低，漏击穿只在高的漏电压下才发生。
再者，为提高漏击穿电压，可采用电连接于源区4或栅电极8的、漏扩展区6上方的场极电极16。场极电极16用台阶状绝缘层17（例如由氧化硅组成）同漏扩展区6隔开。在沟道7和漏扩展区6下面，衬底10和表面区3之间的边界处采用一个第一导电类型重掺杂层18，可以进一步提高漏击穿电压。场极电极16和重掺杂层18使漏扩展区6获得额外的耗尽。
带有场极电极16、掺杂浓度为3×1015原子/cm2的埋层18并带有掺杂浓度为6×1012原子/cm2的连续性漏扩展区6的上述EPMOS，其漏击穿电压为45V，12V栅压时的导通电阻为4000Ω。如果在实践中要求更高的漏击穿电压值，可降低漏扩展区6的掺杂浓度，这是由于漏扩展区6的较轻掺重会引起漏扩展区6的完全耗尽。这种轻掺杂会引起高的漏扩展区6电阻，同时需要额外的掺杂步骤来实现漏扩展区6的轻掺杂。
根据本发明，漏扩展区的几何形状不同于已知的漏扩展区6，前者包含多个第二导电类型的区域25，这些区域从沟道7延伸到漏区5、宽度为26而掺杂浓度要使表面区3和漏扩展区6之间的阻塞pn结28上的电压差升高时，在漏击穿发生之前漏扩展区6至少要局部地完全耗尽。根据本发明的方法，可能选择区域25的数目和宽度26作为器件的附加参数。
估计本发明器件中区域25的耗尽同时发生在纵向（即贯穿表面2）从区域的下边开始以及横向（即平行于表面2）从区域的侧面30开始。由于这种所谓的多维耗尽，在区域25掺杂水平较高时仍能发生完全耗尽，以致靠近漏扩展区6的电场保持较低从而获得较高的漏击穿电压。由于区域25中掺杂较重，器件的导通电阻就较低。
图3示出了第一实施例，其中区域25的宽度26约等于漏扩展区6的深度27，而掺杂浓度从区域25的中央向各区25的边缘28减小。可以用较简单的方法来制作区域25而无需额外的工艺步骤：在漏扩展区6的掺杂步骤中形成一个带有区域25的漏扩展区以替代连续性漏扩展区6。为此用光掩模来确定漏扩展区6就足够。在此例中，漏扩展区可分为例如六个区域25（见图1）。这样，就以已知的方法由通过用光掩模方法制得的窗口的离子注入和扩散形成了漏扩展区6。此例中的窗口的宽度为3μm，窗口之间的间距为6μm。区域25则用通过窗口进行离子注入使区域25中达到约6×1012原子/cm2的方法来形成。
这一掺杂原子浓度使得有可能采用CMOS（互补MOS）中对p阱进行掺杂的工艺来对漏扩展区6的区域25进行掺杂。离子注入之后，在1150℃进行6小时的热处理。扩散之后，各区域25的宽度约为6μm而深度约为5μm。在掺杂原子横向和纵向扩散开之后，区域25中的掺杂水平较低，而且掺杂浓度向区域25的边缘28降低。低的掺杂水平使漏击穿电压降低，因而在标准的掺杂步骤（注入较大量的掺杂原子）中提供附加的可能性来获得击穿电压较高的器件。器件的导通电阻只轻微地受扩散影响。
区域25可以大致地彼此相靠，如图4所示。在漏扩展区6的这种形状中，半导体的表面区2得到了最佳利用。区域25之间较小的间距已引起多维耗尽并使漏击穿电压得到改善。
当带有连续性漏扩展区6的晶体管同带有含区域25的漏扩展区的晶体管进行比较时，设区域25和连续区6中的掺杂浓度相等，则本发明的器件具有较高的漏击穿电压而且电阻的增加较小。根据上述本发明的半导体器件在导通电阻约为5600Ω时的击穿电压为140V。比之已知的晶体管漏击穿电压提高了三倍多，而导通电阻只上升了40%。当带有掺杂浓度较低的连续漏扩展区6的晶体管同带有含掺杂浓度较高的区域25的漏扩展区的晶体管进行比较时，在同一漏击穿电压下，本发明的器件的电阻低得多。
图5和6示出了另一实施例中区域25的宽度26如何从沟道区7向漏区5增加。这一实施例提供了一个优点，即比之区域25宽度恒定为26的情况，漏击穿电压可增加。由于区域25的宽度26从沟道区7向漏区5增加，电场分布就更均匀，以致电场的最大值降低因而击穿发生在更高的电压下。另一个优点是由于区域25的宽度26的增加使得区域25的电阻比区域25的宽度26恒定时的为小，从而使晶体管的导通电阻变小。区域的宽度26可以如图5所示从沟道区7连续地增加，也可以如图6所示台阶增加。用光刻技术可容易地实现这一最后实施例。在图5和6的例子中，区域25在邻接沟道7处的宽度为6μm，而在离沟道的水平距离为10μm处各区域25彼此接触。漏扩展区6的总长度为18μm。比之带恒定宽度区域25的情况，漏击穿电压提高而导通电阻下降。
图1示出了一个实施例，其中区域25用邻近沟道区7的漏扩展区6部分内的第二导电类型区域31互连起来。沟道区7是一个连续区域，亦即电流可在沟道7的整个宽度内从源区4流向漏扩展区6而不仅仅是从区域25处流过，这就得到更陡的晶体管。这意味着栅电压改变时流过带有区域31的晶体管的电流改变大于无区域31的晶体管。为实现高的漏击穿电压，可能希望采用额外的手段来耗尽邻近沟道区7的漏扩展区6，特别是区域31、这就是通过在漏扩展区6的这部分之上采用场极电极16。场极电极用绝缘层17（此例中由氧化硅构成）同漏扩展区6分开并电连接到源。也可以利用衬底10和表面区3之间边界上的第一导电型重掺杂层18来耗尽这部分漏扩展区6。这一重掺杂层18于是延伸到邻近沟道7的漏扩展区6的部分31以下。邻近沟道区7的漏扩展区6的部分31则从重掺杂区18被额外地耗尽，以致在漏扩展区6的这一部分31中不发生过早的击穿。在图1的例子中提供了一个掺杂浓度为6×1012原子/cm2的区域31。
图1、5和6示出了另一个实施例，其中各区域25用邻近漏区5的部分漏扩展区6中的第二导电型区域29互连起来。漏扩展区6和漏区5之间的过渡变缓，以致电场不出现尖峰因而可实现更高的漏击穿电压。当区域29比漏扩展区6的其余部分掺杂更重时，这一实施例可得到特别高的漏击穿电压。这种重掺杂可在制作区域25过程中用简单的方法来实现。由于制作区域25过程中的扩散，区域25中掺杂原子的平均浓度较低。扩散引起的掺杂原子损失在连续区域29中小得多，以致区域29的掺杂水平比区域25高。在图1、5和6的例子中，提供了宽度为8μm的区域29。比之不带区域29的晶体管，这一区域29提高了本发明晶体管的漏击穿电压并降低了导通电阻。
本发明不局限于上述实施例。例如也可采用硅以外的半导体材料。表面区3不仅可用外延生长来形成，也可用扩散或注入来形成。例子中各区域的导电类型也可以反过来。

Claims (6)

1、一种半导体中含有一个第一导电类型表面区的半导体器件，此表面区邻接于一表面且其中形成有一个场效应晶体管，而场效应晶体管带有隔离栅、在表面区中带有与第一导电类型相反的第二导电类型的源区和漏区以及一个第二导电类型的漏扩展区，它邻接于漏区和表面，掺杂浓度比漏区低，并沿源区的方向纵向延伸、有一个位于漏扩展区和源区之间的第一导电型沟道区、并且有一个位于沟道区之上而用隔离层同沟道区分开的栅电极。这种半导体器件的特征是：漏扩展区包含多个第二导电类型的区域，这些区域从沟道区向漏区延伸，其宽度和掺杂浓度要使表面区和漏扩展区之间的阻塞pn结上的电压差上升时，在发生漏击穿之前，漏扩展区至少局部地完全耗尽。
2、如权利要求1所述的半导体器件，其特征是各区域的宽度约等于漏扩展区的深度，而掺杂浓度从各区的中央向边缘降低。
3、如前面任一权利要求所述的半导体器件，其特征是区域的宽度从沟道区向漏区增加。
4、如前面任一权利要求所述的半导体器件，其特征是各区域用邻近沟道区的那部分漏扩展区中的第二导电类型的一个区域互连起来。
5、如前面任一权利要求所述的半导体器件，其特征是各区域用邻近漏区的那部分漏扩展区中的第二导电类型的一个区域互连起来。
6、如前面任一权利要求所述的半导体器件，其特征是区域中的掺杂原子的数量约为6×1012原子/cm2。
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JP2599493B2 (ja) * 1990-08-27 1997-04-09 松下電子工業株式会社 半導体装置
CN1019720B (zh) * 1991-03-19 1992-12-30 电子科技大学 半导体功率器件

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1079996C (zh) * 1995-12-02 2002-02-27 Lg半导体株式会社 高压金属氧化物硅场效应晶体管结构
CN1307725C (zh) * 2003-03-11 2007-03-28 因芬尼昂技术股份公司 场效应晶体管
US7202529B2 (en) 2003-03-11 2007-04-10 Infineon Technologies Ag Field effect transistor
CN101529589B (zh) * 2006-07-28 2012-09-19 万国半导体股份有限公司 具有底部源极的横向式扩散金属氧化物场效应晶体管的结构及其方法
CN103681855A (zh) * 2012-08-31 2014-03-26 爱思开海力士有限公司 半导体器件
CN103730503A (zh) * 2012-10-12 2014-04-16 三菱电机株式会社 横向高耐压晶体管及其制造方法
CN103730503B (zh) * 2012-10-12 2016-08-17 三菱电机株式会社 横向高耐压晶体管及其制造方法

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JPH0738097A (ja) 1995-02-07
HU9402061D0 (en) 1994-09-28
HUT68222A (en) 1995-06-28
BE1007283A3 (nl) 1995-05-09
AU6742494A (en) 1995-01-19
US5473180A (en) 1995-12-05
HU217491B (hu) 2000-02-28
EP0634798A1 (en) 1995-01-18
AU679748B2 (en) 1997-07-10
CA2127645A1 (en) 1995-01-13

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