CN1111834C - Liquid crystal indicator with display mode mapping function - Google Patents
Liquid crystal indicator with display mode mapping function Download PDFInfo
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- CN1111834C CN1111834C CN96111781A CN96111781A CN1111834C CN 1111834 C CN1111834 C CN 1111834C CN 96111781 A CN96111781 A CN 96111781A CN 96111781 A CN96111781 A CN 96111781A CN 1111834 C CN1111834 C CN 1111834C
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Abstract
The invention discloses a kind of liquid crystal indicator (LCD), comprising: microcomputer, storage piece, dot matrix clock generating circuit, horizontal output generation circuit, status signal circuit and storage and control circuit with display mode mapping function.When the color of the VGA that resolution is low, SVGA pattern, level and vertical synchronizing signal were supplied with the LCD of XGA pattern, the frequency by making the dot matrix clock signal and the frequency of horizontal-drive signal improved, and image is presented on the whole image.
Description
Technical field
The present invention relates to liquid crystal indicator (LCD), more specifically to liquid crystal indicator with display mode mapping function.
Background technology
By the on-off element corresponding with each pixel each pixel is lighted separately or the active matrix liquid crystal display apparatus that extinguishes (ON/OFF) as shown in Figure 1, it comprises LCD control device 20 and LCD panel 30.
LCD drive unit 40 is housed in LCD panel 30, the simulating signal that LCD control device 20 will be provided by the main frame (host) 10 of personal computer and so on is transformed to the digital color signal, and produces horizontal output signal Vin and dot matrix clock signal (dot clock Signal) Dclk.Digital color signal, dot matrix clock signal and the horizontal output signal supply device LCD driving circuit of exporting respectively by LCD control device 20 40 in LCD panel 30.
With reference to Fig. 2, existing LCD control device 20 comprises phase-locked loop circuit (PLL) 21 and analog to digital converter (ADC) circuit 22.Phase-locked loop circuit (PLL) (hereinafter to be referred as the phase-locked loop) 21 is used for the input level synchronizing signal, produces horizontal output signal Hout and dot matrix clock signal Dclk; Analog to digital converter (ADC) circuit 22 will be converted to digital red, green, blue signal respectively by the simulation that main frame provides red (R), green (G), blue (B) signal, supply with LCD driving circuit 40.Above-mentioned horizontal output signal Hout is the signal corresponding with horizontal-drive signal Hsync, and the frequency of this horizontal output signal Hout is identical with the frequency of horizontal-drive signal Hsync.
On the contrary, because the characteristic of main frame, the polarity that is input to the horizontal-drive signal Hsync of phase-locked loop 21 might change, but the horizontal output signal Hout of above-mentioned phase-locked telegram in reply road 21 output predetermined polarity.
For example, have and the horizontal output signal Hout of negative polarity synchronously and among the LCD of the driving circuit 40 of work, even the horizontal-drive signal Htsync that positive polarity is provided by main frame is to phase-locked loop 21, the horizontal output signal hout of negative polarity still can be supplied with the driving circuit 40 of LCD in the phase-locked loop.Here, phase-locked loop 21 is made of phase detectors, voltage controlled oscillator (VCO), frequency divider (divider) and generator output signal (output generator) as everyone knows.
Usually, LCD has only single display mode, such as: video graphics array (Video GraphicsArray, abbreviation: VGA), hypervideo pattern matrix (super VGA, abbreviation: SVGA) or expanded images array (Extended Graphics Array, abbreviation: XGA) a kind of in the pattern.
Therefore, supporting that total resolution (total resolution) is the LCD of 1344 * 806 XGA pattern, for example, if it is the signal of 420 * 499 VGA pattern that total resolution is provided, then as shown in Figure 3, the a part of regional A display image (image) on the LCD of above-mentioned XGA picture only, the area B beyond it is display image not.With total resolution be the signal of 1056 * 628 SVGA pattern when supplying with the LCD of XGA too.
This shows, there is such problem in prior art, promptly, when low resolution display mode signal (low resolution display mode signals) being supplied with the LCD that supports high resolving power display mode (high resolution display mode) by main frame, a part of display image at picture.
Summary of the invention
The objective of the invention is to, even provide the signal of a kind of input low resolution display mode also can be at the LCD of view picture picture display image.
Another object of the present invention is to, the control device of a kind of LCD is provided, the signal transformation that it has the low resolution display mode is the function of supporting the signal of LCD high resolving power display mode.
In order to achieve the above object, according to feature of the present invention, liquid crystal indicator comprises: the control device of LCD and the drive unit of LCD.Horizontal-drive signal and vertical synchronizing signal that described control device input is provided by main frame, judge the display mode that main frame is supported according to its input signal, output has horizontal output signal and the dot matrix clock signal with the pattern respective frequencies of judging, the simulation chrominance signal that is provided by main frame is transformed to the digital color signal that is suitable for described LCD panel display mode; Described drive unit is imported above-mentioned horizontal output signal and above-mentioned dot matrix clock signal, drives above-mentioned LCD panel.The signal transformation of the display mode that above-mentioned main frame is supported is the display mode signal of this LCD panel.
In this device, above-mentioned LCD control device comprises: memory device, dot matrix clock signal generating apparatus, horizontal output generating means and the storage and control device of display mode judgment means, the above-mentioned digital color signal of storage.Described display mode judgment means is imported above-mentioned horizontal-drive signal and above-mentioned vertical synchronizing signal, according to the display mode that the above-mentioned main frame of its input-signal judging is supported, and the data-signal of the above-mentioned horizontal output signal waveform of output expression; Described horizontal output signal is corresponding to the pattern of judging the pattern shows signal that is the display mode supported of the above-mentioned main frame of expression; Described dot matrix clock signal generating apparatus is imported above-mentioned horizontal-drive signal, produce the write operation be used for above-mentioned storing apparatus write the dot matrix clock signal and be used for above-mentioned storing apparatus read operation read the dot matrix clock signal; Described horizontal output generating means responds above-mentioned vertical synchronizing signal, and imports above-mentioned data-signal, with above-mentioned to read the dot matrix clock signal synchronous, produces above-mentioned horizontal output signal; Described storage and control device is imported above-mentioned horizontal-drive signal and the above-mentioned dot matrix clock signal of writing, and controls the write operation of above-mentioned storing apparatus, also imports above-mentioned horizontal output signal and the above-mentioned dot matrix clock signal of reading, and controls the read operation of above-mentioned storing apparatus.
In this device, above-mentioned storing apparatus comprises: store the 1st to the 3rd storage piece of above-mentioned digital color signal respectively and utilize above-mentioned storage and control device to control and will write the output selection device that the above-mentioned above-mentioned chrominance signal that respectively stores piece is selected output.
In this device, above-mentioned each storage piece comprises 3 row memories at least.
In this device, above-mentioned storage and control device comprises: device for marking, storage device for selection controlling and storage management device.Described device for marking is used to produce a plurality of signs, and these signs are illustrated respectively in the above-mentioned row memory that carries out above-mentioned write operation and read operation in the above line memory of piece that respectively stores by predefined procedure; Described storage device for selection controlling is used to respond the above-mentioned a plurality of signs that provided by above-mentioned device for marking, produce the 1st and the 2nd storage and select signal, so that select respectively to carry out the row memory of above-mentioned write operation and read operation, but prevent to select a row memory to carry out above-mentioned write operation and above-mentioned read operation simultaneously; The storage management device is used to import above-mentioned horizontal-drive signal, above-mentioned horizontal output signal, above-mentioned dot matrix clock signal and the above-mentioned dot matrix clock signal of reading write, utilize the control of the selection control module that above-mentioned storage device for selection controlling controls, management is for the access that writes the memory that carries out with read operation of above-mentioned storing apparatus.
In this device, above-mentioned storage device for selection controlling comprises selects the error monitoring device, the information that it provides according to above-mentioned device for marking, before the write operation of the row memory in being in write operation finishes, whether prediction above line memory selects following read operation, when being judged as read operation below will selecting of above line storage, just producing to read and indicate that control signal makes above-mentioned reading indicate that generating means does not enable (disable).
In this device, above-mentioned storage device for selection controlling comprises loop error monitoring arrangement and control signal output unit, described loop error monitoring arrangement when the sequential (timing) of above-mentioned horizontal-drive signal and above-mentioned horizontal output signal is consistent, produce make above-mentioned read that the sign generating means enables (enable) another read the control signal of sign; Described control signal output unit is used for above-mentioned any one of reading the sign control signal supplied with the above-mentioned sign generating means of reading selectively.
In this device, above-mentioned storage management device comprises: write/read-out control device, address producing device, address selection device and dot matrix clock selecting device.The response of described writing/read-out control device is selected signal by above-mentioned the 1st memory that the storage device for selection controlling provides, and the writing and read operation of row memory of piece respectively stored in control; Described address producing device is imported above-mentioned horizontal-drive signal, above-mentioned horizontal output synchronizing signal, above-mentioned dot matrix clock signal and the above-mentioned dot matrix clock signal of reading write, and what produce the read operation be used for memory and write operation reads and write the address; Described address selection device utilizes above-mentioned writing/read-out control device to control, and writes and reads the address and supply with the above-mentioned above line memory that respectively stores piece respectively selectively above-mentioned; Described dot matrix clock selecting device utilizes above-mentioned writing/read-out control device to control, and writes and reads the dot matrix clock signal and supply with the above-mentioned above line memory that respectively stores piece respectively selectively above-mentioned.
In this device, above-mentioned LCD panel is supported the XGA pattern, and above-mentioned LCD control device is imported the signal of VGA pattern, the signal of above-mentioned XGA pattern is supplied with the drive unit of above-mentioned LCD.
In this device, above-mentioned LCD panel is supported the XGA pattern, and the signal of the control device input SVGA pattern of above-mentioned LCD is supplied with above-mentioned LCD drive unit with the signal of above-mentioned XGA pattern.
Chrominance signal, level and vertical synchronizing signal when low-resolution mode, when supplying with the LCD of XGA pattern, image can be shown on the whole image of LCD, so that the frequency of the frequency of dot matrix clock signal and horizontal synchronization improved, thereby the along continuous straight runs vertical direction has been expanded the viewing area of picture.
Description of drawings
Below in conjunction with accompanying drawing LCD control device of the present invention is described in detail.In the accompanying drawing:
Fig. 1 is the block scheme of the basic structure of expression active matrix liquid crystal display apparatus;
Fig. 2 is the block scheme of the existing liquid crystal indicator circuit structure of expression;
Fig. 3 A, 3B are when being illustrated in the liquid crystal indicator of the signal of VGA pattern supply XGA pattern, according to the picture of the shown image-region of prior art;
When Fig. 4 A, 4B are illustrated in the liquid crystal indicator of the signal of VGA pattern supply XGA pattern, the picture of the image-region that the present invention is shown;
Fig. 5 is the block scheme of expression liquid crystal indicator circuit structure of the present invention;
Fig. 6 is the block scheme of the circuit structure around the expression storage piece shown in Figure 5;
Fig. 7 is the circuit diagram of the embodiment of expression output select circuit shown in Figure 5;
When Fig. 8 represents that the signal of VGA pattern is supplied with liquid crystal indicator of the present invention, in each storage piece, the order that each row memory carries out write operation and carries out read operation;
When Fig. 9 represents that the signal of VGA pattern is supplied with liquid crystal indicator of the present invention, in each storage piece, the order that each memory carries out write operation and carries out read operation;
Figure 10 is the circuit diagram of expression horizontal output generation embodiment of circuit shown in Figure 5;
Figure 11 is the sequential chart of vertical synchronizing signal and horizontal-drive signal;
Figure 12 is the circuit diagram of the embodiment of expression status signal circuit shown in Figure 5;
Figure 13 is the circuit diagram that expression memory shown in Figure 5 is selected the embodiment of control circuit;
Figure 14 is a sequential chart, and the selection course of selecting the row memory of read operation according to write operation is described;
Figure 15 is the circuit diagram of comparatively ideal embodiment in the expression storage management circuit shown in Figure 6.
Embodiment
At first, under the signal of VGA pattern is input to situation in the LCD control device of the present invention, the frequency of vertical synchronizing signal Vsync remains unchanged, the frequency of the frequency of horizontal-drive signal Hsync and dot matrix clock signal Dclk increases by 0.6 training as table 1, in view of the above, the image on the LCD picture almost shows with the resolution of XGA pattern.
＜table 1 〉
| Before the conversion | After the conversion | |||
| Resolution is counted * line number | Horizontal frequency KHz | Vertical frequency Hz | Horizontal frequency KHz | Resolution is counted * line number |
| 640×350 (800×440) | 31.5 | 70.0 | 50.40 | 1024×560 (1280×718) |
| 640×480 (800×525) | 31.5 | 60.0 | 50.40 | 1024×768 (1280×840) |
| 640×400 (800×449) | 31.5 | 70.0 | 50.40 | 1024×640 (1280×718) |
| 640×480 (800×520) | 37.87 | 72.8 | 60.59 | 1024×768 (1331×832) |
The resolution of table 1 is resolution (active resolution) commonly used, and the value in () is total resolution (total resolution).
As table 1, for example: owing to be 640 * 480 resolution conversion 1024 * 768 resolution, so the ratio of the resolution after the resolution before the conversion and the conversion is 1: 1.6, according to this mapping mode, be transformed to the chrominance signal of going corresponding to 8 corresponding to the 5 red, green, blue chrominance signals of going.
Be input to situation in the LCD control device of present embodiment at the signal of VGA pattern below, the frequency of vertical synchronizing signal Vsyne is constant, the frequency of the frequency of horizontal-drive signal Hsync and dot matrix clock signal Dclk increases by 0.25 times as table 2, in view of the above, as shown in Figure 4, the image on the LCD picture shows with the resolution of XGA pattern basically.
＜table 2 〉
| Before the conversion | After the conversion | |||
| Resolution is counted * line number | Horizontal frequency KHz | Vertical frequency Hz | Horizontal frequency KHz | Resolution is counted * |
| 800×600 (1024× 625) | 35.16 | 56.2 | 43.95 | 1000×750 (1280×781) |
| 800×600 (1056× 628) | 37.88 | 60.3 | 47.35 | 1000×750 (1320×785) |
| 800×600 (1040× 666) | 48.08 | 72.0 | 60.10 | 1000×750 (1300×832) |
Resolution in the table 2 is resolution commonly used, and the value in () is a total resolution.
As table 2, for example: 800 * 600 resolution conversion is 1000 * 750 resolution, so the ratio of the resolution after the resolution before the conversion and the conversion is 1: 1.28.But convenient for conversion, the ratio of the resolution after the resolution before the conversion and the conversion changes 1: 1.25 into, according to this mapping mode, is transformed to chrominance signals corresponding to 5 row corresponding to the chrominance signals of 4 row.
Fig. 5 represents the signal transformation of VGA or SVGA pattern to be the circuit structure of LCD control device of the present invention of the signal of XGA pattern.
With reference to Fig. 5, be input to the microcomputer 100 from the horizontal-drive signal Hsync and the vertical synchronizing signal Vsync of main frame output, microcomputer 100 is according to horizontal-drive signal Hsync and vertical synchronizing signal Vsync, differentiate the display mode that main frame supports (below be called main frame support display mode), and produce its result's of expression the 1st and the 2nd pattern shows signal MD1, MD2.
When the support display mode of above-mentioned main frame is SVGA, by the 1st pattern shows signal MD1 of microcomputer 100 output high level and the 2nd pattern shows signal MD2 of high level; When the display mode of main frame support is VGA, the 2nd pattern shows signal MD2 of the 1st pattern shows signal MD1 of output low level and high level; When the display mode of main frame support is XGA, by the 2nd pattern shows signal of microcomputer 100 output low levels.
And, also providing the 1st data-signal TA and the 2nd data-signal PW by above-mentioned microcomputer 100, the former represents counting as each cycle of the horizontal output signal Hout of the horizontal-drive signal of XGA pattern; The latter represents the pulse width of above-mentioned horizontal output signal Hout.
Dot matrix clock generating circuit 200 is made of 2 phase-locked loops (210,220) respectively, phase-locked loop 210,220 produce respectively be used for memory write operation and read operation write, read dot matrix clock signal W-Dclk, R-Dclk.
Horizontal output generation circuit 300 utilizes the vertical synchronizing signal Vsync that provided by main frame and the above-mentioned the 1st and the 2nd data-signal TA, the PW that are provided by microcomputer 100 and produce horizontal output signal Hout, at this moment, above-mentioned horizontal output signal Hout and horizontal-drive signal Hsync (following with " Hin " expression) produce synchronously.
As shown in Figure 5, the inventive system comprises the memories 400 with three storage piece 410as, 410b, 410cs and the output selection parts 420 corresponding with red, green, blue (R, G, B) signal difference, each among storage piece 410a, 410b, the 410c is made of the row memory more than three (linememory) at least.
The output of horizontal-drive signal Hin and dot matrix clock generating circuit 200 and horizontal output generation circuit 300 all provides via the storage and control circuit of selecting control circuit 600 and storage management circuit 700 to constitute by status signal circuit 500, storage.This storage and control circuit input level synchronizing signal Hin and write dot matrix clock signal W-Dclk controls the write operation of above-mentioned memory 400, and input level output signal Hout and read dot matrix clock signal R-Dclk, the read operation of control memory 400.
Status signal circuit (flag circuit) 500 in each storage piece, provides marking signal, and these marking signals represent that each row memory carries out the predefined procedure of write operation and read operation.
Storage selects control circuit (memory selection control circuit) 600 to provide memory to select signal W-Se1, R-Se1, so that the row memory that above-mentioned write operation and read operation are carried out in selection respectively; But any one row memory that prevents from respectively to store in the piece carries out write operation and read operation simultaneously.
Storage management circuit 700 is managed the access of memory according to the instruction of storage selection control circuit 600, and the access of described memory is carried out for writing with read operation of row memory of each storage piece.
Describe the embodiment of LCD control device of the present invention with reference to the accompanying drawings in detail.
As shown in Figure 5, memory 400 comprises: 3 storage piece 410a, 410b, 410c and the output select circuit 420 that is made of 33 * 1 traffic pilot 420a, 420b, 420c.Described 3 traffic pilot 420a, 420b, 420c store piece 410a with three, 410b, 410c are corresponding respectively.
Fig. 6 represents the detailed structure of storage piece 410a, 410b, 410c, traffic pilot 420a, 420b, 420c and storage management circuit 700 shown in Figure 5, unshowned two other storage piece is the same with the storage piece shown in the above-mentioned figure among Fig. 6, also is connected with memory management circuit 700.
With reference to Fig. 6, each stores piece 410a, 410b, 410c is made of 3 row memory LM0, LM1, LM2, and each row memory has the memory capacity (storagecapacity) of 1344 words * 8 (bits) at least.
Fig. 7 represents the embodiment of output select circuit shown in Figure 5 420, with reference to Fig. 7,3 input terminals separately of 33 * 1 traffic pilot 420a, 420b, 420c connect row memory LM0, the LM1 that respectively stores in the piece, the data output end (not shown) of LM2 respectively.
The memory of reading that each traffic pilot response selects control circuit 600 to provide by storage is selected signal R_Se10, R_Se11, select a data output from the data of row memory LM0, LM1, the LM2 input of each storage piece, output Rout, the Gont of these traffic pilots 420a, 420b, 420c, Bout supply with the driving circuit of LCD.
Refer again to Fig. 6, storage management circuit 700 comprise write/read-out control part divides 710, part 720, address selection part 730 and dot matrix clock selecting part 740 take place in the address, write/the storage of writing that read-out control part divides 710 responses to select control circuit 600 to provide by storage selects signal W-Se1, and the writing and read operation of row memory of piece respectively stored in control.
Part 720 level of response synchronizing signal Hin and horizontal output signal Hout take place in the address, produce be used for memory read operation and memory write operation write and read address signal R-Add, W-Add; Address selection part 730 by write/read-out control part divide 710 control, will write and read address signal W-Add, R-Add selectively and supply with row memory LM0, LM1, the LM2 that respectively stores piece respectively.
Dot matrix clock selecting part 740 by write/read-out control part divide 710 control, will write and read dot matrix clock signal W-Dclk, R-Dclk selectively and offer row memory LM0, LM1, the LM2 that respectively stores piece respectively.
When the signal of the lower resolution model of the resolution of LCD is supplied with the LCD Controller device of present embodiment by main frame, each store writing of piece 410a, 410b, 410 row memory LM0, LM1, LM2 and readout as follows:
About each chrominance signal, the write operation of memory and horizontal-drive signal Hin carry out synchronously, and the read operation of memory and horizontal output signal Hont carry out synchronously.The write operation of memory is from the row memory LM0 of each storage piece, and the read operation of memory is from the row storage LM2 of each storage piece, and the row memory that is used for respectively storing the storage piece of the writing of piece/read operation is selected by (inrotation) in turn.
But carve at a time, when being in row memory in the ablation process and having read operation to require, the row memory that has so just finished readout carries out read operation once more.
When Fig. 8 represents the LCD of the present embodiment of the signal supply support XGA pattern of VGA pattern, in each storage piece, the order that each row memory carries out write operation and carries out read operation.
With reference to Fig. 8, the chrominance signal of 5 row VGA patterns is transformed to the chrominance signal of 8 row XGA patterns, after signal transformation begins, carries out write operation respectively in row memory LM0, carries out read operation in row memory LM2.
After the read operation of row memory LM2, must carry out the read operation of row memory LM0, as shown in Figure 8, at the read operation t1 finish time of row memory LM2, row memory LM0 is in the write operation process.
Therefore, after the read operation of row memory LM2 finished, the read operation of above line memory LM2 repeated once again.At the read operation t2 finish time of the 2nd time row memory LM2, row memory LM1 is among the write operation process.
Therefore, the 2nd read operation one of row memory LM2 finishes, and just carries out read operation for the third time at row memory LM0.After row memory LM0 is through three read operations, just prepare to carry out the write operation of row memory LM1, but after the 4th time the memory read operation t3 zero hour, because the write operation of row memory LM1 will continue, so after memory read operation for the third time finished, the read operation of above line memory LM0 repeated once again.
After, as described above, should make and write and read operation is unlikely in same row memory simultaneously and takes place, in view of the above, at moment t4, finish the write operation of the 5th memory, and finish the read operation of No. the 8th memory, in view of the above, when respectively storing piece corresponding to the chrominance signal input of 5 row, this storage piece output this means that corresponding to the chrominance signal of 8 row the input signal of this storage piece and the ratio of output signal are 1.6, as a result, be transformed to the signal of XGA pattern as the signal of the VGA pattern of storing the piece input signal.
When Fig. 9 represents the liquid crystal indicator of the signal supply present embodiment of SVGA pattern, in each storage piece, the order that each row memory carries out write operation and carries out read operation.
With reference to Fig. 9, when importing by each storage piece, according to writing/reading method of above-mentioned memory, from the chrominance signal of this storage piece output corresponding to 5 row corresponding to the chrominance signal of 5 row, in view of the above, the chrominance signal of the SVGA pattern of 4 row is transformed to the chrominance signal of the XGA pattern of 5 row.
Figure 10 represents the embodiment of horizontal output generation circuit 300, and with reference to Figure 10, horizontal output generation circuit 300 comprises 301, two comparers 302,303 of down counter (down counter) and JK flip-flop 304.
The 1st data-signal TA of 11 bits that down counter 301 will be provided by microcomputer 100＜10: 0〉load (load) with vertical synchronizing signal Vsync, at each rising edge of reading dot matrix clock signal R-Dclk the value of this loading is counted.
The 1st data-signal TA that provided by microcomputer 100＜10: 0 just automatically is provided after " 0 " above-mentioned down counter 301 its output valves 〉.Comparer 302 was the 1st data-signal TA＜10: 0〉when identical with the output of down counter 301, the output high level signal, at this moment, the reversed-phase output Q of JK flip-flop 304 output low level signal as shown in figure 11.
Afterwards, whenever low 3 outputs of down counter 301 and the 2nd data-signal PW＜2: 0〉when identical, comparer 303 is just repeatedly exported high level signal, comparer 302 is only the 1st data-signal TA＜10: 0〉just export the signal of high level when packing (load) down counter 301 into, so as shown in figure 11, low level is kept in the output of JK flip-flop 304.
Figure 12 represents the embodiment of status signal circuit 500 shown in Figure 5.With reference to Figure 12, generation is used for marking signal Fa, the Fb of write operation, the sign that writes of Fc circuit 510 takes place and produce marking signal Fd, the Fe, the reading of Ff that are used for read operation to indicate that circuit 520 takes place has identical structure, that is, sign takes place that each includes in the circuit 510,520: with door and the circulating register (rotate shifter regisger) that is made of three d type flip flops.
Horizontal-drive signal Hin supplied with write sign circuit 510 and input end door 511 take place, horizontal output signal Hout is supplied with read sign circuit 520 and input end door 521 take place.
The enable signal (Enable) of the high level effective (active high) of each sign generation circuit 510,520 and low level effectively the reset signal Reset of (active low) are imported respectively by microcomputer 100.Described reset signal Reset is supplied with the set end of trigger 512,522 and the reset terminal of other trigger 513,514,523,524 respectively.
Therefore, when above-mentioned reset signal Reset was low level, trigger 512,522 was SM set mode respectively, other trigger 513,514,523,524 is reset mode respectively, at this moment, marking signal Fa and Ff are high level, and other marking signal Fb, Fc, Fd, Fe are low level.
When enable signal (Enable) be high level, when above-mentioned reset signal Reset is high level, in the forward position of horizontal-drive signal Hin and horizontal output signal Hout (loaing edge), the output that circuit 510,520 takes place sign is recycled displacement (rotate shift) respectively, in view of the above, in each storage piece, horizontal-drive signal Hin and each motor synchronizing of horizontal output signal Hout, and circulation is specified the row memory that writes usefulness and is read the row memory of usefulness respectively.
Figure 13 represents the embodiment of storage selection control circuit 600 shown in Figure 5.With reference to Figure 13, storage selects control circuit 600 to comprise: select error monitoring part (selection error supervisor) 610, loop error monitor portion (cyclic error supervisor) 620 and control signal output 630.
Select error monitoring part 610 to constitute: the phase inverter 611 that makes horizontal output signal Hout upset by following elements; With the output of this phase inverter 611 synchronously, receive and read marking signal Ff, Fd, Fe and its d type flip flop that latchs 612,613,614; More above-mentioned read marking signal Ff, fd, Fe and write marking signal Fa, Fb, Fc whether identical with door 615,616,617 and rejection gate 618.
As shown in figure 13, write marking signal Fc and Fb and be used separately as and write memory and select signal W-Se10 and W-Se11, be used separately as and read memory and select signal R-Se10 and R-Se11 and read marking signal Ff and Fe.
The memory that writes by monitor portion 610 output is selected signal W-Se10 and W-Se11 and is read memory and select signal R-Se10, R-Se11 to supply with memory management circuit 700 and output select circuit 420 respectively.
Table 3 and table 4 are represented respectively to select signal W-Se10, W-Se11 and read the logic level that memory is selected signal R-Se10, R-Se11 according to writing memory, and that selects respectively in each storage piece writes memory and read memory.
＜table 3 〉
| W_Se11 | W_Se10 | Write the row memory of usefulness |
| L | L | LM0 |
| H | L | LM1 |
| L | H | LM2 |
＜table 4 〉
| R_Se11 | R_Se10 | Read the row memory of usefulness |
| L | L | LM0 |
| H | L | LM1 |
| L | H | LM2 |
On the contrary, row memory in selecting error monitoring part 610 and being in write operation is associated, before the write operation of above-mentioned memory finishes, next whether prediction select this memory to carry out read operation, when concluding that the above-mentioned memory of selection carries out ensuing read operation, just produce and read sign control signal RFC1, make to read to indicate that circuit 520 takes place does not enable (disable).
With reference to Figure 14, the selection of row memory that writes usefulness is by the decision of the rising edge of horizontal-drive signal Hin, and the selection of the row memory of next read operation is by negative edge (falling edge) decision of horizontal output signal Hout.
For example, the row memory that carries out write operation at time section t1＜t＜t4 is by moment t1 decision, and the row memory that carries out read operation at time section t3＜t＜t5 is determined by moment t2.
At moment t2, when the row memory of next read operation is identical with the row memory in being in write operation, select error monitoring part 610 just to produce the low level sign control signal RFC1 that reads, in view of the above, read sign generation circuit 520 and do not enable (disable), ring shift does not take place in its output, its result, and the row memory that is just carrying out at present read operation will be used for carrying out following read operation again.
On the contrary, at moment t2, the row memory of next read operation is with the row memory that is just carrying out write operation when inequality, select error monitoring part 610 to produce reading of high level and indicate control signal RFC1, in view of the above, read sign generation circuit 520 and be enabled (enable) the output generation ring shift of foregoing circuit 520, its result, a row memory that is just carrying out the row memory back of read operation at present is used for carrying out following read operation.
As shown in figure 13, loop error monitor portion 620 is made of following several parts: the counter circuit that is made of d type flip flop 621,622,623; By with door 624 and or door 625, the 626 counting region control circuits that constitute (counting range control circuit); By the reset circuit that constitutes with door 627; And read the sign control circuit by what rejection gate 628 constituted.
The 1st pattern shows signal MD1 that 624,625,626 responses of counting region control circuit are provided by microcomputer 100, the output area of control counter circuit 621,622,623.
Reset circuit 627 inputs when the signal of XGA pattern is imported the LCD of this embodiment, reset above-mentioned counter circuit 621,622,623 by reset signal Reset and the 2nd pattern shows signal MD2 that microcomputer 100 provides respectively.Read 628 generations of sign control circuit and read sign control signal RFC2, indicate that circuit 520 takes place enables (enable) so that make to read.
LCD when VGA mode signal input present embodiment, when above-mentioned counter circuit 621,622,623 is output as " 5 ", and signal in input SVGA pattern, and above-mentioned counter circuit 621,622,623 is when being output as " 8 ", sign control signal RFC2 is read in above-mentioned control circuit 628 generations that enable of reading sign, indicates that circuit 520 takes place to enable so that make to read.
As mentioned above, loop error monitor portion 620 input be the signal of VGA pattern the time, above-mentioned counter circuit 621,622,623 is output as " 5 ", and the input be the signal of SVGA pattern the time, above-mentioned counter circuit 621,622,623 is output as " 8 ", why make and read sign and circuit 520 takes place force to enable work, be in order to make its horizontal-drive signal Hin consistent, thereby the device of present embodiment can be worked reliably with horizontal output signal Hout.
The output 630 of control signal by have two input ends and an output terminal or door 631 constitute, wherein, two input ends receive the output signal of selection error monitoring part 610 and the output signal of loop error monitor portion 620 respectively, and a described output terminal is connected with the Enable Pin of reading sign generation circuit 520.When the output signal of the output 630 of above-mentioned control signal is low level, reads sign circuit 520 disables (disable) take place.
Therefore, even this moment input level output signal Hout, ring shift does not take place in the output of reading sign generation circuit 520 yet, when the output signal of the output 630 of above-mentioned control signal is high level, reading sign generation circuit 520 is enabled, therefore, during horizontal output signal Hout input at this moment, read the output generation ring shift that circuit 520 takes place sign.
Figure 15 represents the desirable embodiment of memory management circuit 700 shown in Figure 6, with reference to Figure 14, write/read-out control part divides 710 to constitute by phase inverter 711,712,714,716 with door 713,715,717.
As shown in table 3, in each storage piece, at first, if W-Se10=" L ", W-Se11=" L ", but then row memory LM0 is a write state, other row memory LM1, LM2 are readable doing well.Secondly, if W-Se10=" L ", W-Se11=" H ", but then row memory LM1 is a write state, other row memory LM0, LM2 are readable doing well.At last, if W-Se10=" H ", W-Se11=" L ", but then row memory LM2 is a write state, other row memory LM0, LM1 are readable doing well.
Part 720 takes place and part 721 takes place and read the address part 722 takes place to constitute by writing the address in the address, and the former carries out initialization with horizontal-drive signal Hin and with to write dot matrix clock signal w-Dclk synchronous, generation is used for the address W-Add of write operation; The latter carries out initialization with horizontal output signal Hout, and with to read dot matrix clock signal R-Dclk synchronous, produces the address R-Add that is used for read operation.Part 721 takes place and reads the address part 722 to take place by adding counter (up-counter) formation in the above-mentioned address that writes.
Address selection part 730 is made of three 2 * 1 traffic pilot 731,732,733, to write and read two input ends that address W-Add, R-Add supply with each traffic pilot respectively, row memory LM0, LM1, the LM3 that respectively stores piece supplied with in the output of above-mentioned traffic pilot 731,732,733 respectively, with write/read-out control part divides outputs with door 713,715,717 in 710 to supply with the selection control end of above-mentioned traffic pilot 731,732,733 respectively.Write and read address W-Add, R-Add by write/read-out control part divide 710 selectively from each the storage piece row memory LM0, LM1, LM2 supply with respectively.
Two input ends that dot matrix clock signal W-Dclk, R-Dclk supply with each traffic pilot respectively be write, be read to dot matrix clock selecting part 740 also by three 2 * 1 traffic pilot 741,742,743 formations, will.
Row memory LM0, LM1, the LM3 that respectively stores piece supplied with in the output of above-mentioned traffic pilot 741,742,743 respectively, with write/read-out control part divides outputs with door 713,715,717 in 710 to supply with the selection control end of above-mentioned traffic pilot 741,742,743 respectively.Writing/Reading dot matrix clock signal W-Dclk, R-Dclk by write/read-out control part divides 710 to supply with row memory LM0, LM1, the LM2 respectively store piece selectively respectively.
Above, be that example is described the present invention with the chrominance signal of 8 bits, but the present invention is not limited thereto, to those skilled in the art, clearly, the chrominance signal of 16 bits or more bits also is applicable to the present invention.
According to the present invention, even the mode signal input LCD lower than the resolution of LCD pattern also can demonstrate image on the whole image of LCD.
Claims (14)
1, a kind of liquid crystal indicator comprises:
LCD (liquid crystal indicator) control device, horizontal-drive signal Hin and vertical synchronizing signal Vsync that its input is provided by main frame, judge the display mode that described main frame is supported according to these input signals, output has horizontal output signal Hout and the dot matrix clock signal R-Dclk with the pattern respective frequencies of being judged, and the simulation chrominance signal that is provided by above-mentioned main frame is transformed to digital color signal Rin, Gin, the Bin that is suitable for described LCD panel display mode;
The LCD drive unit is imported this drive unit with above-mentioned horizontal output signal and above-mentioned dot matrix clock signal, to drive above-mentioned LCD panel;
Wherein, this liquid crystal indicator is the display mode signal of this LCD panel with the signal transformation of the support display mode of described main frame;
Described LCD control device comprises:
Display mode judgment means (100), it imports above-mentioned horizontal-drive signal Hin and above-mentioned vertical synchronizing signal Vsync, judge the display mode that above-mentioned main frame is supported according to its input signal, the data-signal of the above-mentioned horizontal output signal waveform of output expression, described horizontal output signal is corresponding to the pattern of judging the pattern shows signal that is the display mode supported of the above-mentioned main frame of expression
Storing apparatus (400) is used to store above-mentioned digital color signal Rin, Gin, Bin,
Dot matrix clock signal generating apparatus (200), it imports above-mentioned horizontal-drive signal, produce be used for above-mentioned storing apparatus write operation write dot matrix clock signal W-Dclk and be used for above-mentioned storing apparatus read operation read dot matrix clock signal R-Dclk,
Horizontal output generating means (300), it responds above-mentioned vertical synchronizing signal, imports above-mentioned data-signal, and with above-mentioned to read the dot matrix clock signal synchronous, produces above-mentioned horizontal output signal,
Storage and control device, it imports above-mentioned horizontal-drive signal and the above-mentioned dot matrix clock signal of writing, and controls the write operation of above-mentioned storing apparatus, also imports above-mentioned horizontal output signal and the above-mentioned dot matrix clock signal of reading, and controls the read operation of above-mentioned storing apparatus;
Described storing apparatus comprises:
Be respectively applied for the 1st to the 3rd storage piece (410a, 410b, 410c) of the above-mentioned digital color signal of storage,
Utilize above-mentioned storage and control device to control and to write the output selection device (420) that the above-mentioned above-mentioned chrominance signal that respectively stores piece is exported selectively;
Described each of respectively storing piece comprises three row memories at least; With
Described storage and control device comprises:
Device for marking (500) is used to produce a plurality of signs, and these signs are illustrated respectively in the above-mentioned above line memory that respectively stores piece by predefined procedure will carry out the row memory of above-mentioned write operation and read operation,
Storage device for selection controlling (600), be used to the above-mentioned a plurality of marking signals that provide by above-mentioned device for marking are provided, produce the 1st and the 2nd storage and select signal W-Se1, R-Se1, so that select respectively to carry out the line storage of above-mentioned write operation and above-mentioned read operation, but prevent to select a memory; Carry out above-mentioned write operation and above-mentioned read operation simultaneously,
Storage management device (700), it imports above-mentioned horizontal-drive signal, above-mentioned horizontal output signal, above-mentioned dot matrix clock signal and the above-mentioned dot matrix clock signal of reading write, utilize above-mentioned storage device for selection controlling to control, management writes and read operation and the access of the memory that carries out for above-mentioned storing apparatus.
2, liquid crystal indicator as claimed in claim 1, wherein, the described data-signal by described display mode judgment means output comprises: represent the 1st data-signal TA of above-mentioned horizontal output signal period and the 2nd data-signal PW of the pulse width of the above-mentioned horizontal output signal of expression.
3, liquid crystal indicator as claimed in claim 2, wherein, described horizontal output generating means comprises:
Counter (301), it responds above-mentioned vertical synchronizing signal Vsync, loads above-mentioned the 1st data-signal TA, at above-mentioned each rising edge of reading dot matrix clock signal R-Dclk, the value of this loading is subtracted counting;
The 1st comparer, when above-mentioned the 1st data-signal TA is identical with the output of above-mentioned counter (301), the predetermined level signal of this comparer output;
The 2nd comparer, when the low n position of above-mentioned the 1st data-signal TA signal was identical with above-mentioned the 2nd data-signal PW, this comparer was exported above-mentioned predetermined level signal; And
JK flip-flop (304) is input to J input end and K input end with the output of above-mentioned the 1st comparer and the output of the 2nd comparer respectively.
4, liquid crystal indicator as claimed in claim 1, wherein, described device for marking comprises:
Write sign generating means (510), it is synchronous with above-mentioned horizontal-drive signal Hin, and what generation was used for above-mentioned write operation writes marking signal Fa, Fb, Fc;
Read sign generating means (520), it is synchronous with above-mentioned horizontal output signal Hout, and what generation was used for above-mentioned read operation reads marking signal Fd, Fe, Ff.
5, liquid crystal indicator as claimed in claim 4 wherein, describedly indicates that respectively generating means comprises circulating register.
6, liquid crystal indicator as claimed in claim 1, wherein, described storage device for selection controlling comprises selects error monitoring device (610), the information that it provides according to above-mentioned device for marking, before the write operation of the row memory in being in write operation finishes, whether prediction above line memory selects following read operation, when being judged as the read operation of above line memory below will selecting, just producing and read sign control signal RFC1 the above-mentioned sign generating means (520) of reading is not enabled.
7, liquid crystal indicator as claimed in claim 6, wherein, described storage device for selection controlling also comprises:
Loop error monitoring arrangement (620), when the sequential of above-mentioned horizontal-drive signal Hin and above-mentioned horizontal output signal Hout is consistent, just produce make above-mentioned read that sign generating means (520) enables another read sign control signal RFC2;
Control signal output unit (630), it supplies with the above-mentioned sign generating means (520) of reading selectively with above-mentioned any one of reading among sign control signal RFC1, the RFC2.
8, liquid crystal indicator as claimed in claim 6, wherein, described selection error monitoring device (610) comprising: with above-mentioned horizontal output signal Hout synchronously, read the latch means (612,613,614) that marking signal Ff, Fd, Fe latch with above-mentioned; And more above-mentioned marking signal Ff, Fd, Fe and the above-mentioned whether identical comparison means (615,616,617,618) of marking signal Fa, Fb, Fc that writes read.
9, liquid crystal indicator as claimed in claim 7, wherein, described loop error monitoring arrangement (620) comprising:
Counter (621,622,623);
Output area control device (624,625,626), it responds the above-mentioned pattern shows signal that above-mentioned microcomputer (100) provides, and controls above-mentioned counter output area;
Resetting means (627), it responds reset signal Reset and the above-mentioned pattern shows signal that above-mentioned microcomputer (100) provides respectively, with above-mentioned counter reset; And
Device (628), it receives the output signal of above-mentioned counter, produces another described sign control signal RFC2 that reads, and the above-mentioned sign generating means (520) of reading is enabled.
10, liquid crystal indicator as claimed in claim 7, wherein, the output unit of described control signal (630) comprises or door (631), input ends described or door (631) receive the above-mentioned sign control signal RFC1 that reads respectively, RFC2 and its output terminal is connected with the above-mentioned Enable Pin that indicates generating means of reading.
11, as claim 1 or 7 described liquid crystal indicators, wherein, described storage management device (700) comprising:
Write/read-out control device (710), its response is selected signal by above-mentioned the 1st storage that above-mentioned storage device for selection controlling (600) provides, and the writing and read operation of row memory of piece respectively stored in control;
Address producing device (720), it imports above-mentioned horizontal-drive signal Hin, above-mentioned horizontal output signal Hout, above-mentioned dot matrix clock signal W-Dclk and the above-mentioned dot matrix clock signal R-Dclk that reads of writing, generation be used for the read operation of memory and memory write operation write and read address W-Add, R-Add;
Address selection device (730) utilizes above-mentioned writing/read-out control device to control, and writes and read address W-Add with above-mentioned, and R-Add supplies with above-mentioned above line memory LM0, LM1, the LM2 that respectively stores piece selectively respectively; And
Dot matrix clock selecting device (740) utilizes above-mentioned writing/read-out control device to control, and writes and read dot matrix clock signal W-Dclk with above-mentioned, and R-Dclk supplies with above-mentioned above line memory LM0, LM1, the LM2 that respectively stores piece selectively respectively.
12, as claim 1 or 7 described liquid crystal indicators, wherein, above-mentioned output selection device (420) comprises traffic pilot.
13, liquid crystal indicator as claimed in claim 1, wherein, described LCD panel is supported XGA (expanded images array) pattern, and the signal of above-mentioned LCD control device input VGA (video graphics array) pattern is supplied with above-mentioned LCD drive unit with the signal of above-mentioned XGA pattern.
14, liquid crystal indicator as claimed in claim 1, wherein, above-mentioned LCD panel is supported the XGA pattern, the signal of above-mentioned LCD control device input SVGA (hypervideo pattern matrix) pattern is supplied with above-mentioned LCD drive unit to the signal of above-mentioned XGA pattern.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR19960011554 | 1996-04-17 | ||
| KR11554/1996 | 1996-04-17 | ||
| KR11554/96 | 1996-04-17 |
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| Publication Number | Publication Date |
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| CN1166668A CN1166668A (en) | 1997-12-03 |
| CN1111834C true CN1111834C (en) | 2003-06-18 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN96111781A Expired - Lifetime CN1111834C (en) | 1996-04-17 | 1996-08-28 | Liquid crystal indicator with display mode mapping function |
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| Country | Link |
|---|---|
| JP (2) | JP4093380B2 (en) |
| CN (1) | CN1111834C (en) |
Families Citing this family (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100483532B1 (en) * | 1997-12-24 | 2005-08-17 | 삼성전자주식회사 | PLEL system implements multi-sync |
| JP2001166733A (en) * | 1999-11-30 | 2001-06-22 | Koninkl Philips Electronics Nv | Video signal interpolating method and display device having video signal interpolating function |
| TWI282957B (en) * | 2000-05-09 | 2007-06-21 | Sharp Kk | Drive circuit, and image display device incorporating the same |
| KR101012788B1 (en) * | 2003-10-16 | 2011-02-08 | 삼성전자주식회사 | Liquid crystal display and driving method thereof |
| KR20050037784A (en) * | 2003-10-20 | 2005-04-25 | 삼성전자주식회사 | Display apparatus and control method thereof |
| CN100389448C (en) * | 2004-05-21 | 2008-05-21 | 联咏科技股份有限公司 | Serial protocol type panel display system and display method |
| JP4559172B2 (en) * | 2004-09-17 | 2010-10-06 | 富士通セミコンダクター株式会社 | Image processing circuit and image processing method |
| WO2008047568A1 (en) * | 2006-09-27 | 2008-04-24 | Nec Corporation | Display method, display system, mobile communication terminal, and display controller |
| CN102033705B (en) * | 2010-12-10 | 2012-08-08 | 福州瑞芯微电子有限公司 | Special effect display and control system of roller |
| JP2013207769A (en) * | 2012-03-29 | 2013-10-07 | Toshiba Corp | Video processing apparatus and video processing method |
| DE112016001701T5 (en) * | 2015-04-13 | 2018-01-04 | Semiconductor Energy Laboratory Co., Ltd. | Decoder, receiver and electronic device |
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| US4851826A (en) * | 1987-05-29 | 1989-07-25 | Commodore Business Machines, Inc. | Computer video demultiplexer |
| US5038218A (en) * | 1990-10-10 | 1991-08-06 | Fuji Xerox Co., Ltd. | Image processing assembly with conversion and rotation of input image data or predetermined data to match data resolution and orientation |
| US5406308A (en) * | 1993-02-01 | 1995-04-11 | Nec Corporation | Apparatus for driving liquid crystal display panel for different size images |
| JPH07261732A (en) * | 1994-03-17 | 1995-10-13 | Oki Electric Ind Co Ltd | Display device |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2008165243A (en) | 2008-07-17 |
| CN1166668A (en) | 1997-12-03 |
| JPH09292863A (en) | 1997-11-11 |
| JP4093380B2 (en) | 2008-06-04 |
| JP4827105B2 (en) | 2011-11-30 |
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