CN1111907C - 在半导体器件上形成互连的方法和半导体器件上的互连件 - Google Patents

在半导体器件上形成互连的方法和半导体器件上的互连件 Download PDF

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CN1111907C
CN1111907C CN95190256A CN95190256A CN1111907C CN 1111907 C CN1111907 C CN 1111907C CN 95190256 A CN95190256 A CN 95190256A CN 95190256 A CN95190256 A CN 95190256A CN 1111907 C CN1111907 C CN 1111907C
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layer
tiw
mentioned
contact hole
ptsi
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CN1125999A (zh
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S·-H·洪
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Infineon Technologies AG
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Telefonaktiebolaget LM Ericsson AB
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Abstract

描述了用于微电路互连的两类金属化方案PtSi/TiW/TiW(N)/Au(第一类)和PtSi/TiW/TiW(N)/TiW/Au(第二类)及相关工艺。该金属化方案及工艺可应用到与小至1.5μm或更小金属间距互连的集成电路中，对于持续高温和大电流工作条件，该金属化方案是可靠的。

Description

在半导体器件上形成互连的方法 和半导体器件上的互连件
                发明背景
1)发明的领域
通常，本发明与电子器件的微电路互连中的金属化方案相关联，特别与半导体及相关的金属化工艺中的PtSi/TiW/TiW(N)/Au(第一类)和PtSi/TiW/TiW(N)/TiW/Au(第二类)Au的互连相关联。
2)相关工艺讨论
通常，高性能、高度集成的半导体器件要求缩小整个尺寸，包括金属引线和接触孔直径(包括路径尺寸)。这种尺寸缩小导致芯片工作温度升高和金属条及接触孔处的硅与金属导体间的界面上的电流密度增大。
同时，接触孔尺寸缩小必然增加其纵横比(即，台阶高度/直径度)，从而损害金属台阶覆盖层。在接触孔处，较小的台阶覆盖层将导致接触孔处电流密度的进一步增加。
特别地，大功率晶体管产生大电流并释放热量。器件在大电流密度和高温下工作将导致由于电子迁移引发的铝合金(一般含有铜和硅)基互连的退化。由电子动量转移引发的电迁移导致空洞的形成及金属导体断路。
金是一种良导体，其原子重量较铝重7倍。金基互连对电迁移现象具有强的抵抗作用。然而，由于金-硅的低共熔点(～370℃)，需要具有某些基本特征的扩散阻挡层，这些基本特征如：
长期高温稳定性，
在大电流密度下，良好的抗电迁移能力，对绝缘层和金导体具有良好的附着能力，
良好的导体，
具有与掺杂Si(n+和p+)的低的接触电阻，接触孔处形成良好的台阶覆盖层，无颗粒化，和
一个宽的工艺宽容度，甚至在很小尺寸(～1μm)的情况下。
金基互连通常用两种方法形成，一是利用基于扩散阻挡层和金的蒸发的剥离技术，例如，Ti/Pt/Au金属的剥离；二是利用与等离子刻蚀金相结合的溅射技术或电镀金导体。
剥离技术的一个主要优势是它可相当容易地形成小于2μm的金属间距。成功的剥离技术要求具有金属源与片子之间距离很长的电子束蒸发设备，例如，对直径为6英寸的片子，为得到蒸发金属的入射角偏离片子表面法线方向小于3°，金属源与片子间距离必须大于145cm。因此蒸发设备的尺寸是巨大的，贵金属的浪费也是非常大的。此外，对光致抗蚀剂截面的要求是相当高的：如图1c所示的厚的(大于2.5μm)及有负倾斜侧墙(大于90°)的凹形截面。本技术产生非常低的台阶覆盖层，并且，始终如一地被证明，就扩散阻挡层的可靠性而论对粒子是非常敏感的。
与等离子体刻蚀相结合的溅射和电镀技术，利用普通设备就能容易地实现，与剥离技术相反，对大直径片子(大于6英寸)没有困难。然则，该技术的一个缺点是由于某些严重的工艺障碍难以得到一个小于4μm的金属间距，这些工艺障碍例如：
电镀槽中光致抗蚀剂的损失；
电镀速度的几何尺寸依赖关系和电镀同时具有大面积几何尺寸与细线条时的困难；
在溅射金膜的湿法刻蚀后过于粗糙的金导体表面被用于电镀及扩散阻挡层的保护；和
扩散阻挡层处的刻蚀钻蚀。
由于电镀的金层必须代替光致抗蚀剂充当刻蚀掩膜，因此即使利用等离子体刻蚀，也难以消除某些钻蚀。
金较扩散阻挡层软很多，因此在等离子体刻蚀工艺中难以应用强的物理溅射效应。同时，金刻蚀掩膜不能提供任何侧面钝化，而光致抗蚀剂刻蚀掩膜却能提供有机聚合物侧面钝化。因此，抑制微电路互连方面的刻蚀钻蚀是非常重要的。
在此所称的TiW和TiW(N)，过去曾称之为钛-钨或/和氮化钛-钨，(这并不代表化学配比的组分，而是代表TixW1-x“赝合金”，TixW1-x是由阴极组分X＝0.3得到的(相当于Ti的重量百分比为10％))。溅射TiW和TiW(N)膜的实际组分由溅射参数决定，并相应地改变了作为扩散阻挡层和附着层等的特性。
以前，TiW和TiW(N)扩散阻挡层已用在作为集成电路互联材料的Si/TiW/Al或PtSi/TiW/Al金属化系统中或用于封装的Al(键和块)/TiW(N)-TiW/Au(连线或焊点)金属化系统中。
J.A.Cunningham等的文章，“Corrosion Resistance ofSeveral Integrated-Circuit Metallization System”IEEETransactions on Reliability，Vol.R-19，No.4，November1970，PP.182-187，讨论了Al(键合块)/TiW/Au(连线)金属化系统，而R.S.Nowicki等的文章，“Studies of theTiW/Au metallization on Aluminum” Thin Solid Films，53(1978)，PP.195-205，讨论了Al(键合块)/TiW(N)/Au金属化系统。Nowicki等的文章包括当TiW膜相对较纯时，在300℃下让TiW和Au充分混合6分钟的观察结果。他们也观察到反应溅射TiW(O，N)膜大大改善了扩散阻挡层的性能。TiW(O，N)膜中，氮、氧原子百分比组分分别为42％和8％，氧原子是从溅射腔内残余气体中非有意引入的。TiW(O，N)膜甚至只有极小的本征应力，而含4％原子百分比氧的TiW(O)膜则具有张应力。
R.K.Sharma等的两项专利中透露了在用于TAB(带自动键合)或线键合应用的Al(键合块)/TiW(N)(1.5-3.0k)/TiW(0.5-1.0k)/Au(2-7k)金属化系统中TiW(N)/TiW双层扩散阻挡层的使用。见美国专利4,880,708号和4,927,505号，其授权日分别为1989年11月14日和1990年5月22日。优化的厚度范围在括号中给出。TiW(N)膜通过使用氩气中含不少于30％体积百分比的氮气的混合气体溅射而获得。没有有关溅射技术的信息。
将Ti含于W中的主要原因是由于在界面处可形成强的Ti-O键，因此可改善与SiO2的附着性能。Ti在W中的最大溶解度是600℃时的约10％原子百分比。任何多余的Ti均将以赝合金TiW形式微观分散着，甚至分布在晶界和界面处。实际的扩散阻挡层性能改善是通过在TiW阴极(靶)溅射过程中Ti原子的氧化或/和氮化获得的。特别是在晶界处形成稳定的TiO2和TiN似乎有效地减慢了重要的晶界扩散。然而，Ti原子的氧化和氮化的一个主要不足是失去或降低了在SiO2和TiW间界面处形成Ti-O键的能力。
对于封装应用，鉴于Al与W彼此可形成金属合金，因此具有良好的附着能力，Cunningham等和Nowicki等已成功地在Al键合块上直接使用TiW(N)。进而为消除Al2O3，人们可容易地在Al表面使用强溅射刻蚀，也可在钝化膜上使用强溅射刻蚀。强溅射刻蚀能粗化表面，从而增加附着能力。由于通常扩散阻挡层过覆盖钝化层接近为10μm，因此在任何情况下，由于在TiW(N)和钝化层SiO2(磷硅玻璃，硼磷硅玻璃)或Si3N4间附着能力差，引起刻蚀中数微米的横向尺寸损失均不会影响可靠性。
然而，当微电路互连中金属间距小到1.5μm时，情况就完全不同了。在具有接触孔(下于1μm)的SiO2层和扩散阻挡层间的附着强度对刻蚀钻蚀面积和可靠性有决定性影响。在这种情况下，扩散阻挡层的覆盖层，超过接触孔(图1e)可以是十分之几微米，而此处十分之一微米也是非常重要的。由于对高频功率晶体管和高速器件的结深一般非常浅，因此溅射刻蚀的应用将受到很大的限制。
Dening等在“Reliability of High Temperature I2LIntegrated Circuits，”IEEE/International ReliabilityPhysics Symposium Proc.，1984，PP.30-36中讨论了应用于集成电路互连的金属化方案PtSi/TiW(250)/TiW(N)(2k)/TiW(250A)/Au(5k)/TiW(500)。文章涉及到应用于3英寸片子的剥离技术，但文章中没有剥离技术的细节。然则，在集成电路生产中，存在一系列实现问题，例如由于在热应力作用下图形要发生形变，而与金属钨(熔点＝5660℃)的蒸发与冷凝相关将形成大量的热，因此难以在剥离技术中使用光致抗蚀剂或某些聚合物图形。进而，甚至对3英寸片子，应力水平就高到足以使Au导体形成小丘和空洞。高的应力水平也将限制片子尺寸的增加。鉴于与氮气分子碰撞产生台阶覆盖，将氮气引入金属钨和钛的蒸发过程对金属剥离将引起困难。总之，由于在反应蒸发中，坩埚中的熔融金属钛和钨将与氮气反应，因而获得高质量的膜几乎是不可能的。
按照本发明人的经验及Dening等文章中的报道，SiO2与TiW(N)间的附着强度并没强到足以抵抗由热失配引起的应力，热失配主要来源于TiW(N)的淀积温度在100-350℃范围内，而TEC(热膨胀系数)差为4-8ppm/℃。这一弱的附着性能导致不能接受的大刻蚀钻蚀，并经常在接触孔侧壁留下小的孔洞。由于在420℃退火30分钟后观察到金扩散进入体硅和硅扩散进入金层，这种孔洞的形成将引起严重的可靠性问题。其机制似乎是表面扩散。
K.A.Lorenzen等，在专利号为5,173,449，授权日为1992年12月22日，题目为“Metallization Process”的美国专利中，包括了应用于微器件互连的TiW(0.2-0.8k)/TiW(N)(2-5k)/TiW0.2-0.8k)/Au(5-20k)/TiW(1-4k(作为金图形的刻蚀掩膜，之后被刻掉)方案的金属化工艺。主要工艺步骤是基于溅射和等离子体刻蚀技术。然而对于形成细线条金导体(1-1.25μm宽或更窄)，由于厚的金层的等离子体刻蚀是基于氩和氧气的纯物理溅射，该工艺的宽窄度(现实性)似乎是低的。结果，为了清除残余金属金、钛和钨，推荐了在金刻蚀后用HNO3煮的方法。然而，除非TiW表面已被氧化，否则HNO3煮将容易损害TiW层。
同时，TiW表面的氧化将导致刻蚀掩膜处刻蚀残留的金属钛和钨的氧化。结果，此清除工艺是无效并有害的。氧化步骤可能导致在金和TiW层间的附着失败，尤其在细线条金导体情况下。
Lorenzen等在专利号为5,173,449的美国专利中详细描述了溅射系统(MRC-603，Material Research Corp.N.Y.)的参数设定，尤其对反应溅射TiW(N)膜后N2的清除过程。然而，没有应用溅射技术的描述，而这对反应溅射TiW(N)膜是决对重要的。他们使用氮气浓度在14-38％体积百分比范围内的N2/Ar混合气体。由Lorenzen等的专利提出的金属化方案由于底层的TiW直接与硅衬底相接触，因而对接触电阻和高温稳定性没有优化。
                   发明概略
本发明通过接触形成一薄层PtSi提供良好的欧姆接触和稳定性。我们知道PtSi和PtSi2可降低接触电阻，然而人们不知道PtSi可充当TiW基扩散阻挡层的稳定剂。类似于应力缓冲层，稳定机制可能是热力学的或是动力学的，准确的机制还没有建立。我们还知道TiW膜对应力相当敏感，其本征应力为张应力。TiW膜与体硅(p+和n+掺杂)直接接触，在高温(420)下是不稳定的。
本发明通过使用由射频反应溅射技术得到的氮化TiW、TiW(N)提供了一种非常稳定的扩散阻挡层。通过SIMS(二次离子质谱计)和SEM(扫描电子显微镜)对由不同技术溅射得到的扩散阻挡层进行了对比研究。由直流磁控管和射频磁控管溅射得到的TiW(N)的稳定性较射频溅射膜差很多(图2和图5)。
射频反应溅射的优势是同时改善了附着强度和台阶覆盖并降低了颗粒的生成。目前，由于高的溅射速度，直流磁控管溅射技术被广泛应用在IC金属化中。
本发明在SiO2与TiW层间和扩散阻挡层与金层间提供了良好的附着能力。依赖于溅射腔中残余气体H2O和O2的组分，本发明提供了两类界面。对超过10-7乇的高真空，TiW(N)-Au(第一类)界面具有极其高的稳定性。然而对于中或相对较低真空条件，TiW-Au(第二类)界面具有优势。后者稍微改善了附着能力，但由于在金属钛和金之间形成金属合金，因此寿命相对较短。
附着强度依赖于TiW(N，O)膜中的氧和氮组分。金膜脱落主要是由于界面处存在薄的TiO2膜，它有效地阻止了金通过氧化层渗透到扩散阻挡层中。Dening等的文章观察到TiW(N，O)和金间的附着强度弱于TiW和金间的界面。在他们的文章中对原因没有解释。然而，这个较弱的附着力可能主要依赖于界面处相对较高的氧组分(～6％，借助于AES，即俄歇电子能谱分析)和由于剥离技术引起的TiW(N，O)膜中不可控的氮组分(可能太高)。
在SiO2与底部的TiW膜结合层间的附着强度对刻蚀钻蚀和器件稳定性有重要影响。由于合金过程中温度不匹配，弱的附着力容易在接触孔处产生小空洞。结果，金原子进入硅衬底和硅原子进入金导体的表面扩散被大大推进。
本发明也提供了用于微电路器件互连的抗腐蚀的金属化方案。
从而，本发明与半导体器件、特别是硅基器件的金互连相关联。本发明与工作在大电流、高温条件并具有良好的可靠性和长寿命的器件相关联。本发明直接与两类金与硅间的多层结构的扩散阻挡层相关联，扩散阻挡层主要是由于Au-Si共熔点～370℃要求的。
本发明与多层结构的扩散阻挡层相关联，该扩散阻挡层具有与硅衬底的低的接触电阻、与绝缘层SiO2(包括掺杂磷硅玻璃和硼磷硅玻璃)和Si3N4及金导体的良好的附着能力。
本发明也与等离子体刻蚀中产生较小的钻蚀的多层结构的扩散阻挡层相关联。
本发明进一步与反应溅射技术相关连，该技术适合于获得扩散阻挡层的大多数基本特性。例如，长期的高温稳定性，良好的附着性能，较少的颗粒，接触孔处较好的台阶覆盖及宽的工艺宽窄度甚至于1.5μm或更小的金属间距。
此外，本发明还与容易实现和成本经济的适合于精细几何尺寸的金导体大量生产时的金属化工艺相关联。
          `     附图的简单描述
下面将参考下述附图来描述本发明。
图1a～1g描述了微器件互连的制造过程。
图2表示了射频反应溅射的第一类金属化方案在420℃退火280小时(氮气氛)后的SIMS分析结果，多层结构为：PtSi(200)/TiW(250)/TiW(N)(1.8k)/Au(1k)。
图3表示了直流磁控管反应溅射扩散阻挡层在420℃退火30分钟(氮气氛)后的SIMS分析结果，多层结构为：PtSi(200)/TiW(N)(3k)/TiW(1k)/Au(10k)。
图4表示了射频磁控管反应溅射第二类金属化方案在420℃退火30分钟(氮气氛)后的SIMS分析结果，多层结构为：PtSi(200)/TiW(250)/TiW(N)(1.8k)/TiW(120A)/Au(12k)。
图5表示了射频反应溅射第二类金属化方案在420℃退火90小时(氮气氛)后的SIMS分析结果，多层结构为：PtSi(200)/TiW(250)/TiW(N)(1k)/TiW(250)/Au(1k)。
               发明的详细描述
描述了用于微电路互连的两种金属化方案：PtSi/TiW/TiW(N)/Au(第一类)和PtSi/TiW/TiW(N)/TiW/Au(第二类)及其相关工艺。该金属化方案可用于小到1.5μm或更小金属间距的集成电路互连，该金属化方案对于持续高温和大电流工作条件是可靠的。
按照本发明，用于微电路互连作为扩散阻挡层的TiW/Au，TiW(N)/Au和TiW(N)/TiW/Au等金属化方案在附着能力和高温长期可靠性方面的不足得到了改善。本发明提供了降低整个金属化系统到线宽为1μm范围的可能性，在实现上本发明没有或很少有问题，同时本发明是成本最经济的金属化工艺之一。
本发明包含两类金属化方案及相关工艺第一类：PtSi(0.1-0.4k)/TiW(0.2-0.5k)/TiW(N)(1.0-2.0k)/Au(0.3-1.0k)/Au(7-15k，电镀)第二类：PtSi(0.1-0.4k)/TiW(0.2-0.5k)/TiW(N)(1.0-2.0k)/TW(0.1-0.5k)/Au(0.3-1.0k)/Au(7-15k，电镀)
第一类在溅射腔高真空(＜10-7乇)条件下被认为较好，而第二类对中或较低真空(＞10-7乇)系统较好。在两种情况下，对于TiW(N)膜的反应溅射，氩气中的氮气含量为5～10％体积百分比。为了良好的欧姆接触和多层结构扩散阻挡层的稳定性及附着能力，在接触孔处形成一薄层(100-400)的PtSi。本发明包含由溅射(最好以与其它金属相同的溅射设备)或蒸发方法在无氧的硅衬底表面淀积一层纯金属铂(约为PtSi厚度的一半)。对于膜的厚度，一薄(＜20)的自然SiO2膜就足以使整个硅化物工艺变为不可靠。PtSi层的形成最好在600～620℃惰性气氛N2中退火30分钟来获得，剩余的金属铂最好用普通的HNO3+3HCl混合液来剥离掉。
在第一个结合层TiW膜溅射前，为了分别消除自然氧化层SiO2和PtSi及SiO2膜表面上的H2O，最好用射频溅射技术进行轻微的溅射刻蚀。没有这种溅射刻蚀，消除通过氢键键合在SiO2表面的水和单层OH根是非常困难的。在SiO2表面附着失败的一个主要原因是通过氢键键合形成的表面水和溅射腔中过高的残余气体H2O和O2的浓度。
为了清洁靶表面和排除溅射腔中残余的气体H2O和O2，最好对TiW靶进行几分钟(2-5)的预溅射。
溅射一薄层TiW膜(200-500)作为结合层。TiW膜的纯度和厚度是重要的。膜中高组分的氧和氮均将引起对SiO2膜弱的附着能力。由于有与PtSi层中的硅原子反应形成硅化物的趋势，太厚的TiW膜是不利的(图3-5)。没有PtSi层，TiW膜的稳定性是相当差的。已经观察到钛和钨原子相当快地扩散进入硅衬底。
利用氮气和氩混合气体由射频溅射技术可得到反应溅射TiW膜(1.0-2.0k)。混合比(氩气中的氮气浓度＝5-10％体积百分比)依赖于射频功率密度(W/cm2)、压强(10-15mToor)、氮气流速、和片子温度，它们决定氮与钛和钨原子化学反应速度。
为了得到相对无氧的TiW(N)膜，要求一个高的射频功率密度(＞1.5W/cm2)。而对于得到与第一类结构中的金膜的好的附着能力，相对无氧的TiW(N)膜是需要的。这个射频反应溅射TiW(N)膜起到真正的扩散阻挡层的作用。为了综合扩散阻挡层的特性、附着能力、薄层电阻和应力，控制膜中氮和氧(由残余气体非有意引入的)组分是非常重要的。TiW(N)膜中氮和氧的组分越高，扩散阻挡作用越好，但这种膜具有与金膜太差的附着能力和太高的电阻率。TiW(N)膜的电阻率的典型值较纯TiW膜高三倍。正如本文在其它地方提到的一样，由于在TiW(N)膜表面氧化形成TiO2，附着能力损失的影响是显著的。
适当溅射技术的选择对TiW(N)膜的质量有重要的影响。本发明揭示了由射频溅射和与磁控管(直流磁控管和射频磁控管)相关的溅射技术得到的TiW(N)膜的某些基本区别，SIMS分析已经证明了420℃退火280小时(氮气氛)的由射频溅射得到的TiW(N)膜的优越性(图2)，SIMS分析也指出了在金和TiW(N)层间良好的附着性能。420℃退火30分钟的由直流磁控管和射频磁控管溅射获得的扩散阻挡层的SIMS分析结果分别表示在图3和图4。
直流磁控管和射频磁控管溅射技术均产生相当不稳定的扩散阻挡层。由于磁控管在其正下方产生非常强的等离子体，与这些磁控管相关的反应溅射技术将导致氮与片子和TiW靶(阴极)间发生不均匀的化学反应。这一严重的结果是在片子上产生不均匀的TiW(N)膜的氮化。靶的强的和不均匀的氮化将引起颗粒。显然，迄今为止无人清楚地指出过与磁控管相关的反应溅射TiW(N)膜的这些负效应。然而，众知的较少台阶覆盖的负效应是由于在磁控管下面的靶上形成空洞所致，可由使用最近的转动或扫描磁控管技术来改善。但是，既使用先进的技术，不均匀氮化也不能完全避免。
本发明揭示了在需要结合层的情况下，在第二类金属化方案中金层下适当厚度的纯TiW层的重要性。相对较纯TiW膜作为硅和金间的扩散阻挡层的不稳定性已经有报道(在Nowicki等人的文章中)。新的离解机制可由Au-Ti合金的作用来解释。TiW结合层在高温(400℃)下失去稳定性并且在金属钛向上扩散进入金层后开始形成Au-Ti合金(图3和图5)。Au-Ti合金的量决定着高温下扩散阻挡层上的张应力的大小。扩散阻挡层上的张应力促进了金扩散进入体硅和硅扩散进入金层。
这是第二类阻挡层的主要离解机制之一，从而选择薄的TiW层(即100-500)是重要的。在TiW(N)膜淀积后，操作上注意从溅射腔中和TiW靶表面上消除氮源是重要的，即仔细清洁溅射腔，并且由于在溅射TiW(N)膜过程中靶表面被氮化，因此在溅射第二类方案中的TiW结合层前应预溅射TiW靶几分钟(2-5)。
在淀积用于第一类方案中的TiW(N)膜或用于第二类方案中最后结合层的TiW膜后，为了得到纯金膜并增强与下层的附着能力，以高的溅射速度在原位(不破真空)溅射一薄的(0.3-1.0k)金层。在这薄的金层溅射前，最好对金靶进行一短的(0.5-1分钟)预溅射。薄的金层主要作为防止TiW和TiW(N)膜氧化和受化学攻击时的保护层，同时也充当均匀电镀金导体(7-15)的导电和初始层。
类似于前面讨论的扩散阻挡层的离解机制，没有任何形成Au-Ti合金倾向的第一类金属化方案(图1b和2)较第二类方案(图1c)更稳定。图5表示了在420℃退火90小时(氮气氛)后，第二类扩散阻挡层的SIMS分析结果，可清楚地观察到金属钛的向上扩散和金属钛、钨和铂向下扩散进入体硅中。
在与钛、钨原子争夺硅原子的竟争后，PtSi层被溶解。钛、钨和铂原子进入体硅的运动机制类似于硅化物的形成。然而，甚至第二类阻挡层也容易满足高温和大电流工作的要求。高频功率晶体管能经受420℃下工作40小时的热负载而无任何输出损失。这个结果相应于在130℃作温度下寿命超过200年和Ea＝0.9eV(Ea＝Arrhenius方程A*exp(-Ea/kT)中的激活能，而A和k(Boltzmann)是常数，T＝绝对温度)。
参照图1a-1g，描述了体现本发明的方法，图1a表示通常用绝缘层SiO2或Si3N4/SiO2或SiO2/Si3N4/SiO2膜2覆盖的硅衬底1。为了形成接触孔，用等离子体或湿法或湿/干(等离子体)结合刻蚀法在绝缘膜2上开孔以形成接触孔。稍微倾斜的接触孔对较好的扩散阻挡层的台阶覆盖来说更有优势(见下面)。一些掺杂剂(n-或p-型)可通过接触孔用注入或淀积并在高温(～1000℃)下推进的方法进入硅衬底1。在使接触孔处形成的薄SiO2膜去氧化后，薄的Pt膜(100-200)可通过溅射或蒸发生成。去氧化是将硅衬底1浸入稀释的HF水溶液(1-2％)中实现的。
在惰性气体氮气中，通过600-620℃退火30分钟形成PtSi层3，最后多余的金属铂用王水(HNO3+3HCl)剥离掉。
图1b和图1c分别表示了本发明的第一类和第二类金属化方案。在仔细的抽空和轻微的溅射刻蚀后，用射频溅射方法溅射形成薄的TiW膜(200-500)4，这个TiW膜4充当绝缘膜2的结合层。
附着强度取决于TiW膜4的纯度，TiW膜4的纯度又由溅射腔中残余的气体H2O和O2的含量、溅射速度和氢与SiO2层2表面键合形成的水来确定。为了减少TiW膜4中的氧组分，要求高于10-7乇的真空度和高的溅射速度。然而由于单层H2O与SiO2表面2发生化学键合(氢键)，没有轻微溅射刻蚀将难以得到最佳附着性能。
由于使表面2和3自然粗糙，轻微溅射刻蚀本身也增强了附着能力。为了不过多地损害PtSi层3，采取保护也是非常重要的。大多数情况下，约50的厚度损失似乎是可接受的。除了以上提到的措施外，为了吸除溅射腔中的残余气体H2O和O2及清洁靶，最好对TiW靶(阴极)进行2-5分钟的预溅射。由于由温度失配引起的应力能在接触孔和TiW层4间形成空洞，为了减小刻蚀和阻止金9通过表面扩散进入硅衬底1，在绝缘层2和TiW结合层4间的强附着能力具有重要意义。
随后，真正的扩散阻挡层TiW(N)膜(1.0-2.0k)由射频反应溅射技术形成，射频功率密度最好大于1.5W/cm2和氩气流中氮气浓度最好在5-10％体积百分比范围内。10mTorr的气压是综合考虑台阶覆盖层、应力和溅射速度的结果。台阶覆盖层依赖于接触孔的纵横比、接触孔的侧角、溅射参数(尤其是压力)和溅射技术。
TiW(N)膜明显比TiW膜产生较小的台阶覆盖和较多的颗粒，然而与磁控管(直流和射频)相关的反应溅射技术相比，用射频反应溅射技术这些副效应要小的多。总之，射频反应溅射膜的稳定性大大优于由与磁控管相关的反应溅射得到的膜。
在清除氮气和对金靶短的预溅射(0.5-1分钟)后，接着溅射形成一薄的金膜7(300-1000)(图1b)，在TiW(N)膜形成后不破真空立即进行金溅射是重要的。否则，由于在TiW(N)膜表面形成TiO2将引起附着能力的损失或金膜脱落。即使膜的厚度很薄，为了得到较好的附着能力，最好使用高的射频功率密度。
参照第二类金属化方案(图1c)，鉴于在溅射TiW(N)膜过程中靶表面发生氮化，在清除溅射腔中氮气和对TiW进行2-5分钟的预溅射后，溅射生成一薄的TiW结合层6(100-500)。同第一类方案相同，金膜7由溅射形成。
图1d表示了在金膜7上一个(凹形)光致抗蚀剂图形8，这个用于金电镀的光致抗蚀剂图形可由通常的光刻工艺获得。为了得到在电镀金膜9上的最后钝化膜10的较好的台阶覆盖层，光致抗蚀剂图形最好产生一凹角(角度＞90°)或垂直的截面8。对于非常小尺寸的金属间距(1.5-4μm)，负光刻胶(AZ5218E或AZ5214E，Hoechst)与i线(波长＝365nm)或g线(436nm)片子步进曝光相结合可容易地在足够厚(＞1.5μm)的刻蚀剂上产生0.5μm的凹形光刻图形。
一种甚至可产生垂直光刻图形的标准的正光刻胶在大多数情况下也可很好工作。在光刻图形加固烘烤(～115℃/30分钟，充分的空气或氮气流)后，氧气等离子体清除(descum)可用来清洁金表面7。由于脏的金表面不能进行电镀，这一等离子体清除是重要的。
图1e表示在具有光刻图形8后电镀形成金膜9。金电镀槽并不是基于可引起光刻胶损失等的AuCN络合物，而是基于NaAuSO3络合物。后一个具有适当PH值(7.2-9.5)的电镀槽对光刻图形无大的损害。槽中还有一整平器，其平面化效应被表示在金截面9中。0.7-1.5μm的金厚度对大多数集成电路是足够了。然而金的厚度可容易地增加到适合于TAB(带自动键合)应用的具有较厚光刻胶的金突起范围(25μm)。
在金导体9电镀后，光刻胶8用丙酮除掉，随后顺序在丙醇和DI水(去离子水)中漂洗片子。在薄金膜7的湿法刻蚀前，为了得到干净的金表面，在去除光刻胶后，应再次进行氧气等离子体清除。
图1f表示了电镀的金导体9、湿法刻蚀的金薄膜7、等离子体刻蚀的TiW结合层6(仅对第二类)、TiW(N)扩散阻挡层5和底部TiW结合层4的截面。通过使用等离子体型(射频阳极耦合)或RIE(反应离子刻蚀、射频阴极耦合)型干法刻蚀机，利用SF6气体对第6、5和4层进行等离子体刻蚀。为了减小刻蚀钻蚀，最好使用RIE型干法刻蚀机。对第6、5和4层最好不用H2O2溶液进行湿法腐蚀。湿法腐蚀会引起钻蚀，而且对TiW(N)层5腐蚀太慢。
为了得到良好的欧姆接触和增强良好附着能力所必需的金属的某些互相混合，在刻蚀完第7，(6)，5，4层后，在氮气气氛中进行420℃ 30分钟退火。
图1g表示了最后的金导体9和钝化膜PESiNx(等离子体增强氮化硅，4-8k)10的截面。钝化膜10保护金导体9不受机械和化学(腐蚀)损害。由于在氮气中退火和暴露于空气中，在所有TiW和TiW(N)层6，5和4的暴露表面上均形成了TiN和TiO2保护膜，因此即使没有钝化膜，这种互连方案实际上也不会有腐蚀。选择PESiNx膜也是由于它较SiO2膜具有良好的热导性。对大功率晶体管，有效的热传递对稳定性是一个非常重要的特性。
在进行一个非标准的光刻步骤后，用NF3刻蚀气体或CF4+O2(～10％体积百分比)的混合气体由常规的等离子体刻蚀方法在PESiNx膜上开出键合块。然后，用丙酮或某些其它溶液除去光刻胶。
图2表示了420℃氮气氛退火280小时的射频反应溅射形成的扩散阻挡层的SIMS分析结果。第一类金属化方案的多层结构是：
PtSi(200)/TiW(220)/TiW(N)(1.8k)/Au(1k)。
在几次热应力试验后扩散阻挡层仍然是非常稳定的，并且由于已清楚观察到金向下扩散进入TiW(N)层，在金层与TiW(N)层间的附着能力是良好的。TiW与PtSi层间的欧姆接触也是好的。由于Si和Pt离子的最上部是明显重叠的，PtSi层也没受损害。对TiW(N)膜溅射氩气中的氮气组分为10％体积百分比。
图3表示了420℃氮气氛退火30分钟的直流磁控管反应溅射形成的扩散阻挡层的SIMS分析结果。金属化方案的多层结构是：
PtSi(200)/TiW(N)(3k)/TiW(1k)/Au(10k)。
扩散阻挡层相对是非常不稳定的，可非常清楚地看到钛和硅原子向上扩散进入金层，而钛、钨、金和铂原子向下扩散进入体硅。
PtSi层的离解也是非常清楚的。氩气中的氮气组分为30％体积百分比。扩散阻挡层的不稳定性是由于形成TiW(N)膜的反应溅射技术不适当和导致Au-Ti合金形成的结合层太厚(1k)。
图4表示了420℃氮气氛退火30分钟的射频磁控管反应溅射形成的扩散阻挡层的SIMS分析结果。金属化方案的多层结构是：
PtSi(200)/TiW(250)/TiW(N)(1.8k)/TiW(120)/Au(12k)。
扩散阻挡层相对是不稳定的，可非常清楚地看到硅原子向上扩散进入金层，而钛、钨、金和铂原子向下扩散进入体硅。然而这种情况下，图3中观察的钛原子向上扩散没有看到。PtSi层的离解是非常清楚的。氩气中的氮气组分为10％体积百分比。扩散阻挡层的稳定性较图3情形稍微得到改善，即使用第二种结构，不稳定性也是由于形成TiW(N)膜的反应溅射技术的不适当造成的。
图5表示了420℃氮气氛退火90小时后射频反应溅射形成的扩散阻挡层的SIMS分析结果。第二类金属化方案的多层结构是：
PtSi(200)/TiW(250)/TiW(N)(1k)/TiW(250)/Au(1k)。
扩散阻挡层在数次热应力试验后变得不稳定。可清楚地看到钛和钨原子向上扩散和钛，钨和铂原子向下扩散。然而这种情况下，图3中观察的钛原子向上扩散没有看到。PtSi层的离解已经开始，但不严重。用显微镜(SE M)可观察到Au-Ti合金的形成。然而，即使在TiW(N)的厚度仅为1k的情况下，在420℃下热冲击40小时，扩散阻挡层还是相当稳定的，高频功率晶体管没有任何输出损失。
正如以上证明的，膜结构、厚度和溅射技术的适当选择决定着长期稳定性，与SiO2、Si3N4和金层的良好附着能力和与p+(硼)和n+(磷、砷或锑)掺杂硅衬底的低的接触电阻。对于TiW和TiW(N)膜的连续淀积，应用射频反应溅射技术代替常用的直流磁控管在获得长期稳定性、良好的附着能力、接触孔处的良好台阶覆盖和较少的颗粒方面将起到重要作用。
射频反应溅射的TiW(N)膜作为扩散阻挡层的稳定性大大优于由与磁控管相关的反应溅射(直流磁控管和射频磁控管)得到的阻挡层。这个优越性已被SIMS(二次离子质谱)、SEM(扫描电子显微镜)分析和高频功率晶体管的寿命证明。
第一类和第二类金属化方案在长期稳定性和接触电阻方面优于某些已知的Si/TiW(N)/TiW/Au、Si/TiW/TiW(N)/TiW/Au或Si/TiW/TiW(N)/Au方案。而第一类方案在溅射腔中具有良好真空((10-7乇)时更有优势，第一类方案在长期高温稳定性、工艺简单程度和较少的刻蚀钻蚀的工艺宽容度方面优于第二类方案。
然而，第二类方案避免了由于真空系统不好引起的溅射腔中残余气体H2O和O2的组分相对较高时的金脱离问题。第二类方案中由于金的互扩散，增强了在TiW(N)和Au层间的薄TiW层的附着能力。但在厚的金层下，纯的TiW将引起Au-Ti合金的形成，进而开始引发第二类方案的破坏。
第一类和第二类方案至少分别经受得住420℃/280小时和420℃/40小时的热应力，而高频功率晶体管无任何输出损失。即使第二类方案的最短寿命也相当于器件在130℃的温度下工作超过200年。
通过应用较好建立的溅射金电镀和等离子体刻蚀技术，本金属化工艺就可很好地实现而且成本也是经济的。
可以理解，这里描述的具体技术仅仅是为了解释的目的，在没有离开本发明的精神和范围的情况下，有许多技术变化可以使用。从而，基于这里所述技术的一些变化被包含在下面的权利要求书的范围内。

Claims (48)

1.一种在半导体器件上形成互连的方法，所述的方法包括下列步骤：
在硅衬底上形成一个绝缘层；
在上述绝缘层上形成一个接触孔，  以暴露上述衬底的一部分；
用上述接触孔，在上述衬底上形成一个PtSi层；
用上述接触孔，在上述PtSi层上形成一个TiW层；
用上述接触孔，在上述TiW层上形成一个TiW(N)层；及
用上述接触孔，在上述TiW(N)层上形成一个Au层。
2.按权利要求1中所述的方法，其特征在于，所述PtSi层可降低接触电阻和稳定上述衬底和上述充当结合层的TiW层间的界面。
3.按权利要求1所述的方法，其特征在于，进一步包括下述步骤：
在上述PtSi层形成后和上述TiW层形成前，以轻微的溅射刻蚀增强上述绝缘层和上述TiW层间的附着能力，这个轻微的溅射刻蚀还可进一步清除所述PtSi层上的SiO2。
4.按权利要求1中所述的方法，其特征在于，进一步包括下述步骤：
在上述PtSi层形成后和上述TiW层形成前，通过预溅射以从TiW靶表面减少溅射腔中的残余气体H2O和O2。
5.按权利要求1中所述的方法，其特征在于，其中所说的TiW层是纯TiW膜。
6.按权利要求1中所述的方法，其特征在于，进一步包括下述步骤：
在TiW(N)层形成后和上述薄Au层溅射前，通过预溅射与净化相结合以便从TiW靶表面和溅射腔中清除氮。
7.按权利要求1中所述的方法，其特征在于，其中所说的形成上述Au层的步骤进一步包括下述步骤：
用上述接触孔，在上述TiW(N)层上由溅射形成一个Au薄层；和
用上述接触孔，在上述薄Au层上形成一个电镀Au层。
8.按权利要求7中所述的方法，其特征在于，进一步包括下述步骤：
用一种溶液腐蚀上述薄Au层。
9.按权利要求7中所述的方法，其特征在于，进一步包括下述步骤：
用上述电镀金层作为刻蚀掩膜，使用等离子体刻蚀方法，刻蚀作为扩散阻挡层的上述TiW(N)层和作为结合层的上述TiW层。
10.按权利要求9中所述的方法，其特征在于，其中所述的刻蚀步骤是在原位进行的。
11.按权利要求1中所述的方法，其特征在于，进一步包括下述步骤：
通过将金互扩散进入上述TiW(N)层以便退火上述金层来得到优化的接触和附着能力。
12.按权利要求1中所述的方法，其特征在于，其中所述互连是键合块。
13.按权利要求1中所述的方法，其特征在于，其中步包括下述步骤：
在上述金层上形成一PESiNx钝化膜。
14.按权利要求1中所述的方法，其特征在于，其中厚度范围是：
  PtSi(0.1-0.4kA)/TiW(0.2-0.5k)/TiW(N)(1.0-2.0kA)/Au(0.3-1.0k)/Au(7-15k，电镀)。
15.按权利要求1中所述的方法，其特征在于，为了避免内部应力，用于对上述TiW(N)层和上述TiW层的溅射的射频功率密度的是同一量级的。
16.按权利要求1中所述的方法，其特征在于，其中用于溅射上述TiW(N)层和上述TiW层的射频功率密度大于1.5W/cm2。
17.一种在半导体器件上形成互连的方法，所述的方法包括下列步骤：
在硅衬底上形成一个绝缘层；
在上述绝缘层上形成一个接触孔，以暴露上述衬底的一部分；
用上述接触孔，在上述衬底上形成一个PtSi层；
用上述接触孔，在上述PtSi层上形成第一TiW层；
用上述接触孔，在上述第一TiW层上形成一个TiW(N)层；
用上述接触孔，在上述TiW(N)层上形成第二TiW层；及
用上述接触孔，在上述第TiW层上形成一个Au层。
18.按权利要求17中所述的方法，其特征在于，其中所述的PtSi层降低了接触电阻和稳定了上述衬底与充当结合层的上述第一层TiW层间的界面。
19.按权利要求17中所述的方法，其特征在于，进一步包括下述步骤：
在上述PtSi层形成后和上述第一层TiW层形成前，通过轻微地溅射刻蚀以增强上述绝缘层和上述TiW层间的附着能力，这一轻微的溅射刻蚀进一步清除了上述PtSi层上的SiO2。
20.按权利要求17中所述的方法，其特征在于，进一步包括下述步骤：
在上述PtSi形成后和上述第一层TiW层形成前，通过预溅射以从TiW靶表面减少溅射腔中的残余气体H2O和O2。
21.按权利要求17中所述的方法，其特征在于，其中所述的TiW层是纯TiW膜。
22.按权利要求17中所述的方法，进一步包括下述步骤：
在TiW(N)层形成后和上述第二TiW层形成前，通过预溅射与净化相结合以便从TiW靶表面和溅射腔中清除氮。
23.按权利要求17中所述的方法，其特征在于，其中所说的形成上述Au层的步骤进一步包括下述步骤：
用上述接触孔，在上述第二层TiW层上由溅射形成一个Au薄层；和
用上述接触孔，在上述薄Au层上形成一个电镀Au层。
24.按权利要求23中所述的方法，其特征在于，进一步包括下述步骤：
用一种溶液腐蚀上述的薄Au层。
25.按权利要求23中所述的方法，其特征在于，进一步包括下述步骤：
用上述的电镀金层作为刻蚀掩膜，使用等离子体刻蚀方法，刻蚀作为扩散阻挡层的上述TiW(N)层和作为结合层的上述第一和第二TiW层。
26.按权利要求25中所述的方法，其特征在于，其中所述的刻蚀步骤是在原位进行的。
27.按权利要求17中所述的方法，其特征在于，进一步包括下述步骤：
通过将金互扩散进入上述第二层TiW层，从而退火上述金层，以得到优化的接触和附着能力。
28.按权利要求17中所述的方法，其特征在于，其中所述互连是键合块。
29.按权利要求17中所述的方法，其特征在于，进一步包括下述步骤：
在上述金层上形成一PESiNx钝化膜。
30.按权利要求17中所述的方法，其特征在于，其中厚度范围是：
            PtSi(0.1-0.4k)/TiW(0.2-0.5k，第一层)/TiW(N)(1.0-2.0k)/TiW(0.1-0.5k，第二层)/Au(0.3-1.0k)/Au(7-15k，电镀)。
31.按权利要求17中所述的方法，其特征在于，其中为避免内部应力，用于上述TiW(N)层和上述第一和第二层TiW层的溅射的射频功率密度是同一量级的。
32.按权利要求17中所述的方法，其特征在于，其中用于溅射上述TiW(N)层和上述TiW层的射频功率密度大于1.5W/cm2。
33.一种半导体器件上的互连件，该互连件包括：
在硅衬底上的绝缘层；
在上述绝缘层中用以暴露部分上述衬底的接触孔；
在上述接触孔中、在上述衬底上的PtSi层；
在上述接触孔中、在上述PtSi层上的TiW层；
在上述接触孔中、在上述TiW层上的TiW(N)层；和
在上述接触孔中、在上述TiW(N)层上的Au层。
34.按权利要求33中所述的互连件，其特征在于，其中所述的PtSi层降低了接触电阻和稳定了上述衬底与充当结合层的上述TiW层间的界面。
35.按权利要求33中所述的互连件，其特征在于，其中所述的TiW层是纯TiW膜。
36.按权利要求33中所述的互连件，其特征在于，其中所说Au层进一步包括：
在上述接触孔中、在上述TiW(N)层上的一个Au薄层；和
在上述薄Au层上的电镀Au层。
37.按权利要求33中所述的互连件，其特征在于，其是所述的互连件是键合块。
38.按权利要求33中所述的互连件，其特征在于，进一步包括：
在上述金层上的PESiNx钝化膜。
39.按权利要求33中所述的互连件，其特征在于，所述厚度范围是：
       PtSi(0.1-0.4k)/TiW(0.2-0.5k)/TiW(N)(1.0-2.0k)/Au(0.3-1.0k)。
40.一种半导体器件的互连件，该互连件包括：
在硅衬底上的绝缘层；
在上述绝缘层中用以暴露部分上述衬底的接触孔；
在上述接触孔中、在上述衬底上的PtSi层；
在上述接触孔中、在上述PtSi层上的第一层TiW层；
在上述接触孔中、在上述第一层TiW层上的TiW(N)层；
在上述接触孔中、在上述TiW(N)层上的第二层TiW层；和
在上述接触孔中、在上述第二层TiW层上的Au层。
41.按权利要求40中所述的互连件，其特征在于，所述的PtSi层降低了接触电阻和稳定了上述衬底与充当结合层的上述第一层TiW层间的界面。
42.按权利要求40中所述的互连件，其特征在于，所述的TiW层是纯TiW膜。
43.按权利要求40中所述的互连件，其特征在于，所说Au层进一步包括：
在上述接触孔中，在上述第二层TiW层上的一个Au薄层；和
在上述薄Au层上的电镀Au层。
44.按权利要求40中所述的互连件，其特征在于，所述的互连件是开孔的键合块。
45.按权利要求40中所述的互连，其特征在于，进一步包括：
在上述金层上的PESiNx钝化膜。
46.按权利要求40中所述的互连件，其特征在于，所述厚度范围是：
        PtSi(0.1-0.4k)/TiW(0.2-0.5k，第一层)/TiW(N)(1.0-2.0k)/TiW(0.1-0.5k，第二层)/Au(0.3-1.0k)/Au(7-15k，电镀)。
47.按权利要求33中所述的互连件，其特征在于，所述厚度范围是：
   PtSi(0.1-0.4k)/TiW(0.2-0.5k)/TiW(N)(1.0-2.0k)/Au(7-15k，电镀)。
48.按权利要求40中所述的互连件，其特征在于，厚度范围是：
               PtSi(0.1-0.4k)/TiW(0.2-0.5k，第一层)/TiW(N)(1.0-2.0k)/TiW(0.1-0.5k，第二层)/Au(7-15k，电镀)。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1315158C (zh) * 2003-11-18 2007-05-09 国际商业机器公司 选择性电镀半导体器件的输入/输出焊盘的方法

Families Citing this family (39)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
MY115336A (en) * 1994-02-18 2003-05-31 Ericsson Telefon Ab L M Electromigration resistant metallization structures and process for microcircuit interconnections with rf-reactively sputtered titanium tungsten and gold
JPH09125231A (ja) * 1995-10-30 1997-05-13 Fujitsu Ltd 導電膜とその形成方法及び磁気抵抗効果ヘッド
KR970052931A (ko) * 1995-12-11 1997-07-29 김광호 텅스텐 질화박막 형성방법 및 이를 이용한 금속배선 형성방법
US7510961B2 (en) * 1997-02-14 2009-03-31 Micron Technology, Inc. Utilization of energy absorbing layer to improve metal flow and fill in a novel interconnect structure
US5933758A (en) * 1997-05-12 1999-08-03 Motorola, Inc. Method for preventing electroplating of copper on an exposed surface at the edge exclusion of a semiconductor wafer
SE9704150D0 (sv) * 1997-11-13 1997-11-13 Abb Research Ltd Semiconductor device of SiC with insulating layer a refractory metal nitride layer
JP2937998B1 (ja) 1998-03-16 1999-08-23 山形日本電気株式会社 配線の製造方法
US6153521A (en) * 1998-06-04 2000-11-28 Advanced Micro Devices, Inc. Metallized interconnection structure and method of making the same
SE515836C3 (sv) 1999-05-17 2001-11-06 Ericsson Telefon Ab L M Förfarande för tillverkning av en bipolär högfrekvent kiseltransistor samt effekttransistoranordning
SE516338C2 (sv) 1999-05-31 2001-12-17 Ericsson Telefon Ab L M RF-effekttransistor med kollektor upp
JP2001118927A (ja) * 1999-10-22 2001-04-27 Mitsubishi Electric Corp 半導体装置およびその製造方法
US6316831B1 (en) 2000-05-05 2001-11-13 Aptos Corporation Microelectronic fabrication having formed therein terminal electrode structure providing enhanced barrier properties
US6740603B2 (en) * 2001-02-01 2004-05-25 Texas Instruments Incorporated Control of Vmin transient voltage drift by maintaining a temperature less than or equal to 350° C. after the protective overcoat level
JP4571781B2 (ja) * 2003-03-26 2010-10-27 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
JP4502691B2 (ja) * 2003-04-16 2010-07-14 昭和電工株式会社 ｐ形オーミック電極構造、それを備えた化合物半導体発光素子及びＬＥＤランプ
JP3678239B2 (ja) * 2003-06-30 2005-08-03 セイコーエプソン株式会社 半導体装置及びその製造方法、回路基板並びに電子機器
US7315077B2 (en) * 2003-11-13 2008-01-01 Fairchild Korea Semiconductor, Ltd. Molded leadless package having a partially exposed lead frame pad
US7307314B2 (en) * 2004-06-16 2007-12-11 Cree Microwave Llc LDMOS transistor with improved gate shield
US7531426B2 (en) * 2005-08-19 2009-05-12 Honeywell International Inc. Approach to high temperature wafer processing
US20070238222A1 (en) * 2006-03-28 2007-10-11 Harries Richard J Apparatuses and methods to enhance passivation and ILD reliability
US8420520B2 (en) * 2006-05-18 2013-04-16 Megica Corporation Non-cyanide gold electroplating for fine-line gold traces and gold pads
US8071441B2 (en) * 2008-02-14 2011-12-06 Micron Technology, Inc Methods of forming DRAM arrays
EP2280417B1 (en) * 2008-04-15 2015-07-22 Sumitomo Electric Industries, Ltd. Semiconductor device and method for manufacturing the same
TWI394239B (zh) * 2008-12-17 2013-04-21 Univ Ishou The integrated circuit with the isolation layer of metal ion migration and its encapsulation structure
CN102479744B (zh) * 2010-11-25 2014-02-26 上海华虹宏力半导体制造有限公司 铝填孔连线工艺
RU2494492C1 (ru) * 2012-06-07 2013-09-27 Общество с ограниченной ответственностью "Компания РМТ" Способ создания токопроводящих дорожек
KR101877878B1 (ko) * 2012-06-11 2018-07-13 에스케이하이닉스 주식회사 복층의 스토리지노드를 구비한 반도체장치 및 그 제조 방법
US20140209926A1 (en) * 2013-01-28 2014-07-31 Win Semiconductors Corp. Semiconductor integrated circuit
US20140264865A1 (en) * 2013-03-14 2014-09-18 Infineon Technologies Ag Semiconductor device and manufacturing method thereof
EP2793265B1 (en) * 2013-04-15 2017-06-07 Nexperia B.V. Semiconductor device and manufacturing method
US10192970B1 (en) * 2013-09-27 2019-01-29 The United States Of America As Represented By The Administrator Of National Aeronautics And Space Administration Simultaneous ohmic contact to silicon carbide
US9905658B2 (en) * 2013-11-26 2018-02-27 Nxp Usa, Inc. Transistors with field plates resistant to field plate material migration and methods of their fabrication
US9240450B2 (en) 2014-02-12 2016-01-19 Infineon Technologies Ag IGBT with emitter electrode electrically connected with impurity zone
US9401328B2 (en) 2014-12-22 2016-07-26 Stmicroelectronics S.R.L. Electric contact structure having a diffusion barrier for an electronic device and method for manufacturing the electric contact structure
US9704804B1 (en) 2015-12-18 2017-07-11 Texas Instruments Incorporated Oxidation resistant barrier metal process for semiconductor devices
JP2018142562A (ja) * 2017-02-24 2018-09-13 株式会社村田製作所 半導体装置
US10903329B2 (en) * 2018-02-13 2021-01-26 Wisconsin Alumni Research Foundation Contact photolithography-based nanopatterning using photoresist features having re-entrant profiles
CN110459479B (zh) * 2018-05-07 2021-07-13 北京北方华创微电子装备有限公司 阻挡层沉积方法、金凸块的底层金属薄膜及其制备方法
US20220262754A1 (en) * 2021-02-18 2022-08-18 International Business Machines Corporation Sintering a nanoparticle paste for semiconductor chip join

Family Cites Families (34)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3833842A (en) * 1970-03-09 1974-09-03 Texas Instruments Inc Modified tungsten metallization for semiconductor devices
US4042950A (en) * 1976-03-01 1977-08-16 Advanced Micro Devices, Inc. Platinum silicide fuse links for integrated circuit devices
US4141022A (en) * 1977-09-12 1979-02-20 Signetics Corporation Refractory metal contacts for IGFETS
US4330343A (en) * 1979-01-04 1982-05-18 The United States Of America As Represented By The Secretary Of The Navy Refractory passivated ion-implanted GaAs ohmic contacts
US4300149A (en) * 1979-09-04 1981-11-10 International Business Machines Corporation Gold-tantalum-titanium/tungsten alloy contact for semiconductor devices and having a gold/tantalum intermetallic barrier region intermediate the gold and alloy elements
US4354307A (en) * 1979-12-03 1982-10-19 Burroughs Corporation Method for mass producing miniature field effect transistors in high density LSI/VLSI chips
US4507851A (en) * 1982-04-30 1985-04-02 Texas Instruments Incorporated Process for forming an electrical interconnection system on a semiconductor
US4845050A (en) * 1984-04-02 1989-07-04 General Electric Company Method of making mo/tiw or w/tiw ohmic contacts to silicon
US4566026A (en) * 1984-04-25 1986-01-21 Honeywell Inc. Integrated circuit bimetal layer
JPS6212003A (ja) 1985-07-10 1987-01-21 株式会社フジクラ 自己潤滑性絶縁電線
US4965218A (en) * 1985-10-21 1990-10-23 Itt Corporation Self-aligned gate realignment employing planarizing overetch
JPH0691125B2 (ja) * 1985-11-20 1994-11-14 古河電気工業株式会社 半導体装置
US4702967A (en) * 1986-06-16 1987-10-27 Harris Corporation Multiple-layer, multiple-phase titanium/nitrogen adhesion/diffusion barrier layer structure for gold-base microcircuit interconnection
JPS6373660A (ja) * 1986-09-17 1988-04-04 Fujitsu Ltd 半導体装置
US4732865A (en) * 1986-10-03 1988-03-22 Tektronix, Inc. Self-aligned internal mobile ion getter for multi-layer metallization on integrated circuits
US4907066A (en) * 1986-12-05 1990-03-06 Cornell Research Foundation, Inc. Planar tungsten interconnect with implanted silicon
US4753851A (en) * 1987-05-29 1988-06-28 Harris Multiple layer, tungsten/titanium/titanium nitride adhesion/diffusion barrier layer structure for gold-base microcircuit interconnection
US5055908A (en) * 1987-07-27 1991-10-08 Texas Instruments Incorporated Semiconductor circuit having metallization with TiW
US4787958A (en) * 1987-08-28 1988-11-29 Motorola Inc. Method of chemically etching TiW and/or TiWN
US4927505A (en) * 1988-07-05 1990-05-22 Motorola Inc. Metallization scheme providing adhesion and barrier properties
US4880708A (en) * 1988-07-05 1989-11-14 Motorola, Inc. Metallization scheme providing adhesion and barrier properties
JP2537413B2 (ja) * 1989-03-14 1996-09-25 三菱電機株式会社 半導体装置およびその製造方法
US5173449A (en) * 1989-06-05 1992-12-22 Motorola, Inc. Metallization process
US5041191A (en) * 1989-11-13 1991-08-20 Rockwell International Corporation Diffusion barrier for thin film hybrid circuits
DE4129647B4 (de) * 1990-09-28 2009-02-12 Siemens Ag Vorderseiten-Metallisierung zum Drahtbonden für ein III-V Halbleiterbauelement und Verfahren
US5136364A (en) * 1991-06-12 1992-08-04 National Semiconductor Corporation Semiconductor die sealing
US5156998A (en) * 1991-09-30 1992-10-20 Hughes Aircraft Company Bonding of integrated circuit chip to carrier using gold/tin eutectic alloy and refractory metal barrier layer to block migration of tin through via holes
US5164331A (en) * 1991-10-03 1992-11-17 Hewlett-Packard Company Method of forming and etching titanium-tungsten interconnects
US5240880A (en) * 1992-05-05 1993-08-31 Zilog, Inc. Ti/TiN/Ti contact metallization
JP2861629B2 (ja) * 1992-05-27 1999-02-24 日本電気株式会社 半導体装置
US5286676A (en) * 1992-06-15 1994-02-15 Hewlett-Packard Company Methods of making integrated circuit barrier structures
US5249728A (en) * 1993-03-10 1993-10-05 Atmel Corporation Bumpless bonding process having multilayer metallization
US5343071A (en) * 1993-04-28 1994-08-30 Raytheon Company Semiconductor structures having dual surface via holes
MY115336A (en) * 1994-02-18 2003-05-31 Ericsson Telefon Ab L M Electromigration resistant metallization structures and process for microcircuit interconnections with rf-reactively sputtered titanium tungsten and gold

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1315158C (zh) * 2003-11-18 2007-05-09 国际商业机器公司 选择性电镀半导体器件的输入/输出焊盘的方法

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JPH08512435A (ja) 1996-12-24
EP0695463A1 (en) 1996-02-07
NO954040L (no) 1995-12-14
US5821620A (en) 1998-10-13
CA2160234A1 (en) 1995-08-24
US5920794A (en) 1999-07-06
FI954942A (fi) 1995-11-24
BR9505846A (pt) 1996-02-13
MY115336A (en) 2003-05-31
TW293928B (zh) 1996-12-21
KR960702179A (ko) 1996-03-28
FI954942A0 (fi) 1995-10-17
AU1828795A (en) 1995-09-04
MX9504299A (es) 1997-05-31
CN1125999A (zh) 1996-07-03
KR100376955B1 (ko) 2003-06-19
WO1995022838A1 (en) 1995-08-24
SG52880A1 (en) 1998-09-28
US6211568B1 (en) 2001-04-03
NO954040D0 (no) 1995-10-11

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