CN1119771C - 在验证期间将输入数据加载到算法中的方法和装置 - Google Patents
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Abstract
用芯片卡进行支付的保密问题在验证期间将输人数据加载到算法中。以预先选定的次数(时钟脉冲数)分离数据块并切换后连接计数器之后的附加反馈,这会有助于提高借款和贷款数据的保密性。本发明可用于使用芯片卡的所有验证过程。
Description
技术领域
本发明涉及一种在验证期间将输入数据加载到算法中的方法和装置。
背景技术
已知该类的几种方法,它们用于各种电子现金卡,同时装置是依照EP 0616429 A1的用于芯片的数字电路。
例如,这里参考的方法类型可以从ETSI D/EN/TE 090114和欧州专利申请0605070中获知,其中ETSI D/EN/TE 090114是1992年2月7日第4版,参阅关于通信用IC卡和终端的终端设备(TE)要求的第4部分-支付方法。
除了具有规定值(起始信用)的电话磁卡(用于磁卡电话)外,还有用于支付小金额的具有类似功能的电子现金卡;这些现金卡的重要性在不断增长。对于“用芯片卡支付”的事件,用于验证卡和信用量的读卡器模块和保密模块(SM)被整合在设备中。
EP0605070A2还描述了一种对芯片卡转帐货币金额(借和贷)的方法,由此将芯片卡中主要的存贮单元至少分成两个存贮单元,一个单元用于借款金额(即,电子现金卡),类似于电话磁卡,另一个单元用于还贷金额,类似于信用卡。通过施加常规的保密条件,计划在这两个区域之间转移款额,以便补充电子现金卡。
为了避免未被验证的人进入读卡器及其内置的保密模块,避免特别保护并且避免安装对操作者十分昂贵的专用线,已经提出一种步骤,读卡器的操作者在发生任何支付行为之前,将具有芯片卡功能的保密模块插入读卡器;当持卡人将他或她的电子现金卡插入读卡器中时,芯片卡的数据区被读出,从而验证卡,并核查剩余的货款金额;接着,对保密模块进行验证,并进行一个或几个承兑核查;最后,用保密功能将应付金额或输入金额记入持卡人芯片卡的借方,并将其与保密模块中货币金额的累加计数器相加;在这种支付行为后,将保密模块的计数器设置传送给开票中心。
发明内容
本发明的目的是针对操作和误动作,提高电子现金卡读卡器的保密性。
为了实现该目的,本发明提供了一种在电子现金卡和保密模块之间进行在验证期间将输入数据加载到算法中的方法。在该方法中,持卡人有一定量的存款存储在所述卡中,在每个POS中,通过保密函数将要支付的金额或持卡人输入的金额记入借方;在保密模块的求和计数器中将各笔金额相加并求和;对于验证算法,使用线性反馈移位寄存器,它的非线性函数使后连接计数器用密码方式相乘,并且输入数据,诸如随机数、保密密钥和非保密卡数据等,进入该算法;将输入数据分成若干数据块,并且当把所述数据块加载到线性反馈移位寄存器中时,一附加反馈在后连接计数器之后加到所述移位寄存器,并且在预定数目的时钟脉冲后切断附加反馈。
在本发明的方法中,可以将卡数据(D)和密钥(K)作为第一块输入,将随机数(R)作为第二块输入。
在本发明的方法中,为了计算验证令牌已按次序加载输入数据后,在输入数据加载相位期间而非后续的相位期间,可以设置其它的计数器设置。
在本发明的方法中,第一后连接计数器的计数可以为1。
在本发明的方法中,选择计数器和要执行的时钟脉冲数,以便根据依赖于其它系统条件的时钟脉冲固定数计算验证令牌。
在本发明的方法中,可以在加载了所有输入数据后,马上就开始位输出。
在本发明的方法中,在加载所述块之后,并且所述附加反馈继续时,可以在输出位之前对整个电路连续加几个时钟脉冲而不加载输入数据。
在本发明的方法中,在加载块之后,并且在切断所述附加反馈之后,可以在输出位之前对整个电路连续加预定数目的时钟脉冲,而不加载输入数据。
本发明还提供了一种适用于上述方法的装置。该装置使用密码MAC功能,包括一线性反馈移位寄存器,所述线性反馈移位寄存器具有非线性前馈功能,能够阅读所述移位寄存器,并且通过计数器影响移位寄存器输出,所述线性反馈移位寄存器后连接另一个计数器;还包括具有后连接计数器的依照所述线性反馈移位寄存器建立的电路,并且用于验证,以密码方式将其乘以可以切断的附加非线性反馈。
在本发明的装置中,可以在锁存器之前第一后连接计数器之后,读取所述附加反馈。
在本发明的装置中,可以读取第一后连接计数器之后的来自所述锁存器的所述附加反馈。
在本发明的装置中,可以读取第二后连接计数器之后的附加反馈。
在本发明的装置中,附加反馈可以是对第一后连接计数器之后锁存器之前的读出值、第一后连接计数器之后的来自锁存器的读出值,以及第二后连接计数器的读出值的异或和。
在本发明的装置中,可以按大小划分或缩小计数器。
具体实施方式
以下举例详细描述了本发明,包括它的作用、优点和应用领域。
验证算法主要用于识别保密性。但是在验证过程中,其它数据除了辨识芯片卡和个人身份之外,还可能起保密模块(SM)的作用;必须保证所述其它数据的正确性。例如,可以在一个验证过程中使用具有密钥(K)和随机数(R)的非保密卡数据(D)。对于电子现金卡,对借和贷使用分开的保密功能,并用密码校验和来校验每一种情况。
本发明的方法用密码令牌进行借贷交易,只要通过计数器设置并使用询问/答复过程来完成验证和密码校验和。在该情况下,单个询问/答复过程(由此,保密模块SM只提供一个随机数并且芯片卡只计算出一个答复),可以证实保密模块的身份(验证)和内部计算器设置。
为了达到这一目的,在内部用“密钥控制的散列函数”=MAC函数来对诸如计算器设置和随机数等可变输入数据进行初始化处理,从而将芯片卡的专用密钥用作密钥。然后,将计数器设置和随机数所产生的令牌与例如异或(XOR)或线性反馈移位寄存器相关联(多半用密码的非保密方法),接着输出,使被保护的数据完整,并具有足够的密码功能。
就密钥控制的散列函数来说,该方法是实用的,其中密钥控制的散列函数只在内部使用,不必满足有关其保密性的特别高的要求;另外,由于这些函数的结果不“脱离”芯片卡,可以使用相对简单的函数。但是,有效地防止了数据的操纵。
本发明的例举假设使用具有附加非线性函数和后连接计数器(post-connected counter)的线性反馈移位寄存器(LFSR):
0.在LFSR中,在后连接计数器后采用附加的反馈电路。
1.当LFSR的反馈和附加反馈都有效时,由非保密卡数据(D)和保密密钥(K)组成的输入数据读入LFSR。
2.产生一定数量的时钟脉冲,在读入数据输入之前。
3.当LFSR的反馈和附加反馈都有效时,读入由随机数据(R)组成的输入数据。
4.切断附加反馈电路,并且在必要时重新设置计数器。
5.产生一些数量的时钟脉冲,并在这些脉冲期间,根据当前计数器的设置产生输出位。
Claims (27)
1.一种在电子现金卡和保密模块之间进行在验证期间将输入数据加载到算法中的方法,其特征在于,持卡人有一定量的存款存储在所述卡中,在每个POS中,通过保密函数将要支付的金额或持卡人输入的金额记入借方;在保密模块的求和计数器中将各笔金额相加并求和;对于验证算法,使用线性反馈移位寄存器,它的非线性函数使后连接计数器用密码方式相乘,并且输入数据,诸如随机数、保密密钥和非保密卡数据等,进入该算法;将输入数据分成若干数据块,并且当把所述数据块加载到线性反馈移位寄存器中时,一附加反馈在后连接计数器之后加到所述移位寄存器,并且在预定数目的时钟脉冲后切断附加反馈。
2.如权利要求1所述的方法,其特征在于,将卡数据(D)和密钥(K)作为第一块输入,将随机数(R)作为第二块输入。
3.如权利要求1或2所述的方法,其特征在于,为了计算验证令牌已按次序加载输入数据后,在输入数据加载相位期间而非后续的相位期间,设置其它的计数器设置。
4.如权利要求1或2所述的方法,其特征在于,第一后连接计数器的计数为1。
5.如权利要求1或2所述的方法,其特征在于,用这样的方法选择计数器和要执行的时钟脉冲数,以便根据依赖于其它系统条件的时钟脉冲固定数计算验证令牌。
6.如权利要求1或2中任何一项所述的方法,其特征在于,加载了所有输入数据后,马上就开始位输出。
7.如权利要求3中任何一项所述的方法,其特征在于,加载了所有输入数据后,马上就开始位输出。
8.如权利要求4中任何一项所述的方法,其特征在于,加载了所有输入数据后,马上就开始位输出。
9.如权利要求5中任何一项所述的方法,其特征在于,加载了所有输入数据后,马上就开始位输出。
10.如权利要求1或2所述的方法,其特征在于,在依照权利要求1加载所述块之后,并且所述附加反馈继续时,在输出位之前对整个电路连续加几个时钟脉冲而不加载输入数据。
11.如权利要求3所述的方法,其特征在于,在依照权利要求1加载所述块之后,并且所述附加反馈继续时,在输出位之前对整个电路连续加几个时钟脉冲而不加载输入数据。
12.如权利要求4所述的方法,其特征在于,在依照权利要求1加载所述块之后,并且所述附加反馈继续时,在输出位之前对整个电路连续加几个时钟脉冲而不加载输入数据。
13.如权利要求5所述的方法,其特征在于,在依照权利要求1加载所述块之后,并且所述附加反馈继续时,在输出位之前对整个电路连续加几个时钟脉冲而不加载输入数据。
14.如权利要求6所述的方法,其特征在于,在依照权利要求1加载所述块之后,并且所述附加反馈继续时,在输出位之前对整个电路连续加几个时钟脉冲而不加载输入数据。
15.如权利要求7-9中任何一项所述的方法,其特征在于,在依照权利要求1加载所述块之后,并且所述附加反馈继续时,在输出位之前对整个电路连续加几个时钟脉冲而不加载输入数据。
16.如权利要求1或2所述的方法,其特征在于,在依照权利要求1加载块之后,并且在切断所述附加反馈之后,在输出位之前对整个电路连续加预定数目的时钟脉冲,而不加载输入数据。
17.如权利要求3所述的方法,其特征在于,在依照权利要求1加载块之后,并且在切断所述附加反馈之后,在输出位之前对整个电路连续加预定数目的时钟脉冲,而不加载输入数据。
18.如权利要求4所述的方法,其特征在于,在依照权利要求1加载块之后,并且在切断所述附加反馈之后,在输出位之前对整个电路连续加预定数目的时钟脉冲,而不加载输入数据。
19.如权利要求5所述的方法,其特征在于,在依照权利要求1加载块之后,并且在切断所述附加反馈之后,在输出位之前对整个电路连续加预定数目的时钟脉冲,而不加载输入数据。
20.如权利要求6所述的方法,其特征在于,在依照权利要求1加载块之后,并且在切断所述附加反馈之后,在输出位之前对整个电路连续加预定数目的时钟脉冲,而不加载输入数据。
21.如权利要求7-9中任何一项所述的方法,其特征在于,在依照权利要求1加载块之后,并且在切断所述附加反馈之后,在输出位之前对整个电路连续加预定数目的时钟脉冲,而不加载输入数据。
22.一种在验证期间将输入数据加载到算法中的装置,其特征在于,该装置使用密码MAC功能,包括一线性反馈移位寄存器,所述线性反馈移位寄存器具有非线性前馈功能,能够阅读所述移位寄存器,并且通过计数器影响移位寄存器输出,所述线性反馈移位寄存器后连接另一个计数器;还包括具有后连接计数器的依照所述线性反馈移位寄存器建立的电路,并且用于验证,以密码方式将其乘以可以切断的附加非线性反馈。
23.如权利要求22所述的装置,其特征在于,在锁存器之前第一后连接计数器之后,读取所述附加反馈。
24.如权利要求22所述的装置,其特征在于,读取第一后连接计数器之后的来自所述锁存器的所述附加反馈。
25.如权利要求22所述的装置,其特征在于,读取第二后连接计数器之后的附加反馈。
26.如权利要求22所述的装置,其特征在于,附加反馈是对第一后连接计数器之后锁存器之前的读出值、第一后连接计数器之后的来自锁存器的读出值,以及第二后连接计数器的读出值的异或和。
27.如权利要求22所述的装置,其特征在于,按大小划分或缩小计数器。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
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DE19622533.7 | 1996-06-05 | ||
DE19622533A DE19622533A1 (de) | 1996-06-05 | 1996-06-05 | Verfahren und Vorrichtung zum Laden von Inputdaten in einen Algorithmus bei der Authentikation |
Publications (2)
Publication Number | Publication Date |
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CN1221507A CN1221507A (zh) | 1999-06-30 |
CN1119771C true CN1119771C (zh) | 2003-08-27 |
Family
ID=7796201
Family Applications (1)
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CN97195212A Expired - Lifetime CN1119771C (zh) | 1996-06-05 | 1997-06-04 | 在验证期间将输入数据加载到算法中的方法和装置 |
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US (1) | US7113592B1 (zh) |
EP (1) | EP0909434B1 (zh) |
JP (1) | JP2000512043A (zh) |
CN (1) | CN1119771C (zh) |
AT (1) | ATE207643T1 (zh) |
AU (1) | AU3032197A (zh) |
DE (2) | DE19622533A1 (zh) |
WO (1) | WO1997046983A2 (zh) |
Families Citing this family (9)
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WO1999022486A1 (de) | 1997-10-28 | 1999-05-06 | Brokat Infosystems Ag | Verfahren zum digitalen signieren einer nachricht |
DE19818726C1 (de) * | 1998-04-27 | 1999-10-14 | Esd Information Technology Ent | Ladeterminal für Geldkarten sowie Verfahren zum Betrieb eines solchen |
NL1012581C2 (nl) * | 1999-07-13 | 2001-01-16 | Koninkl Kpn Nv | Werkwijze voor het beschermen van een draagbare kaart. |
DE10040854A1 (de) * | 2000-08-21 | 2002-03-21 | Infineon Technologies Ag | Chipkarte |
FR2826531B1 (fr) | 2001-06-26 | 2003-10-24 | France Telecom | Procede cryptographique pour la protection d'une puce electronique contre la fraude |
KR100480258B1 (ko) * | 2002-10-15 | 2005-04-07 | 삼성전자주식회사 | 무선 근거리 네트워크에서 고속 핸드오버를 위한 인증방법 |
JP4254201B2 (ja) * | 2002-10-31 | 2009-04-15 | ソニー株式会社 | スクランブラ、送信装置および受信装置 |
CN100409138C (zh) * | 2004-07-21 | 2008-08-06 | 京瓷美达株式会社 | 密码验证装置及验证方法 |
US9940486B2 (en) * | 2015-02-23 | 2018-04-10 | Cisco Technology, Inc. | Detection of hardware tampering |
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FR2650097B1 (fr) * | 1989-07-19 | 1992-12-31 | Pailles Jean Claude | Carte a microcircuit cable et procede de transaction entre une carte a microcircuit cable correspondante et un terminal |
DE69128981T2 (de) * | 1990-06-01 | 1998-08-06 | Toshiba Kawasaki Kk | Geheimübertragungsverfahren und Geheimübertragungseinrichtung |
DE4119924C3 (de) * | 1991-06-17 | 1996-06-20 | Siemens Ag | Verfahren zur Sicherung von ladbaren Guthaben in Chipkarten |
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DE59307854D1 (de) * | 1992-12-01 | 1998-01-29 | Landis & Gyr Business Support | Verfahren zur Abgeltung von Dienstleistungen und/oder Waren und Einrichtung zur Durchführung des Verfahrens |
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-
1996
- 1996-06-05 DE DE19622533A patent/DE19622533A1/de not_active Ceased
-
1997
- 1997-06-04 DE DE59705095T patent/DE59705095D1/de not_active Expired - Lifetime
- 1997-06-04 CN CN97195212A patent/CN1119771C/zh not_active Expired - Lifetime
- 1997-06-04 JP JP10500229A patent/JP2000512043A/ja not_active Abandoned
- 1997-06-04 WO PCT/EP1997/002894 patent/WO1997046983A2/de active IP Right Grant
- 1997-06-04 AU AU30321/97A patent/AU3032197A/en not_active Abandoned
- 1997-06-04 EP EP97925042A patent/EP0909434B1/de not_active Expired - Lifetime
- 1997-06-04 AT AT97925042T patent/ATE207643T1/de active
- 1997-12-20 US US09/202,024 patent/US7113592B1/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
DE59705095D1 (de) | 2001-11-29 |
JP2000512043A (ja) | 2000-09-12 |
EP0909434B1 (de) | 2001-10-24 |
CN1221507A (zh) | 1999-06-30 |
ATE207643T1 (de) | 2001-11-15 |
DE19622533A1 (de) | 1997-12-11 |
WO1997046983A3 (de) | 1998-02-26 |
US7113592B1 (en) | 2006-09-26 |
WO1997046983A2 (de) | 1997-12-11 |
EP0909434A2 (de) | 1999-04-21 |
AU3032197A (en) | 1998-01-05 |
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