CN1129960C - 铜基材料表层的机械化学抛光方法 - Google Patents
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- -1 Cu-Si Chemical compound 0.000 description 1
- BPQQTUXANYXVAA-UHFFFAOYSA-N Orthosilicate Chemical compound [O-][Si]([O-])([O-])[O-] BPQQTUXANYXVAA-UHFFFAOYSA-N 0.000 description 1
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- 230000007935 neutral effect Effects 0.000 description 1
- RVTZCBVAJQQJTK-UHFFFAOYSA-N oxygen(2-);zirconium(4+) Chemical compound [O-2].[O-2].[Zr+4] RVTZCBVAJQQJTK-UHFFFAOYSA-N 0.000 description 1
- NNHHDJVEYQHLHG-UHFFFAOYSA-N potassium silicate Chemical compound [K+].[K+].[O-][Si]([O-])=O NNHHDJVEYQHLHG-UHFFFAOYSA-N 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/7684—Smoothing; Planarisation
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- B—PERFORMING OPERATIONS; TRANSPORTING
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- B24B37/044—Lapping machines or devices; Accessories designed for working plane surfaces operating processes therefor characterised by the composition of the lapping agent
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- C—CHEMISTRY; METALLURGY
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
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Abstract
一种使用抛光组合物对铜基材料表层的机械化学抛光方法，其特征在于所述抛光组合物包括彼此未以硅氧键连接的单个胶体二氧化硅颗粒的一种水悬浮液，其平均粒度在10-100nm之间，且水悬浮液的pH在1-5之间。
Description
本发明涉及一种铜基材料表层的机械化学抛光方法，具体涉及形成集成电路的互连通道。
半导体互连通道一般通过平版印刷成大约1μm厚的铝膜然后通过反应性离子刻蚀来制备。随后用介电薄层最常用氧化硅将其包封而得到，所述氧化硅例如通过原硅酸四乙酯(TEOS)的气相分解得到。
每单位面积三极管数目的增加，也叫作集成密度，必须减少互连通道的宽度。这就导致增大这些互连通道以及电迁移电阻的现象。
铜覆盖铝的优点是对电迁移得到良好的电阻。其比电阻比铝的低。因此铜可以代替铝作为集成电路的互连通道结构。
目前，难于在铜内通过反应性离子刻蚀(RIE)来刻蚀互连通道。
在铜内规划互连通道的镶嵌方法是目前公知最好的方法。镶嵌方法由基体上沉积氧化硅介电层构成。例如通过气相沉积TEOS得到这种介电层。介电层一般有大约2μm厚度。然后通过照相平版印刷将设计的互连电路转印在这种介电层上，再进行反应性离子刻蚀(RIE)。这种刻蚀一般要形成大约一个μm深度的沟槽。
随后在介电层上一般沉积大约100nm厚的扩散阻挡层。这种扩散阻挡层可防止铜在介电材料内扩散。扩散阻挡层通常包括钛或氮化钛(TiN)。之后沉积大约2μm厚的铜基材料表层。铜基材料可以是元素铜或铜合金，特别是Cu-Si，Cu-Al，Cu-Si-Al或Cu-Ag。
铜基材料必须用机械化学抛光，直至达到氧化硅介电层的表面。因此，铜基材料仅仅保留在沟槽内。
图1和图2说明镶嵌方法。具体言之，图1表示机械化学抛光前集成电路互连通道的截面部分。这种截面部分包括已刻蚀沟槽4的介电材料内的表层1。在表层1上沉积扩散阻挡层构成的表层2，这种表层2自身被铜基材料的表层3覆盖。图2表示机械化学抛光后同样的集成电路互连通道的截面部分，后者是以一种理想方式进行的。
进行铜基表层的机械化学抛光必须注意避免两种现象：
-对下面氧化硅表层的破坏一般记作磨蚀现象。其结果是局部引入棱边，它是不利于产生所要求平面化。
-沟槽内互连通道的过分抛光一般记作“形成凹坑”现象。这种现象也会导致引入棱边，而且减少互连通道的厚度，其结果则降低它的传导性。
图3和图4可说明上述两种现象。具体言之，图3表示抛光后有磨蚀现象的图1集成电路的互连通道截面部分。图4表示抛光后有形成凹坑现象的图1集成电路的互连通道截面部分。
磨蚀和形成凹坑两种现象主要由于铜基材料不均匀抛光所至。事实上，抛光消除铜基表层必须要有一定的过分抛光，以便避免电子器件之间电连接的所有风险。这就导致一种互连通道和还未覆盖介电区域的过分抛光。
在US 5622525中，提供一种对铜或主要含铜合金的抛光方法，其中使用一种抛光组合物，包括一种胶体二氧化硅颗粒在碱性溶液中的悬浮液、去离子水和化学活性剂。二氧化硅颗粒的平均粒度在20-50nm之间。
US 5575885叙述一种铜或铜合金薄膜的抛光溶液，包括一种选自氨基乙酸和氨基磺酸的有机酸、一种例如过氧化氢或次氯酸钠的氧化剂和水。该抛光溶液还另外包括研磨颗粒，选自二氧化硅，二氧化锆，铈和铝的氧化物。这些研磨颗粒的平均粒度在20-100nm之间。这些碱性溶液有中性pH或优选在9-14之间的碱性pH。
EP-A-0747939叙述另一种铜或铜合金的抛光组合物。该抛光组合物包括能与铜形成配合物的水溶性有机酸，研磨抛光颗粒和水。该研磨颗粒选自二氧化硅，氧化锆，铈和铝的氧化物；其平均粒度在20-100nm之间。
铜或铜合金的抛光方法通常造成低劣的抛光均匀性，特别是与碱性研磨剂使用时。
因此，本发明第一个目的是提供一种机械化学抛光方法，该方法可以均匀规则地消除铜基材料。
本发明另一个目的是提供一种在集成电路的铜基材料内产生互连的方法，能避免磨蚀和形成凹坑的现象。
本发明还一个目的是提供一种用于抛光铜或铜合金材料的胶体二氧化硅基抛光组合物。
因此，本发明涉及一种使用抛光组合物的机械化学抛光铜基材料的方法，其特征在于所述抛光组合物包括彼此未以硅氧键连接的单个胶体二氧化硅颗粒的一种水悬浮液，其平均粒度在10-100nm优选25-50nm之间，且水悬浮液的pH在1-5之间。
本发明人注意到，通过使用以下抛光组合物，即包括彼此未以硅氧键连接的单个胶体二氧化硅颗粒的一种水悬浮液，其平均粒度在10-100nm优选25-50nm之间，且水悬浮液的pH在1-5之间的组合物，可以在铜表层抛光速度、抛光均匀性百分比和令人满意的表面状态之间得到一种优异的均衡。
本发明方法使用的胶体二氧化硅酸性水悬浮液，既可从碱性硅酸盐特别是硅酸钠或硅酸钾得到又可从硅酸乙酯得到。这种方法更具体详述见K.K.Iler在“二氧化硅化学”一书第9章p331-343，WileyInterscience出版社，1979。按照该方法得到的胶体二氧化硅颗粒以彼此未以硅氧键连接的单个颗粒形式存在。
胶体二氧化硅颗粒悬浮液的pH优选在2-3.5之间。
根据本发明优越性的一个方面，胶体二氧化硅颗粒的平均粒度在10-100nm优选25-50nm之间，最优选35nm。
根据本发明优越性的另一方面，胶体二氧化硅颗粒是“均匀分布”的。应当了解这个术语在本发明范围内是指80％优选90％的胶体二氧化硅颗粒具有相同的检测粒度，误差10％，优选5％。举例说明，粒度35nm均匀分布的胶体二氧化硅颗粒由至少80％优选90％的具有35±3.5nm优选35±1.7nm粒度的颗粒构成。
本发明范围内使用的抛光组合物包括多于20wt％优选30-40wt％的胶体二氧化硅颗粒。
尽管通过水内仅包括胶体二氧化硅悬浮的抛光组合物可得到非常良好的抛光效果，并未规定该组合物不能含有抛光铜基材料通常使用的其它化合物。这些化合物具体包括诸如过氧化氢的氧化剂或有机酸，特别是配合铜的有机酸，如US 5575885和EP-A-747939所列举的有机酸。
另一方面，本发明涉及在集成电路的铜基材料内制备互连通道的方法，按照如下步骤进行：
-在基体上沉积氧化硅介电层，
-在介电层表面上刻蚀互连电路的沟槽，
-如果需要，在介电层上沉积扩散阻挡层，
-在介电层或者如果需要在扩散阻挡层上沉积铜基材料层，
-通过机械化学抛光对基于含铜材料的表层抛光，该方法特征在于通过抛光组合物进行铜基材料的机械化学抛光，组合物包括彼此未以硅氧键连接的单个胶体二氧化硅颗粒的一种悬浮液，所述颗粒平均粒度在10-100nm优选25-50nm之间，且水悬浮液的pH在1-5优选2-3.5之间。
本文详述中，铜基材料由元素铜或选自如下一组的合金构成：Cu-Si，Cu-Al，Cu-Si-Al或Cu-Ag。
下面实施例的目的是简单说明本发明。这些实施例中，使用的插件已沉积大约1μm厚的铜层。然后在PRESI M550型抛光机上按照如下条件抛光铜层：
施加压力 0.25daN/cm2(1daN/cm2＝105Pa)
盘速度 30rpm
头速度 30rpm
温度 20℃
研磨速率 250cm3/mn
织物 IC1400K带皱纹的Rodel产品
进行以下三种类型的试验：
a)抛光组合物对铜层的磨蚀速度试验。通过铜板抛光前和每分钟抛光后不同厚度来测量其磨蚀速度，用/min表示。
b)抛光磨蚀均匀性试验(U)
从试样板不同位点的铜厚度差异测量磨蚀均匀性。根据同样铜板抛光前后铜层的测量用下面公式计算：
U＝((最大厚度-最小厚度)/2×去除的平均厚度)×100
该公式中，通过测量铜层在处理后49个不同位点厚度来决定最大和最小厚度。最大厚度相应于测量的最大厚度，最小厚度相应于测量的最小厚度。去除的平均厚度是抛光前后的平均厚度之差，这些平均值从49个位点测量值计算出。
c)肉眼观察试验，光学显微镜下检测铜板上可能的沟槽及其大小。
实施例1
铜层置于板上然后在上述条件下用包括彼此未以硅氧键连接的单个胶体二氧化硅颗粒水悬浮液的抛光组合物进行抛光，其特征如下：
水悬浮液的pH 2.5
胶体二氧化硅颗粒的平均粒度 35nm
胶体二氧化硅的重量浓度 30wt％
该抛光组合物能够得到以下结果：
-抛光速度1800/mn
-均匀性百分数8％
-光学显微镜下未见沟槽。
实施例2
前述同样条件下用包括彼此未以硅氧键连接的个体胶体二氧化硅颗粒水悬浮液的抛光组合物抛光铜层，其特征如下：
水悬浮液的pH 2.5
胶体二氧化硅颗粒的平均粒度 50nm
胶体二氧化硅的重量浓度 30wt％
得到以下结果：
-抛光速度800/mn
-均匀性百分数11％
-光学显微镜下见到一些轻微沟槽。
实施例3(对比)
实施例1同样条件下用包括具有以下特性的胶体二氧化硅颗粒水悬浮液的抛光组合物抛光铜层，其特征如下：
水悬浮液的pH 11
胶体二氧化硅颗粒的平均粒度 50nm
胶体二氧化硅的重量浓度 30wt％
用氢氧化铵调节水溶液的pH到所要求值。
得到以下结果：
-抛光速度700/mn
-均匀性百分数40％
-肉眼观察到多个微细沟槽。
实施例1-3使用的抛光组合物既不含有氧化剂又不含有配合铜或不配合铜的有机酸；它们也不含有表面活性剂。
本发明抛光组合物可均匀规则地消除铜并同时避免出现沟槽。使用这些抛光组合物时没有观察到磨蚀和形成凹坑现象。
与此相反，用对比实施例3的抛光组合物时，pH为碱性，并未造成铜层的均匀抛光。为了保证在介电层的较高区域没有铜残留物，有效整体抛光这种铜层的难题会导致加大铜通道形成凹坑现象以及介电层磨蚀现象。
这些实施例表明，包括彼此未以硅氧键连接的单个胶体二氧化硅颗粒的一种水悬浮液，其粒度在10-100优选25-50nm之间，且水悬浮液的pH低于5抛光组合物，能得到铜基材料表层的高质量抛光。综合这些因素，就在抛光速度、均匀性百分数和令人满意的铜板处理状态之间得到了良好均衡，特别是在集成电路的铜基材料内产生了互连通道。
Claims (11)
1.一种铜基材料表层的机械化学抛光方法，该材料在半导体电子工业用作构成集成电路互连通道的材料，其特征在于该方法使用的抛光组合物包括彼此未以硅氧键连接的单个胶体二氧化硅颗粒的一种水悬浮液，其平均粒度在10-100nm之间，且水悬浮液的pH在1-5之间。
2.根据权利要求1的方法，其特征在于所述pH在2-3.5之间。
3.根据权利要求1的方法，其特征在于胶体二氧化硅颗粒的平均粒度在25-50nm之间。
4.根据权利要求3的方法，其特征在于单个胶体二氧化硅颗粒的平均粒度是35nm。
5.根据权利要求1的方法，其特征在于胶体二氧化硅颗粒是均匀分散的。
6.根据权利要求1的方法，其特征在于悬浮液包括大于20wt％的胶体二氧化硅颗粒。
7.根据权利要求6的方法，其特征在于悬浮液包括30-40wt％的胶体二氧化硅颗粒。
8.根据权利要求1的方法，其特征在于铜基材料由元素铜构成。
9.根据权利要求1的方法，其特征在于铜基材料是一种铜合金，选自Cu-Si，Cu-Al，Cu-Si-Al和Cu-Ag。
10.一种在集成电路的铜基材料内按照以下步骤制备互连通道的方法：
-在基体上沉积氧化硅介电层，
-在介电层表面上刻蚀互连电路的沟槽，
-在介电层上沉积铜基材料层，
-通过机械化学抛光对基于含铜材料的表层抛光，该方法特征在于通过抛光组合物进行铜基材料的机械化学抛光，该组合物包括彼此未以硅氧键连接的单个胶体二氧化硅颗粒的一种悬浮液，所述颗粒平均粒度在10-100nm之间，且水悬浮液的pH在1-5之间。
11.根据权利要求10的方法，还包括，在所述的在介电层表面刻蚀互连电路的沟槽的步骤之后，在介电层上沉积扩散阻挡层，然后在该扩散阻挡层上沉积所述铜基材料，然后通过机械化学抛光对基于含铜材料的表层抛光。
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| FR9809873 | 1998-07-31 | ||
| FR9809873A FR2781922B1 (fr) | 1998-07-31 | 1998-07-31 | Procede de polissage mecano-chimique d'une couche en un materiau a base de cuivre |
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| CN1129960C true CN1129960C (zh) | 2003-12-03 |
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| US (1) | US6302765B1 (zh) |
| EP (1) | EP0982766B1 (zh) |
| JP (1) | JP2000114213A (zh) |
| KR (1) | KR100596644B1 (zh) |
| CN (1) | CN1129960C (zh) |
| AT (1) | ATE408897T1 (zh) |
| DE (1) | DE69939569D1 (zh) |
| DK (1) | DK0982766T3 (zh) |
| ES (1) | ES2313763T3 (zh) |
| FR (1) | FR2781922B1 (zh) |
| MY (1) | MY118930A (zh) |
| SG (1) | SG78371A1 (zh) |
| TW (1) | TW431947B (zh) |
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| FR2781922B1 (fr) * | 1998-07-31 | 2001-11-23 | Clariant France Sa | Procede de polissage mecano-chimique d'une couche en un materiau a base de cuivre |
| MY118582A (en) * | 2000-05-12 | 2004-12-31 | Kao Corp | Polishing composition |
| JP2001347450A (ja) * | 2000-06-08 | 2001-12-18 | Promos Technologies Inc | 化学機械研磨装置 |
| US6737728B1 (en) * | 2000-10-12 | 2004-05-18 | Intel Corporation | On-chip decoupling capacitor and method of making same |
| EP1236765A1 (de) | 2001-02-28 | 2002-09-04 | hanse chemie GmbH | Siliciumdioxiddispersion |
| KR100444307B1 (ko) * | 2001-12-28 | 2004-08-16 | 주식회사 하이닉스반도체 | 반도체소자의 금속배선 콘택플러그 형성방법 |
| DE10208166B4 (de) * | 2002-02-26 | 2006-12-14 | Advanced Micro Devices, Inc., Sunnyvale | Verfahren zur Herstellung von Metallleitungen mit verbesserter Gleichförmigkeit auf einem Substrat |
| KR100672940B1 (ko) * | 2004-08-03 | 2007-01-24 | 삼성전자주식회사 | 금속막을 위한 화학적기계적 연마 슬러리 및 이를 이용한금속막의 화학적기계적 연마 방법 |
| KR100641348B1 (ko) * | 2005-06-03 | 2006-11-03 | 주식회사 케이씨텍 | Ｃｍｐ용 슬러리와 이의 제조 방법 및 기판의 연마 방법 |
| US20080148652A1 (en) * | 2006-12-21 | 2008-06-26 | Junaid Ahmed Siddiqui | Compositions for chemical mechanical planarization of copper |
| JP5403922B2 (ja) | 2008-02-26 | 2014-01-29 | 富士フイルム株式会社 | 研磨液および研磨方法 |
| CN101638557A (zh) * | 2008-08-01 | 2010-02-03 | 安集微电子（上海）有限公司 | 一种化学机械抛光液 |
| JP4629154B1 (ja) * | 2010-03-23 | 2011-02-09 | Ｊｘ日鉱日石金属株式会社 | 電子材料用銅合金及びその製造方法 |
| US8836128B1 (en) * | 2013-03-15 | 2014-09-16 | Microchip Technology Incorporated | Forming fence conductors in an integrated circuit |
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-
1998
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- 1999-07-22 ES ES99114392T patent/ES2313763T3/es not_active Expired - Lifetime
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Also Published As
| Publication number | Publication date |
|---|---|
| ATE408897T1 (de) | 2008-10-15 |
| DK0982766T3 (da) | 2008-11-17 |
| US6302765B1 (en) | 2001-10-16 |
| ES2313763T3 (es) | 2009-03-01 |
| FR2781922B1 (fr) | 2001-11-23 |
| TW431947B (en) | 2001-05-01 |
| FR2781922A1 (fr) | 2000-02-04 |
| JP2000114213A (ja) | 2000-04-21 |
| EP0982766A1 (en) | 2000-03-01 |
| KR100596644B1 (ko) | 2006-07-06 |
| EP0982766B1 (en) | 2008-09-17 |
| KR20000012088A (ko) | 2000-02-25 |
| MY118930A (en) | 2005-02-28 |
| DE69939569D1 (de) | 2008-10-30 |
| SG78371A1 (en) | 2001-02-20 |
| CN1244033A (zh) | 2000-02-09 |
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