CN1145200C - 半导体衬底及其制造方法 - Google Patents
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Abstract
一种制作半导体衬底的方法,通过除去半导体衬底的外周末端部分,以便使绝缘层的外周末端位于半导体层的外周末端与支承件的外周末端之间,从而该半导体层与绝缘层产生阶梯状外形,能有效地防止在绝缘层和半导体的部分中发生碎裂现象和产生碎片。
Description
本发明涉及一种半导体衬底,包括在一支承件上配置的半导体层,还涉及一种制造这种半导体衬底的方法。
众所周知,SOI(绝缘体上半导体)衬底,具有在绝缘层上边形成单晶半导体层而得到的SOI结构。包括SOI衬底的器件具有超过原来Si衬底的许多优点,包括下列各点:
(1)容易介质隔离且适合于提高集成度;
(2)优良的抗辐射能力;
(3)寄生电容小和有高速器件运行潜力;
(4)无需良好的形成过程;
(5)可靠的闩锁预防;以及
(6)减小薄膜厚度和形成全耗尽型场效应晶体管的能力。
由于SOI结构包括上述的优点,故近十年来,为发展各种制造具有SOI结构衬底的方法而付出了巨大努力。
SOI工艺可以回朔到借助于异质外延生长,用CVD(化学汽相生长)法,在单晶兰宝石衬底上生长Si层的SOS(兰宝石上硅)工艺时期。虽然SOS工艺可看做许多最成熟工艺之一,但是该工艺伴有许多缺点,包括因沿着Si层和下边兰宝石衬底的界面上晶格失配,存在铝从原来含铝的兰宝石衬底混入Si层中造成大量晶体缺陷,衬底的成本高和难以适应向较大衬底的发展趋势,所以不曾有过显著商业利用价值。
SIMOX(注入氧离子的隔离法)工艺,继SOS工艺之后。对该SIMOX工艺领域,也已作出各种研发努力,以减少晶体缺陷和降低制造费用。除SIMOX工艺外,迄今公知的方法包括:晶片键合法,就是键合一对晶片,其间有介入氧化膜,再抛光或蚀刻其中一个晶片,留下氧化膜上的薄单晶Si层;氢离子注入法,就是从其上带有氧化膜的Si衬底表面,将氢离子注入到预定深度,一般通过热处理,将该衬底与另一个衬底键合起来,然后使后者衬底与在氧化膜上留下的薄单晶Si层剥离。
就通过相互键合一对硅晶片而其间介有绝缘膜,并把一个衬底减薄到在绝缘膜上边产生薄膜或Si层来制造SOI半导体衬底的方法而言,通常因斜削衬底加工的有害影响,在周边区域可能会降低硅衬底键合的强度,甚至化为零。
其次,在这样状态下的SOI晶片,在键合强度不够的区域将可能碎裂,如果局部如此,则在制造半导体器件的过程中,晶片的表面可能会被碎片损伤,降低了高质量半导体器件的成品率。
为了克服之一难题,已经研究出了除去出现弱键合强度区的技术。例如,日本专利号2658135公开了一种防止在半导体衬底上发生碎裂现象的技术,包括在一支承件上边配置的半导体层,借助于电沉积金刚石表面的砂轮,用机械抛光该支承件的外周边缘。但是,高集成高密度的半导体器件需要进一步采取预防措施,以防止发生细碎片。
附图13A到13E,示意性地说明本发明的发明人提出的硅除去工艺过程。图13A示出一个通过键合和内蚀刻操作制成的SOI衬底5,包括在一个支承件1上形成的绝缘膜2和已减薄的硅层3。因为该部分键合强度弱,SOI衬底5上硅层3的外周末端部分必须被除去。在半导体工艺中为了除去硅层,应用光刻法是最普通的技术。就这样的技术来说,将光刻胶加到SOI衬底的表面上,对加上了的光刻胶进行曝光,因而仅仅除去可以除去硅层3部分上边的光刻胶。这样,就产生如图13B所示的光刻胶掩模。然后,如图13C所示,用留下来的光刻胶作为掩模,只除去出现弱键合强度的硅层3露出的末端部分。然后,除去位于硅层3下绝缘膜2的相应末端部分。一般采用用氢氟酸作为蚀刻剂的湿式蚀刻技术,因为它不会损伤底下的支承件1。由于湿式蚀刻工艺是各向同性地进行的,故位于硅层3下边其外周末端上部的绝缘膜2也被蚀刻而产生掏蚀,如图13D所示。在除去光刻胶后,就完成除去该硅的工艺过程(图13E)。
于是,除去呈现弱键合强度的硅层3周缘部分。
应注意的是,在通过键合和内蚀刻操作制成的上述说明的SOI衬底5中,由于沿其界面把支承件1和绝缘膜2键合一起,因此也必须除去直接位于该硅层的除去末端部分下的绝缘膜2部分。
但是,一旦除去了出现弱键合强度的硅层3末端部分,当位于硅层3下的相应绝缘膜2末端部分部被除去时,则留下来的硅层3可变成被侧向蚀刻而产生掏蚀,使得位于掏蚀的硅层外周末端部分会变成外伸式而完全没有键合。于是,硅层3的外伸式外周末端部分最终会发生碎裂现象并产生碎片。
这样,本发明的目的是提供一种从半导体层的外周末端不会造成碎裂现象,产生碎片的半导体衬底和制造这种半导体衬底的方法。
按照本发明的一个方面,上述的目的是这样达到的,通过提供一种半导体衬底,包括支承件;配置在该支承件上的绝缘层和配置在该绝缘层上的半导体层,其中:所述半导体层的外周末端位于所述支承件外周末端的内侧,和所述绝缘层的外周末端位于所述半导体层的外周末端与所述支承件的外周末端之间,使得包括所述绝缘层和所述半导体层的半导体衬底外周部分出现阶梯状的外形,其特征在于所述半导体层外周末端的底部与所述绝缘层外周末端的顶部之间的偏离不小于2微米,以及在于所述绝缘层在外周部分的上表面上边具有一台阶,且该外周部分的侧表面倾斜角不大于45°。
具有如上所述结构的半导体衬底,在制造工艺过程中若绝缘层横向地被蚀刻,其外周末端就难以产生外伸式外形,而必然很大程度上减少发生碎裂现象的可能性。
另外,由于将出现弱键合强度的半导体衬底部分除去,所以从衬底的边缘区域产生的碎片,将降到最小的程度。
图1A和1B是按照本发明的半导体衬底的一个实施例示意图。
图2A、2B、2C、2D、2E和2F是按照本发明的半导体衬底的另一个实施例示意图,示出了各个不同的制造步骤。
图3A、3B、3C、3D和3E是按照本发明的半导体衬底的再一个实施例示意图,示出了各个制造步骤。
图4A、4B、4C、4D、4E和4F是按照本发明的半导体衬底的再一个实施例示意图,示出了各个制造步骤。
图5A、5B、5C、5D、5E、5F和5FP是按照本发明的半导体衬底的另一个实施例示意图,示出了各个制造步骤。
图6A、6B、6C、6D、6E和6F是按照本发明的半导体衬底的另一个实施例示意图,示出了各个制造步骤。
图7A、7B和7C是按照本发明的半导体衬底的另一个实施例示意图,示出了各个制造步骤。
图8A和8B是可用于本发明目的边缘蚀刻器的示意图。
图9A和9B是按照本发明的半导体衬底的再一个实施例的示意局部剖面图。
图10A和10B是为比较起见而制造的半导体衬底的示意局部剖面图。
图11和12是按照本发明的半导体衬底的再一个实施例的示意局部剖面图。
图13A、13B、13C、13D和13E是一半导体衬底的示意剖面图,示出了公知半导体衬底制造方法的各个步骤。
(第一实施例)
图1A和1B是按照本发明半导体衬底的一个基本实施例的示意平面图和示意剖面图。
在这个实施例的SOI衬底5中,半导体层3的外周末端3A位于该支承件1的外周末端1A内侧,绝缘膜2的外周末端2A位于该半导体层3的外周末端3A与该支承件1的外周末端1A之间,以致实施例的包括半导体层3和绝缘膜2的外周末端部分10出现阶梯状外形。更准确地说,该半导体层3的外周末端底部和该绝缘膜2的外周末端顶部,相对于彼此偏离为水平距离d,因此,与图13E不同,半导体层3的外周末端没有出现外伸式的外形。换句话说,本实施例,在绝缘膜2的外周末端上边有宽度d的台阶。所以,半导体层3的外周末端难以发生碎裂现象和碎片。
对本发明来说,更可取的是支承件1由一种半导体材料,例如Si、Ge、GaAs或InP预制而成的衬底。尤其,更可取的是用Si晶片。
对本发明来说,更可取的是绝缘层由绝缘材料制成,例如氧化硅或氮化硅。
对本发明来说,更可取的是该半导体层,包括至少一层选自一组包括Si、Ge、SiGe、SiC、GaAs、GaAlAs、InP和GaN的半导体材料的材料层。
对本发明来说,水平偏离d,较好是不小于2微米,最好是不小于2微米且不大于1000微米。
对本发明来说,半导体层的厚度,较好是不小于10纳米且不大于10微米,最好是不小于10纳米且不大于2微米。
对本发明来说,绝缘层的厚度,较好是不小于10纳米且不大于10微米,最好是不小于10纳米且不大于2微米。
对本发明来说,工艺过程包括键合步骤,最好是在加工其外周末端部分之前,用于制造SOI衬底5。可以用于本发明的制造过程的具体例子,包括在日本专利号2608351和美国专利号5371037,日本专利申请公开号7-302889、日本专利公开号5-211128和美国专利号5374564。
特别是,在日本专利号2608351和美国专利号5371037中两者揭示的方法,及日本专利申请公开号7-302889中所揭示的一种方法,包括下列各个步骤:制造一第一构件,具有一多孔性的单晶半导体层和一非多孔性的单晶半导体层;把所述的第一构件与其间介以绝缘层的一第二构件键合起来,以便产生具有所述非多孔性的单晶半导体层位于内部的多层结构;及从所述的多层结构中将所述非多孔的单晶半导体层除去。所述的半导体层包括硅,而上述方法两种方法都可用于制造含有硅单晶的SOI衬底,其结晶性远远优于单晶晶片。
在日本专利公开号5-211128和美国专利号5374564中所揭示的方法包括下列各个步骤:在单晶硅晶片衬底的表面上形成氧化硅;从氧化硅层一侧把氢气离子或稀有气体离子注入到晶片中;在单晶硅晶片上形成微米级-泡层;在氧化硅层一侧把该晶片键合到作为支承件的另一个衬底上边,而后沿微米级-泡层将已键合的衬底分开,产生SOI衬底。于是,如上所述,这种SOI衬底可参照本发明的第一实施例,来制造半导体衬底。
当将诸如Si晶片之类的半导体晶片借助于键合技术用作制造SOI衬底的原材料时,应该注意的是,在晶片外周末端的顶部和底部,晶片都被斜削成斜面。因此,在按照本发明受到加工处理其外周末端之前,在SOI衬底中半导体层(或绝缘层)的外周末端和支承件的外周末端可能有微小范围偏离。
其次,对包括所述绝缘层和所述半导体层的半导体衬底的外周末端部分进行加工而出现阶梯状外形,如图1A和1B所示。
可用于加工处理的较好技术,包括利用蚀刻掩模的湿式或干式蚀刻法和抛光法,例如化学机械抛光法(CMP)。
可将半导体层的外周末端和绝缘层的外周末端两者都加工成出现锥形或倾斜的外形,以这样的方式即其顶面与侧面相互以大于直角的角相交,如下面将要更详细说明的一样。
倘若将半导体衬底蚀刻出阶梯状的外形,则蚀刻过程可以是湿式蚀刻过程或干式蚀刻过程。为了蚀刻硅层,例如,采用湿式蚀刻技术时,可用氢氟酸和硝酸TMAH(三甲基氢氧化铵)作为蚀刻剂,而采用干式蚀刻技术时,可用氯气、CF4或SF6作为蚀刻剂。同样,至于蚀刻氧化硅膜(绝缘膜2),在干式蚀刻过程中通常可使用氢氟酸溶液或缓冲氢氟酸溶液,而在干式蚀刻过程中,可用CH3。蚀刻的方式可以是各向同性或各向异性的。
各向同性的蚀刻过程,更可取的是使用边缘蚀刻器和边缘抛光器,对半导体层和绝缘层进行加工,就本发明来说,使之出现锥状的外形。
通过以各种不同的方法修改上述的第一实施例,还可以实现下列的各个实施例。
(第二实施例)
下面的制造各个步骤可以很好地用于第二实施例。首先,借助于键合技术,制造SOI衬底5,如图2A所示。该SOI衬底5包括一支承件1,它是一个单晶硅衬底;一在该支承件1上形成的绝缘膜2,一般通过干式氧化技术,只用O2气、或湿式氧化技术,用水蒸气;以及借助于CVD(化学气相淀积)法在该绝缘膜2上外延生长一半导体(硅)层3。然后,为了除去在该绝缘膜2上边位于其外周末端并且出现弱键合强度的半导体层3部分,在该硅层3上边形成蚀刻掩模光刻胶4(图2B)。然后,用光刻胶4作为掩模(图2C),蚀刻硅层3,除去其外周末端。除去光刻胶4后,为了蚀刻该绝缘膜2重新加上光刻胶图形6并经过制成图形的操作(图2D)。为了实现绝缘膜2相对于底下支承件1的选择性蚀刻,用氢氟酸作为蚀刻剂,通过湿式蚀刻法蚀刻该绝缘膜2。虽然湿式蚀刻法不可避免地伴有侧面蚀刻,但这个问题可以通过选择掩模尺寸来回避,即使被掏蚀,也不至于蚀刻位于半导体层3底下的绝缘膜2部分。最后,通过除去光刻胶6,将获得具有如图2F所示剖面图的SOI衬底。应注意的是,光刻胶4和光刻胶6都可以是普通的正型胶或普通的负型胶。普通正型光刻胶的例子是酚醛树脂,可用旋涂法把它加上。在把加上光刻胶制成图形的地方,掩模将粘附于半导体层3上,只要使蚀刻掩模在适当位置上安放就行。
用于本实施例的制造SOI衬底5的方法,不限于上述说过方法,也可以用一些别的适当方法来代替。
(第三实施例)
图3A到3E示意说明制造按照本发明的SOI衬底的第三实施例,而示出了各个制造步骤。首先,SOI衬底5包括制造在支承件1上边配置的一层绝缘膜2和一硅层3(图3A)。把光刻胶4施加到SOI衬底5上边,经过制成图形的操作,使之出现所要求的图形(图3B)。然后,连续地蚀刻去掉硅层3末端部分以及绝缘膜2的末端部分(图3C)。结果,连续地除去未被光刻胶4盖住的,在该支承件1上边的硅层3部分和绝缘膜2部分。然后,除去光刻胶4后,形成另一层光刻胶图形6。必须小心进行,以保证这一树脂图形的外周末端,位于第一树脂图形外周末端的内侧。要注意的是,第一光刻胶4不必除去但可以缩小,使其边界线位于原来边界线的内侧,而加上光刻胶6重新产生同样的效果(图3D)。
然后,只蚀刻去掉硅层3的末端部分,使硅层3的外周末端从绝缘膜2的外周末端偏离开来(图3E)。
当将光刻胶用在上述制造方法中时,可产生按照本发明的半导体衬底而不用光刻工艺,并可以通过胶带掩蔽硅衬底进行蚀刻操作。另一方面,可借助于适合于只蚀刻物件边缘的边缘蚀刻器,逐步蚀刻硅衬底的周边区域。再一方面,借助于边缘抛光器,可在外周末端部分产生如图2F所示的外形。
(第四实施例)
图4A到4F示意说明制造按照本发明的SOI衬底的第四实施例,而示出了各个制造步骤。首先,如图4A所示,SOI衬底5包括制造在一支承件1上边配置的一层2μm厚绝缘层2和一层2μm厚硅层3,而后,如图4B所示,把第一光刻胶4施加到SOI衬底5上边,经过制成图形的操作,使之出现所要求的图形(图3B)。当具有与晶片外形相同的光掩模用于曝光和制作图形操作时,采用适合于只使边缘部分曝光的晶片边缘曝光系统,给位于沿支承件外周末端的环形区域曝光,在本实施例中用于除去露出宽度L1。
然后,如图4C所示,连续蚀刻SOI衬底5的硅层3末端部分和绝缘膜2的末端部分。在除去光刻胶4后,施加第二光刻胶6并且借助于晶片边缘曝光系统,只使宽度L2的光刻胶6周边部分被曝光,产生光刻胶图形如图4D所示。这样一来,第二光刻胶6的外周末端就位于该第一光刻胶4的外周末端内侧,距离为(L2-L1)。
鉴于通常的边缘曝光系统的曝光宽度精度约为±0.1mm,更可取的是L1和L2分别可以约为1.8mm和2.0mm。应注意的是,通过使用改进了的精密曝光系统用于制作图形的操作,可以进一步缩小第一光刻胶4与第二光刻胶6的外周末端之间的差距。
然而,如果将各向同性蚀刻技术用于蚀刻图4E的绝缘膜,则当绝缘膜有大约45°锥角的锥状外形时,侧蚀现象可以显示为等于绝缘膜2的薄膜厚度(2μm)的范围。因而,当使宽度小于可能的绝缘膜2(2μm)的侧蚀范围时,在底部处就可能掏蚀该硅层3。
所以,为了使本实施例可行,第一光刻胶4的宽度与第二光刻胶6的宽度之间的距离(L2-L1),需要大于绝缘膜2侧蚀的范围。但对宽度没有上限,当宽度过大时,由此硅有源层可以产生的器件个数减少,因此该宽度应该大于5微米,并与曝光系统的精度有关,且采用晶片边缘曝光系统时,该宽度最好在100微米到500微米之间。
其次,如图4E所示,蚀刻去掉硅层3的外周末端部分并且除去光刻胶6,完成除去SOI衬底的外周末端部分的操作,而产生如图4F所示的外形,其中f约为2.0mm,e约为1.8mm以及d约为198μm。
就本实施例来说,确实能够防止在SOI衬底5的硅层3和绝缘膜2中出现任何碎裂现象。
(第五实施例)
在本实施例中,将绝缘膜侧面的倾斜角作成为小于半导体层侧面的倾斜角。
图5A到5F示意说明制造按照本发明的SOI衬底的第五实施例,而示出了各个制造步骤。首先,如图5A所示,SOI衬底5包括借助于键合技术,在支承硅衬底1上边配置作为绝缘膜的氧化硅膜2具有厚度T2为2μm厚,和一硅层3具有厚度T3为2μm,而后,如图5B所示,将第一光刻胶6施加到SOI衬底5上边并且经过制作图形的操作,使之出现要求的图形。
在本实施例中,此制作图形的操作是利用具有半径比晶片小L2(=2.0mm)而形状相同的光掩模来进行,以便只使沿晶片边缘宽度为L2的区域被曝光。
其次,如图5C所示,仅蚀刻去掉硅层3的末端部分。如果采用湿式蚀刻技术,则碱性TMAH(三甲基铵-氢氧化物)蚀刻溶液或氢氟酸与硝酸的混合溶液将适合于蚀刻操作。另一方面,如果采用干式蚀刻技术,则通常要用CF4和SF6气体的RIE(反应离子刻蚀)或CDE(化学干式蚀刻法)系统。虽然各向同性蚀刻发生在湿式蚀刻系统中,也应为干式蚀刻选择适合各向同性蚀刻的条件。例如,在平行板反应离子刻蚀系统中,用SF6气体和O2气,以高压放电气压50Pa,来适当减小离子的平均自由径,因而降低离子蚀刻的速度,就可以实现各向同性原子团蚀刻。
蚀刻操作完全各向同性地继续进行下去,使得硅层3的侧面具有侧面与顶面之间为钝角的锥形,而角AG3基本上等于45°(听5CP)。同时,可以在蚀刻底下氧化硅膜2的速率与蚀刻硅层3速率之间,得到足够大的蚀刻选择性,因此必然只蚀刻硅层3,以致出现锥形的外形。
在除去光刻胶6后,将第二光刻胶4施加到晶片上边,利用具有形状与第一掩模相同而大于后者8微米的光掩模,只对沿着晶片边缘宽度为L1的区域进行曝光,产生制成图形的光刻胶4,如图5D所示。如果L1是1.992mm,则光刻胶4抗蚀剂图形,具有与第一光刻胶6外侧延伸线对准的外周末端,且与后者隔开8微米。
其次,如图5E所示,仅蚀刻去掉SOI衬底5氧化硅膜2的外周末端部分。如果采用湿式蚀刻技术,则蚀刻溶液,例如缓冲氢氟酸(BHF)溶液将适用于蚀刻操作。另一方面,如果采用干式蚀刻技术,则通常要用CF4、CHF3或H2气体的RIE(反应离子刻蚀)或CDE(化学干式蚀刻法)系统。当要在干式蚀刻系统中引起各向同性蚀刻时候,也应为干式蚀刻选择适合各向同性蚀刻的条件。例如,可以通过用缓冲氢氟酸(BHF)溶液的湿式蚀刻来实现各向同性蚀刻操作,直至氧化硅膜2被稍稍过蚀刻并且角度AG2保持基本上等于30°。同时,可以在蚀刻底下氧化硅膜2的速率与蚀刻硅层3的速率之间,得到足够大的蚀刻选择性,因此必然只蚀刻氧化硅膜2,以致出现具有角度AG2为30°的锥形的外形,如图5E所示(又见图5FP)。
当蚀刻氧化硅膜2,使之在外周末端部分出现锥形的外形,具有角度AG2等于30°时,则2.8μm的侧蚀发生于膜厚为2μm的绝缘氧化硅膜2上。这样一来,当宽度作成为小于绝缘膜2的可能侧蚀范围时,则可能在底部掏蚀该硅层3。
因此,为了使本实施例可行,第一光刻胶4的宽度与第二光刻胶6的宽度之间的距离(L2-L1),需要大于绝缘膜2侧蚀的范围。虽然对宽度没有上限,但当宽度过大时,由此硅有源层能产生的器件个数将减少,因此该宽度应该大于5微米,且与曝光系统的精度有关,采用晶片边缘曝光系统时,该宽度最好在100微米到500微米之间。
最后,除去光刻胶4,产生锥形台阶状外形,如图5F所示,具有30°的角AG2和5.2μm的台阶宽度。就轻度锥形台阶状外形来说,在连续的清洗和蚀刻过程中,该晶片将不会因为侧蚀而出现任何掏蚀。尤其是,当碎裂现象出现于硅层3和/或没有满意地排除清洗的水时,任何掏蚀都可能导致产生颗粒。如果预料到氧化硅膜变成为侧蚀的受害者,则可以制备第一光刻胶6的厚度与第二光刻胶4的厚度之间的差别大一些来防止侧蚀现象,使得掏蚀不会发生在该氧化硅膜上。其次,从它的绝缘膜将末端部分除去宽度e(=L1),就产生半导体衬底。
(第六实施例)
图6A到6F示意说明制造按照本发明的SOI衬底的第五实施例,示出了各个制造步骤。首先,如图6A所示,一个8英寸(直径200mm)的SOI衬底5包括借助于键合技术,在支承硅衬底1上边配置的一层200nm厚的氧化硅膜2作为绝缘膜和一层200nm厚的硅层3。
其次,如图6B所示,将第一掩模带14施加到该SOI衬底5上边,而掩模带的中心与晶片的中心对准。适用于本实施例的掩模带14可具有直径例如196.8mm。其次,如图6C所示,连续蚀刻去掉硅层3的末端部分和绝缘膜2的末端部分。通过控制蚀刻操作的持续时间,使绝缘膜2的横侧面和硅层3的横侧面出现倾斜的锐角。
其次,在借助于胶带剥离机剥离掩模带14后,把具有直径例如196.0mm的另一掩模带16施加到具有已与晶片中心对准的掩模带中心的晶片上,如图6D所示。于是,第二掩模带16被配置在第一掩模带14的内侧,并且在其外边界上的任何一点处横距都为0.4mm。之所以选用这个值,是鉴于预期要用的胶带覆贴机的对准精度。对于本实施例,这个值约为±0.2mm。如果采用较好精度的胶带覆贴机,则可以进一步缩小自第一掩模带14露出区域的宽度与自第二掩模带16露出区域的宽度之间的差距(L2-L1)。虽然对宽度(L2、L1)没有上限,但宽度过大时,由硅有源层能产生的器件个数将减少,因此该宽度应该在10微米与1微米之间,且与胶带覆贴机的精度有关,在实际使用中最好在100微米到500微米之间。
其次,如图6E所示,仅蚀刻去硅层3的外周末端部分,并借助于胶带剥离机剥离掩模带16,产生阶梯状外形,就SOI衬底的外周末端部分来说,如图6F所示。
虽然台阶的高度不能象使用光刻胶那样减小到几个微米的水平,因为掩模带14和16精度相对较差,但是掩模带的费用,低到大约用光刻胶的费用包括显影液的费用的一半,故在蚀刻技术之上使用掩模带的技术具有显著的实际优点,尤其是,鉴于胶带覆贴机和胶带剥离机价格,比光刻胶涂覆器和曝光系统要便宜这个事实。
(第七实施例)
图7A到7C示意说明制造按照本发明的SOI衬底的第五实施例,示出了各个制造步骤。首先,如图7A所示,一个8英寸(直径200mm)的SOI衬底5包括借助于键合技术,在支承硅衬底1上边配置的一层200nm厚的氧化硅膜2作为绝缘膜和一层200nm厚的硅层3。
其次,借助于旋转式薄边缘蚀刻器来蚀刻SOI衬底5的硅层3,该边缘蚀刻器适合于通过薄座在薄片上蚀刻晶片,而具有构造形式如图8A所示。这样的边缘蚀刻器,在日本专利公开号7-15897中已做说明,它包括一辊盘7,以便随着以蚀刻液浸渍的辊盘7施压于晶片而来蚀刻晶片。在蚀刻操作的时候,为了防止蚀刻液的蒸气流向晶片表面,所以通过安排在衬底上边的环形喷嘴(未示出)吹出氮气,使得边缘蚀刻器不需使用蚀刻掩模。
用于蚀刻硅层3的辊盘7的深度DP3约为1.8mm,通过适当选择在其下边辊盘7压向晶片的压力,就可以控制蚀刻深度。其次,该硅层3将被蚀刻成从晶片边缘为1.8到2.0mm,出现轻微锥度的外形。同时,采用碱性TMAH(三甲基氢氧化铵)蚀刻剂,可以在蚀刻硅层3的速率与蚀刻氧化硅膜2之间,得到足够大的蚀刻选择性,因此必然地只蚀刻硅层3。也可以用适当的氢氟酸与硝酸的配比,选择所需的蚀刻选择性。这样,该硅层就加工成如图7A说明的外形。
其次,在以纯净水替换蚀刻液后,借助于如图8B所示的设备,蚀刻氧化硅膜2的外周末端部分。被用于蚀刻氧化硅膜2的辊盘8具有约1.4mm的深度DP2,通过适当选择在其下边辊盘8压向晶片的压力,就可以控制蚀刻深度。其次,蚀刻氧化硅膜2的外周末端并自支承件的相应外周末端起切进距离为e=1.4mm到1.6mm,出现一种轻微锥度的外形。同时,通过用含有氢氟酸或缓冲氢氟酸的蚀刻液,可以在蚀刻硅层的速率与蚀刻氧化硅膜2之间得到足够大的蚀刻选择性,因此必然地只蚀刻硅层3。于是,最终产生出现阶梯状的和轻微锥度外形的外周末端部分,如图7C所示。
被用于本实施例的边缘蚀刻器,包括用于第一次和第二次蚀刻操作的辊盘,分别具有1.4mm和1.8mm的深度DP3和DP2,其差数为0.4mm。通过选择适当参数可以减少这个差数或露出区域的宽度(f-e),因为由蚀刻操作获得的锥形外形,可以随作用类型和蚀刻液的成分,在其下辊盘压向晶片的压力以及其它因素而改变。虽然对宽度(f-e)没有上限,但当宽度(f-e)过大时,由硅有源层可以产生的器件个数将减少,因此使用通常的边缘蚀刻器时,该宽度(f-e)应该在10微米与1微米之间,并且更可取的是,当使蚀刻条件优化时,该宽度可在100微米到500微米之间。最后,以纯净水来替换蚀刻液,产生具有轻微锥度和阶梯状外形的外周末端部分。
虽然由于轻微锥度外形可能含显著增大除去部分的宽度,但就费用来说,使用边缘蚀刻器是有益的,因为它既不用光刻胶也不用胶带。
虽然已说明了有关本实施例中使用的边缘蚀刻器,但也可以用旋转式边缘抛光器来替代。可用于本发明目的的边缘抛光器,就是具有转盘的旋转式,适于供以抛光剂并且只要改变转盘与衬底之间的角度就能有效地抛光衬底。通过控制在其下面把该转盘压向衬底的压力,就可以控制抛光产品的外形。虽然抛光操作很费时间,但若SOI衬底厚度较大,而且要大宽度除去该SOI衬底的外周末端部分产生轻微锥度的外形,就费用来说,使用边缘抛光器是有利的,因为它既不用光刻胶也不用胶带。
另外,可以将使用胶带和使用边缘蚀刻器(或边缘抛光器)这样的组合起来,将胶带用于第一(第二)次蚀刻操作,而边缘蚀刻器(或抛光器)用于第二(第一,随便哪个适合)次蚀刻操作。更一般地说,就本发明而言,根据从SOI衬底上除去区域的宽度、锥形的外形和加工费用的观点出发,可以将使用光刻胶、用胶带、用边缘蚀刻器以及用抛光器适当地结合起来。
(第八实施例)
图9A是按照本发明的半导体衬底的第八实施例外周末端部分的示意说明图,而图9B是同一实施例的外周末端部分(S12)的示意说明图,正是在其横侧面已被蚀刻后所看到的样子。另一方面,图10A是为比较起见而制成的半导体衬底外周末端部分的示意图,而图10B是同一半导体衬底外周末端部分的示意说明图,正是在其横侧面已被蚀刻后所看到的样子。
在图10A的情况下,当半导体衬底经受清洗步骤,例如一种用含有氢氟酸的清洗液和具有侧蚀作用的RCA清洗操作时,就会在半导体层3(在绝缘层2的外周末端顶上)的外周末端下面产生掏蚀UC,如图10B所示。
相反,在第八实施例的情况下,其中半导体层3和绝缘层2在其外周末端部分处产生阶梯状外形,而且绝缘层2具有一个台阶,如图9A所示,如果稍稍发生侧蚀现象,在绝缘层2的外周末端顶部与半导体层3之间就没有产生偏移,因为绝缘层2的外周末端顶部偏离半导体层3不小于2微米(水平方向)。这样,在图9A的结构中就没有出现掏蚀。
另一方面,当半导体层3的外周末端部分侧向表面和绝缘层2的外周末端部分侧向表面彼此在同一条线上而且象图10A结构的情况一样彼此没有偏离时,则侧蚀现象从绝缘层2外周末端的顶部出发产生掏蚀,如图10B所示。
虽然在半导体层3外周末端的底部与绝缘层2外周末端的顶部之间的距离,或偏离d,在上面的说明中在图9A的结构上,不小于2微米,尤其是当在含有施加于绝缘层2的侧蚀作用的工艺过程中侧蚀程度明显时,则可以把这个限制作为侧蚀程度的函数来确定。同时可以把偏离d的下限作为侧蚀程度的函数来确定,把偏离d的上限作为对半导体层有效利用程度的函数,和依赖于晶片大小、半导体芯片的所需的大小和数量以及其它因素来确定。
由产生半导体衬底的原清洗和处理步骤来看,偏离d一般不小于2微米而不大于1mm,较好的是不小于5微米而不大于1mm,最好不小于100微米而不大于500微米。
(第九实施例)
图11是按照本发明的半导体衬底的第九实施例的示意说明图。本实施例由修改图9A的结构而获得,在半导体层3的侧面和支承件1周缘部分的底面、侧面以及顶面上边,分别形成绝缘膜24、21、22和23。
在本实施例中,还使半导体层3外周末端部分的底部与绝缘层2外周末端部分的顶部偏离d,该偏离d不小于2微米,沿半导体衬底外周末端出现阶梯状外形,以致更加难以产生任何掏蚀。
也可以或通过氧化的图9A结构以掩蔽半导体层3的顶面,或通过氧化图9A结构的整个表面,并接着除去半导体层顶面的氧化膜而得到这样的一种结构。
(第十实施例)
图12是按照本发明的半导体衬底的第十实施例的示意剖面图,只示出了其外周末端部分。支承件1的外周末端,在其顶面和和底面都是斜面。半导体层3外周末端的底部和绝缘层2外周末端的顶部偏离为大于2μm,以便在绝缘层2的顶面上边产生一个台阶。
另外,绝缘层2外周末端的底部与支承件1的外周末端,偏离为大于1mm。
虽然图12结构中的半导体层3具有大于绝缘层2的厚度,但是前者的厚度也可以换过来作成小于后者的厚度。另外,层2和3的侧面可以是锥形的和/或支承件的外周末端部分的侧面和底面可覆盖以绝缘膜(21、22),如图11所示。应注意的是,按照本发明的半导体衬底支承件1有数百微米的厚度,远远大于层2和3的厚度。
如上述的那样,参照优选的实施例,应将半导体层和绝缘层两者部分区域除去,在该区域具有弱键合强度,尤其在SOI衬底的外周末端部分,以便沿着半导体层和绝缘层的外周末端产生阶梯状的外形,它能够有效地防止任何碎裂现象出现,因而可在稳定的基底上边制造出高质量SOI衬底。
另外,半导体层的侧面和绝缘层的侧面可以是倾斜的,以防止碎裂现象出现和产生碎片,因此能以高成品率制造出高质量的半导体器件来。
此外,可将SIMOX晶片用作本发明目的SOI衬底。
(实例)
制备一个8英寸Si晶片作为原片,用阳极氧化法从其表面到深度约10μm处,把该表面制成多孔性的。形成的多孔层在400℃下进行热氧化,然后浸入稀氢氟酸溶液中,从多孔层的顶部表面除去氧化膜。接着,在氢气气氛中对试片进行预焙,而后用CVD法在多孔层上,进行外延生长非多孔Si层,厚度为120nm。
然后将外延生长获得的Si层表面进行氧化,产生约40nm厚度的氧化膜,并把单独制成的8英寸晶片作为保持片接合到原片上,是在该组件经受热处理过程之前。
其次,借助于RIE法从背面抛光该原片,而后,借助于含有氢氟酸、过氧化氢和乙醇的蚀刻液,有选择地除去多孔层。其次,在氢气气氛中热处理该试片,并使曾转到保持片上的非多孔Si层的表面平滑化,形成SOI衬底。
接着,参照图7A到7C,试片受到如上述那样的各个加工步骤,产生具有如图7C所示结构的半导体衬底。
制备相同的半导体衬底试片并反复清洗。在每次清洗操作之后,测量粘附于每个半导体衬底试片上的颗粒数。
结果,发现直径超过0.15μm的颗粒数在0.02/cm2和0.1/cm2之间,就全部试片来说,没有显著变化。
(比较例)
如同上述实例制备了多个SOI衬底。接着,参照图13A到13E,使之受到如上述那样的各个加工步骤。其次,反复清洗所得到的半导体衬底,并象上述实例的情况一样,观察了粘附于每个试片上的颗粒数。
结果,发现直径超过0.15μm的颗粒数在0.05/cm2和4/cm2之间,并且每次测量后都显著变化。颗粒数中每次的增加,以直径在0.05μm和0.4μm之间居多。
Claims (3)
1、一种半导体衬底,包括支承件;配置在该支承件上的绝缘层和配置在该绝缘层上的半导体层,其中:
所述半导体层的外周末端位于所述支承件外周末端的内侧,和所述绝缘层的外周末端位于所述半导体层的外周末端与所述支承件的外周末端之间,使得包括所述绝缘层和所述半导体层的半导体衬底外周部分出现阶梯状的外形,其特征在于
所述半导体层外周末端的底部与所述绝缘层外周末端的顶部之间的偏离不小于2微米,以及在于
所述绝缘层在外周部分的上表面上边具有一台阶,且该外周部分的侧表面倾斜角不大于45°。
2、按照权利要求1所述的半导体衬底,其中所述半导体层外周部分的侧向表面是倾斜的。
3、按照权利要求2所述的半导体衬底,其中所述绝缘层的侧向表面和所述绝缘层的上表面之间的倾斜角小于所述半导体层的侧向表面和所述半导体层的上表面之间的倾斜角。
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JP3250721B2 (ja) | 1995-12-12 | 2002-01-28 | キヤノン株式会社 | Soi基板の製造方法 |
WO1997027621A1 (en) | 1996-01-26 | 1997-07-31 | Sibond, L.L.C. | Selective-etch edge trimming process for manufacturing semiconductor-on-insulator wafers |
US6090688A (en) * | 1996-11-15 | 2000-07-18 | Komatsu Electronic Metals Co., Ltd. | Method for fabricating an SOI substrate |
JP3352896B2 (ja) * | 1997-01-17 | 2002-12-03 | 信越半導体株式会社 | 貼り合わせ基板の作製方法 |
-
1999
- 1999-01-28 DE DE69917819T patent/DE69917819T2/de not_active Expired - Lifetime
- 1999-01-28 AT AT99300620T patent/ATE268943T1/de not_active IP Right Cessation
- 1999-01-28 US US09/238,571 patent/US6417108B1/en not_active Expired - Lifetime
- 1999-01-28 EP EP99300620A patent/EP0935280B1/en not_active Expired - Lifetime
- 1999-01-28 SG SG1999000225A patent/SG78332A1/en unknown
- 1999-01-29 TW TW088101399A patent/TW454244B/zh not_active IP Right Cessation
- 1999-02-04 KR KR1019990003829A patent/KR100360979B1/ko not_active IP Right Cessation
- 1999-02-04 CN CNB991017587A patent/CN1145200C/zh not_active Expired - Fee Related
-
2002
- 2002-05-13 US US10/143,015 patent/US7245002B2/en not_active Expired - Fee Related
-
2007
- 2007-01-22 US US11/625,497 patent/US20070114609A1/en not_active Abandoned
Also Published As
Publication number | Publication date |
---|---|
CN1225499A (zh) | 1999-08-11 |
SG78332A1 (en) | 2001-02-20 |
US20020132451A1 (en) | 2002-09-19 |
KR19990072429A (ko) | 1999-09-27 |
DE69917819D1 (de) | 2004-07-15 |
ATE268943T1 (de) | 2004-06-15 |
US6417108B1 (en) | 2002-07-09 |
EP0935280A1 (en) | 1999-08-11 |
EP0935280B1 (en) | 2004-06-09 |
DE69917819T2 (de) | 2005-06-23 |
KR100360979B1 (ko) | 2002-11-18 |
TW454244B (en) | 2001-09-11 |
US20070114609A1 (en) | 2007-05-24 |
US7245002B2 (en) | 2007-07-17 |
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