CN1150613C - 用于引线连接式芯片的有机芯片载体 - Google Patents

用于引线连接式芯片的有机芯片载体 Download PDF

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CN1150613C
CN1150613C CNB98107457XA CN98107457A CN1150613C CN 1150613 C CN1150613 C CN 1150613C CN B98107457X A CNB98107457X A CN B98107457XA CN 98107457 A CN98107457 A CN 98107457A CN 1150613 C CN1150613 C CN 1150613C
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A·C·巴特
S·D·迪赛
J·A·莱特
���ŷ�
T·P·杜菲
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Abstract

一种引线连接式芯片的芯片载体，采用有机介电材料而不是常规陶瓷材料，还至少采用一个有机的可光学成像的介电层，带有镀层光学通路以使扇出电路的多层电互连。并且还采用单层坑来容纳芯片而不用常规多层坑。而且还含有直接位于芯片下方的热通路孔和金属层以增强热耗散。

Description

用于引线连接式芯片的有机芯片载体
本发明的专利申请是专利申请号为96102102.0、申请日是1996年2月2日、发明名称是“用于引线连接式芯片的有机芯片载体”的母案申请的分案申请，母案的在先申请号是US390344，在先申请日是1995年2月15日。
技术领域
本发明一般涉及到用于引线连接式芯片的有机芯片载体。
背景技术
半导体集成电路器件(以下称之为半导体芯片或芯片)的电学封装方法通常是将一个或几个芯片安装在陶瓷(例如氧化铝)芯片载体衬底上，并采取引线连接的方法将各芯片上的I/O(输入/输出端)接触焊点电连接到陶瓷芯片载体衬底上相应的接触焊点上(因而也是相应的扇出电路)。然后将得到的陶瓷芯片载体安装在印刷电路板(PCB)上或印刷电路卡片(PCC)上，并从而(经由PCB或PCC上的电路)电连接到安装在PCB或PCC上的其它陶瓷芯片载体和其它电子元件上。
虽然上述的封装方法肯定是有用的、但采用陶瓷芯片载体衬底确实牵涉到一些限制和缺点。例如，正如人们已知的，电信号通过介电层上或二个介电层之间的引线的传播速度正比于介电层介电常数平方根的倒数。不幸的是，陶瓷的介电常数相当大，例如氧化铝的介电常数约为9，这就使陶瓷芯片载体的信号传播速度相当低，有时低得不合要求。
采用陶瓷芯片载体衬底还引起某些I/O限制。例如，单层陶瓷芯片载体衬底在陶瓷单层的上表面上只包含一层延伸至陶瓷单层外围附近接触焊点的扇出电路。(通常用带有连接于这些外围接触焊点的内引线的引线框来实现这种陶瓷芯片载体到PCB或PCC的电连接。)然而，当芯片I/O数目增加时，就必须增加扇出引线的数目，而且必须相应地减小各扇出引线之间的间隔，直至相邻扇出引线之间不希望有的串扰变成不可接受。而且，在陶瓷层外围附近要制作相应的大量接触焊点即使不是不可能，也变得越来越困难。这样，单层陶瓷芯片载体衬底在其处置具有大量I/O的芯片的能力方面肯定要受到限制。
为适应具有相当大量I/O数目的芯片而作的努力导致了采用多层陶瓷芯片载体衬底，它采用所谓的球栅阵列(BGA)来代替引线框。这种陶瓷芯片载体衬底与单层陶瓷芯片载体衬底之间的差别在于，它们在二个或多个陶瓷层上含有二个或多个扇出电路层。重要的是，扇出电路的各层间的电互连是用机械钻制的通道孔(镀有和/或填充有导电材料)来实现的。此外，一定数目的这种孔从扇出电路层延伸到芯片载体衬底上装设有焊球(呈栅阵列状，故称球栅阵列)的底部。这些焊球要按机械方式和导电连接到PCB或PCC上各相应的可焊接的接触焊点。遗憾的是，使扇出电路各层导电互连的机械钻制的孔的直径相当大，要求扇出引线之间的间隔相当大。但这一相当大的扇出引线之间的间隔限制了这种多层陶瓷衬底芯片载体衬底所能容纳的芯片I/O的数目。
为封装具有相当大数目芯片I/O的芯片所作的其它努力导致采用多层陶瓷衬底中的多层坑。(此处所谓的“坑”表示衬底中的一个凹陷处而不是贯穿衬底厚度的孔)。当采用这种封装结构时，芯片面朝上地安装在多层坑的底部。引线从芯片上表面的I/O接触焊点延伸到构成多层坑的不同层的多层陶瓷衬底的不同层的各个暴露的上表面上的接触焊点。尽管这种结构确实能够容纳相当大量的芯片I/O，它也确实使从芯片延伸到多层坑上层的引线相当长。结果，相应电信号的“飞行时间”就不希望有地增加了。
陶瓷芯片载体衬底就其热耗散能力来说也受到限制。例如，在带有位于多层坑底部的芯片的多层陶瓷芯片载体的情况下，通常是用直接于坑的下方提供热沉(heat sink)的方法来获得热耗散。但这意味着芯片产生的热在到达热沉之前必须传递坑底部的陶瓷层。结果，热耗散速率受到限制。
于是，开发芯片载体的人们就希望有一种芯片载体能够：(1)具有相当高的电信号传播速度；(2)能容纳相当大量I/O的芯片同时又无需机械钻制的孔来互连扇出电路的不同层；(3)具有相当短的“飞行时间”；以及(4)具有相当高的热耗散速率。但迄今未能成功。
发明内容
本发明涉及到一种芯片载体，它：(1)具有相当高的电信号传播速度；(2)能容纳相当大量I/O的芯片同时又无需机械钻制的孔来互连扇出电路的不同层；(3)免去了采用相当长的引线，从而获得了相当短的“飞行时间”；以及(4)获得了相当高的热耗散速率。
重要的是，本发明的芯片载体采用了诸如以FR4和DriClad商标出售的环氧/玻璃配方的有机介电材料来代替陶瓷介电材料。这些有机材料的介电常数相当低，例如FR4的介电常数为4.0。结果，本发明的芯片载体就具有相当高的电信号传播速度。
本发明的芯片载体还采用一个用作薄膜再分布层(FRL)的有机可光学成像的介电层。亦即，此特殊的有机介电层对光很灵敏，并且正如光抗蚀剂那样可用掩模方便地选择性曝光及显影，以便在可光学成像介电层中形成通道孔(此处称之为光学通道以区别于机械钻制的通道孔)。重要的是，这些光学通道可容易地做成直径远远小于常规机械钻孔技术所形成的通道的直径。例如，常规钻制通道孔的直径通常不小于约12密尔(0.012英寸)，而光学通道的直径可小于例如2密尔(0.002英寸)。结果，当这种可光学成像介电层结合到本发明的芯片载体中的时候，就可以使扇出电路的二个(或更多个)层互连而不必将扇出引线之间的间隔限制到采用机械钻制孔那样的程度。结果，本发明的芯片载体就可容纳具有比常规陶瓷芯片载体所能容纳的更多的I/O数目的芯片。
本发明的芯片载体还采用一个单层坑(single-tiered cavity)来容纳一个芯片而不是采用多层坑。结果就避免了相当长的引线连接。因此，本发明的芯片载体可得到相当短的相应电信号的“飞行时间”。
在本发明的一个实施例中，热通道孔提供在单层坑之下方，延伸至芯片载体的底部，以便将芯片产生的热排出到大气中。在另一实施例中，将热沉直接提供在热通道孔下方以进一步增强热耗散。在又一个实施例中，芯片载体包含一个用作热沉的金属(例如铜)层，而且单层坑的深度延伸到甚至进入金属层。这就在坑中的芯片与热沉之间导致直接的物理接触，引起更大的热耗散。
在另一实施例中，本发明的芯片载体至少包括二个有机层，其间夹有一个接地平面。同这一实施例相关的单层坑的深度至少延伸至接地平面。重要的是，本实施例还包含一个几乎连续的金属环围绕着坑的侧壁并按垂直方向延伸至芯片载体的上表面。由于此金属环使得有可能容易与接地平面导电接触同时又无需延伸至接地平面的机械钻制的通道孔，故此金属环的存在是有利的。结果就可有利地减小扇出引线之间的间隔。
附图说明
参照附图来描述本发明，在这些附图中：
图1是本发明芯片载体第一实施例的剖面图；
图2是本发明芯片载体第二实施例的剖面图；
图3是本发明芯片载体第三实施例的剖面图；
图4是本发明芯片载体第四实施例的剖面图；
图5是本发明芯片载体第五实施例的剖面图；以及
图6是衬底的俯视图，示出了用于制造本发明芯片载体第五
实施例的工序。
具体实施方式
本发明涉及到一种用于引线连接式芯片的芯片载体，这种载体(1)具有相当高的电信号传播速度；(2)容易容纳相当大量的I/O的芯片；(3)无需长的引线连接从而获得相当短的电信号传过引线的“飞行时间”；以及(4)获得了相当高的热耗散速率。
如上所述，本发明的芯片载体由于采用了诸如以商标FR4和DriClad出售的环氧/玻璃配方的有机材料来代替陶瓷材料而获得了相当高的电传播速度。本发明的芯片载体由于至少采用了一种其中形成了光学通道的有机可光学成像介电层作为薄膜再分布层(FRL)以电互连扇出电路的二个(或更多个)层，故还易于容纳相当大量I/O的芯片。本发明的芯片载体避免了相当长的引线连接，因而传过引线连接的电信号获得了相当短的“飞行时间”，这是由于采用了单层坑而不是多层坑来容纳芯片。而且，本发明的芯片载体的某些实施例还含有例如直接位于芯片之下的热通道或金属材料层来增强热传输。
现参照图1，本发明芯片载体10的第一实施例包括一个带有相对表面30和40的芯片载体衬底24。此衬底24还包含多个(例如三个)叠层有机介电层50、60和70，它们由例如以商标FR4和DriClad出售的环氧/玻璃配方组成。虽然在图1中未清楚地示出，此有机介电层50用来支持例如由铜构成的扇出电路层80。在有机介电层50和60之间夹有一层90，它由导电材料例如铜构成，用作电源面。在有机介电层60和70之间夹有另一层100，它由导电材料例如铜组成，用作接地面。
有机介电层50、60和70的厚度范围为约2密尔到约20密尔。小于约2密尔的厚度由于对应的有机介电层不合要求地脆弱、不可靠且难以处置而不可取。大于约20密尔的厚度则由于一般不需要如此厚的介电层以及在如此厚的层中难以钻制通道孔因而也不可取。
各导电材料层80(扇出电路)、90(电源面)和100(接地面)的厚度范围为约0.125密尔到约2.5密尔。小于约0.125密尔的厚度由于相应的导电层常常不能承受芯片载体很可能要遇到的温度变化范围而不可取。大于约2.5密尔的厚度则由于用常规的电镀技术制作如此厚的层要花很长的时间以及与线宽控制有关的困难明显增加而不可取。
如图1所示，芯片载体衬底24还包含一个覆盖着扇出电路层80的有机可光学成像介电层110。层110的可用组分例如是作为本专利参考文献的美国专利5026624所述的可光学成像阳离子可聚合树脂基材料的组分。这种特殊的材料包含一个环氧树脂系统，它的主要组成为约10％-约80％重量的多元醇树脂(它是表氯醇和双酚A的凝聚物，分子量为约40,000-约130,000)；约20％-约90％重量的环氧化八功能双酚A甲醛酚醛树脂(分子量为4,000-10,000)；而若要求阻燃性，则约35％-约50％重量的四溴双酚A的环氧化缩水甘油醚(软化点为约60℃-约110℃，分子量为约600-约2500)。向这种树脂系统中加入0.1％-15％重量的可在暴露于光化幅照时引发上述环氧化树脂系统聚合的阳离子光引发剂；此系统的特性还在于对2.0密尔厚的膜对330-700nm范围内的光的吸收率小于0.1。也可加入诸如二萘嵌苯及其衍生物或并三苯及其衍生物之类的光敏感剂。
用诸如幕涂和辊涂之类的常规涂布技术可容易地沉积有机可光学成像介电层110。可光学成像介电层110的厚度范围为约2密尔-约20密尔。小于约2密尔的厚度由于太难以制作同时又要获得所需的光学成像和介电性质的如此薄的层而不可取。大于约20密尔的厚度由于在如此厚的层中太难以制作小的光学通道而不可取。
用常规光刻技术，可光学成像介电层110可容易地通过掩模而被选择性曝光，然后显影，以制作层110中的光学通道120，为图1所示。(应当指出的是，曝光区受到交叉耦合，因而相对于显影液变得比未曝光区更难溶解。)然后用常规电镀技术把铜之类的导电材料容易地镀于这些光学通道120。
虽然在图1中未清楚地示出，可光学成像介电层110支持着例如由铜组成的含有接触焊点的扇出电路层130。显然，可光学成像介电层110中的电镀光学通道120用来使扇出电路的层130和80互连。重要的是，如上所述，光学通道的直径小于机械钻制通道孔的直径。因此，扇出引线之间的间隔可比原先小。
如图1所示，芯片载体衬底24包含一个单层坑140，其深度只延伸过可光学成像介电层110的厚度。引线连接式芯片150面朝上地置于坑的底部，引线连接160从芯片150上的接触焊点延伸到扇出电路130层的接触焊点。
如图1所示，芯片载体衬底24最好包含(机械钻制的)热通道孔170，它们直接位于芯片150下方并延伸过有机层80、90和100的厚度。这些热通道孔170用来将芯片150产生的热导出到大气中，从而增加热耗散。(应当指出的是，这些热通道孔最好用充银的环氧膏来填充以便增加热传输。还应当指出的是，在最后制造阶段中，对芯片载体10的表面40加了一层焊料掩模材料，因而此焊料掩模材料覆盖着充银的环氧膏。)
热通道孔170的直径范围为约6密尔-约12密尔。小于约6密尔的直径由于相应的热通道孔达到的热传输太小而不可取。大于约12密尔的直径由于与相应热通道孔中充银环氧膏相接触的焊料掩模材料倾向于破裂且覆盖的芯片倾向于从芯片载体衬底剥离而不可取。
如图1所示，芯片载体衬底24还包含多个机械钻制的电镀的通道孔180。各个孔180终止于表面40，由固定在表面40上的例如由铜组成的导电焊盘190所围绕。同样固定在表面40上的是多个导电焊点200以及例如由铜组成的将焊点200连接到电镀通道孔180的电路线(未示出)。安装在焊盘190和焊点200上的是焊球210，其组分包含例如67％的铅和33％的锡。显然，这些焊球将要附着到PCB或PCC上的可焊接触焊点上。
现参照图2，芯片载体10的第二实施例同第一实施例不同之处在于单层坑140的深度还延伸过例如有机层80和90。此外，热沉220附着在表面40，同芯片150和热通道孔170基本垂直对准。而且，焊球210附着在表面30上的焊盘和焊点上。
现参照图3，芯片载体10的第三实施例同第一和第二实施例不同之处在于芯片载体24含有一个紧邻表面30的相当厚的可光学成像介电层110以及一个紧邻表面40的由金属材料例如铜构成的层230。此处，层230部分地用作加强肋且最好是导电地接地的。另一方面，如前所述，可光学成像介电层110负有一个带有接触焊点的扇出电路层130。此外，可光学成像介电层110包含穿过层110厚度伸至导电地接地的金属层230的光学通道120。而且，焊球210附着在扇出电路层130的一些接触焊点上。
如图3所示，芯片载体10的第三实施例包含一个穿过可光学成像介电层110延伸至金属材料层230的单层坑140。引线连接式芯片150位于坑140的底部，且同金属层230直接物理接触。结果，由于金属层230也起热沉的作用而增强了热耗散。
在芯片载体10的第三实施例中，可光学成像介电层110的厚度范围为约2密尔-约20密尔。由于上述已知的原因，超出此范围的厚度是不可取的。
金属层230的厚度范围为约4密尔-约20密尔。小于约4密尔的厚度由于相应的金属层刚性太差而不可取。大于约20密尔的厚度由于相应金属层的热膨胀系数(CTE)主导了相应芯片载体衬底的CTE，引起芯片载体衬底同相应芯片之间的CTE失配，因而导致芯片破裂，故也不可取。
现参照图4，芯片载体10的第四实施例同第三实施例不同之处在于可光学成像介电层110相当薄，且金属层230相当厚。此外，单层坑140穿透可光学成像层110的整个厚度而且部分地延伸过金属层230的厚度。
在芯片载体10的第四实施例中，可光学成像介电层110的厚度范围仍为约2密尔-约20密尔。由于上述已知的理由，超出此范围的厚度都不可取。
金属层230的(总)厚度的范围还是约4密尔-约20密尔。由于上述已知的理由，超出这一范围的厚度也都不可取。
紧邻坑140之下的金属层230的(局部)厚度至少应为约4密尔。小于约4密尔的厚度由于相应的金属层的刚性太差而不可取。
现参照图5，芯片载体10的第五实施例同第一和第二实施例相似之处在于芯片载体衬底24包含多个(例如三个)例如由以商标DriClad出售的环氧/玻璃配方组成的叠层有机介电层50、60和70。如前所述，有机介电层50支持着包含接触焊点的扇出电路层80。夹在有机介电层50和60之间的是一个由导电材料例如铜组成的在此实施例中用作接地面的层90。夹在有机介电层60和70之间的是另一个由导电材料例如铜组成的用作电源面的层100。应当指出的是，接地面横向延伸至坑140的侧壁而电源面不如此。
有机介电层50、60和70的厚度同上面给出的相似。而且，导电层80(扇出电路)、90(接地面)和100(电源面)的厚度也同上面给出的相似。
芯片载体10的第五实施例同第三和第四实施例的相似之处还在于芯片载体衬底24还包含一个最好是接地的金属层230。金属层230的厚度相似于第三实施例中金属层230的厚度。
如图5所示，芯片载体10的第五实施例也包含一个单层坑140，其厚度穿过有机介电层50、60和70延伸至金属层230。芯片150位于坑140的底部，因而同金属层230直接物理接触。结果，由于同前所述金属层230用作热沉而增强了热耗散。
重要的是，芯片载体10的第五实施例同其它实施例的不同之处在于它包含一个由导电材料例如铜构成的附着且围绕着坑140的侧壁的几乎连续的层240。此层240按垂直方向从坑140的底部延伸到坑140的顶部，而横向在有机介电层50的上表面上延伸，邻接于扇出电路的层80。由于接地面90横向延伸至坑140的侧壁，层240就同接地面直接物理和电接触，因而也导电地接地。
由于层240的存在降低了对多个机械钻制的穿透有机介电层50的厚度而延伸至接地面90的通道孔的需要，因而是有利的。这样，若某些芯片接触焊点要导电地接地，则从这些芯片接触焊点的引线连接延伸到有机介电层50表面上的层240，而不是到围绕延伸至接地面90的机械钻制通道孔的焊盘。由于在第五实施例中只需要很少量的这种机械钻制的通道孔，故可有利地减小扇出引线之间的间隔。
应当指出的是，芯片载体10的第五实施例包含一个穿透有机介电层50和60的厚度延伸至电源面100的机械钻制的电镀通道孔180。而且，第五实施例也包含一个金属(例如铜)的环250，此环围绕着坑140且物理地和导电地接触于伸至电源面100的电镀通道孔180。此环250由于消除了对延伸至电源面的额外通道孔的需求而显出优越性。这样，同电源面100的电接触仅仅用电接触环250的方法就达到了。
图6描述了制作层240和环250的方法。如图6所示，当制作坑140时，穿透有机介电层50、60和70以机械方式切出二个直角形槽260和270。这些槽的宽度范围是约25密尔-约100密尔。这些槽的外表面确定了坑140的侧壁。然后在有机介电层50的表面上沉积一层光抗蚀剂280。然后对此光抗蚀剂层进行曝光和显影，以便留下可覆盖除槽260和270、待由层240占据的有机介电层50表面上的区域241、以及待由环250占据的区域251之外的整个有机介电层50的光抗蚀剂。(应当指出的是，此层光抗蚀剂由被槽260和270围绕的有机介电材料层来支持)。然后用常规的引晶和金属电镀技术来使槽260和270、待由层240占据的区域241、以及待由环250占据的区域金属化。再通过槽260和270的中线进行机械切割，然后这些切口延伸以连接这些中心线，并清除切去的材料。这就形成了坑140，使金属在坑140的侧壁附近几乎连续地延伸(除了原来各槽未延伸到的坑角之外)。
尽管参照最佳实施例已对本发明进行了描述，但本技术领域的熟练人员应能理解，可以作出形式和细节方面的各种改变而不超越本发明的构思与范围。

Claims (8)

1.一种芯片载体，它包含：
一个芯片载体衬底，它包含一个第一表面、一个与上述第一表面相对立的第二表面；
其特征在于：
一个紧邻上述第一表面且带有包括接触焊点的电路层的有机材料层、以及一个紧邻上述第二表面的金属材料层；
一个单层坑，其深度从上述第一表面向上述第二表面延伸，上述深度至少延伸到上述金属材料层；
一个面朝上地位于上述坑中并接触上述金属材料层的半导体芯片，上述芯片包含芯片接触焊点和从上述芯片接触焊点延伸到上述有机材料层上接触焊点的引线连接。
2.权利要求1的芯片载体，其特征在于，上述金属材料层导电地接地。
3.权利要求1的芯片载体，其特征在于，上述有机材料层是一个可光学成像层，且上述芯片载体还包含多个含有导电材料的穿过上述可光学成像层厚度延伸至上述金属材料层的光学通道。
4.权利要求1的芯片载体，其特征在于，上述坑的上述深度延伸上述金属材料层的一部分厚度。
5.权利要求1的芯片载体，其特征在于，上述金属材料是铜。
6.权利要求1的芯片载体，其特征在于，上述电路层包含多个导电焊点和焊盘，且上述芯片载体还包含附着于上述焊点和焊盘的焊球。
7.一种芯片载体，它包含：
一个芯片载体衬底，它包含一个第一表面、一个与上述第一表面相对立的第二表面；
其特征在于：
至少第一和第二有机材料层，紧邻上述第一表面的上述第一层带有包含接触焊点的第一电路层，一个接地的第二导电材料层夹在上述第一和第二有机材料层之间，上述芯片载体衬底还包含一个紧邻上述第二表面的金属材料层；
一个单层坑，其深度从上述第一表面向上述第二表面延伸，上述深度至少延伸到上述金属材料层；
一个面朝上地位于上述坑中且接触上述金属材料层的含有芯片接触焊点和从上述芯片接触焊点延伸到上述第一电路层的接触焊点的引线连接的半导体芯片；以及
一个与上述第二导电材料层接触的、至少部分地围绕上述坑侧壁且延伸到上述第一表面上的导电材料区域，引线连接也从上述芯片延伸到上述第一表面上的一部分上述区域。
8.权利要求7的芯片载体，其特征在于，上述第一电路层包含多个导电焊点和焊盘，且上述芯片载体还包含附着在上述焊点和焊盘上的焊球。
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CN1205548A (zh) 1999-01-20
CZ286385B6 (cs) 2000-03-15
PL179061B1 (pl) 2000-07-31
RU2146067C1 (ru) 2000-02-27
JPH08241936A (ja) 1996-09-17
WO1996025763A2 (en) 1996-08-22
DE69605286D1 (de) 1999-12-30
WO1996025763A3 (en) 1996-11-07
CA2164901C (en) 2003-02-11
TW297935B (zh) 1997-02-11
SG34493A1 (en) 1996-12-06
EP0809862B1 (en) 1999-11-24
EP0809862A2 (en) 1997-12-03
US5798909A (en) 1998-08-25
ATE187014T1 (de) 1999-12-15
KR100213955B1 (ko) 1999-08-02
DE69605286T2 (de) 2000-05-25
KR960032659A (ko) 1996-09-17
JP3297287B2 (ja) 2002-07-02
PL321595A1 (en) 1997-12-08
TW301795B (zh) 1997-04-01
CA2164901A1 (en) 1996-08-16
MY140232A (en) 2009-12-31
ES2139330T3 (es) 2000-02-01
US6038137A (en) 2000-03-14
CN1134601A (zh) 1996-10-30
HUP9702316A3 (en) 1998-12-28
CZ225697A3 (cs) 1998-01-14
US5724232A (en) 1998-03-03
CN1041470C (zh) 1998-12-30
US5599747A (en) 1997-02-04
HUP9702316A2 (hu) 1998-03-02
HU216982B (hu) 1999-10-28

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