CN1155080C - 球网格阵列组装件的多串衬底及其组装件的安装方法 - Google Patents

球网格阵列组装件的多串衬底及其组装件的安装方法 Download PDF

Info

Publication number
CN1155080C
CN1155080C CNB951202707A CN95120270A CN1155080C CN 1155080 C CN1155080 C CN 1155080C CN B951202707 A CNB951202707 A CN B951202707A CN 95120270 A CN95120270 A CN 95120270A CN 1155080 C CN1155080 C CN 1155080C
Authority
CN
China
Prior art keywords
bga
pcb
substrate
circuit board
printed circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
CNB951202707A
Other languages
English (en)
Other versions
CN1132462A (zh
Inventor
诺尔曼・L・欧文斯
诺尔曼·L·欧文斯
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NXP USA Inc
Original Assignee
Motorola Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Family has litigation
First worldwide family litigation filed litigation Critical https://patents.darts-ip.com/?family=23371679&utm_source=google_patent&utm_medium=platform_link&utm_campaign=public_patent_search&patent=CN1155080(C) "Global patent litigation dataset” by Darts-ip is licensed under a Creative Commons Attribution 4.0 International License.
Application filed by Motorola Inc filed Critical Motorola Inc
Publication of CN1132462A publication Critical patent/CN1132462A/zh
Application granted granted Critical
Publication of CN1155080C publication Critical patent/CN1155080C/zh
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4803Insulating or insulated parts, e.g. mountings, containers, diamond heatsinks
    • H01L21/481Insulating layers on insulating parts, with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/60Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/12Mountings, e.g. non-detachable insulating substrates
    • H01L23/13Mountings, e.g. non-detachable insulating substrates characterised by the shape
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/50Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93Batch processes
    • H01L24/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/0097Processing two or more printed circuits simultaneously, e.g. made from a common substrate, or temporarily stacked circuit boards
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814Conductive parts
    • H01L21/4846Leads on or in insulating or insulated substrates, e.g. metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/48463Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93Batch processes
    • H01L2224/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/00014Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01006Carbon [C]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01029Copper [Cu]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01033Arsenic [As]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01078Platinum [Pt]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01079Gold [Au]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01082Lead [Pb]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01087Francium [Fr]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/12Passive devices, e.g. 2 terminal devices
    • H01L2924/1204Optical Diode
    • H01L2924/12042LASER
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/12Passive devices, e.g. 2 terminal devices
    • H01L2924/1204Optical Diode
    • H01L2924/12044OLED
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/14Integrated circuits
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/301Electrical effects
    • H01L2924/3025Electromagnetic shielding
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09Shape and layout
    • H05K2201/09009Substrate related
    • H05K2201/09063Holes or slots in insulating substrate not used for electrical connections
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/0011Working of insulating substrates or insulating layers
    • H05K3/0044Mechanical working of the substrate, e.g. drilling or punching
    • H05K3/0052Depaneling, i.e. dividing a panel into circuit boards; Working of the edges of circuit boards
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10TTECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00Metal working
    • Y10T29/49Method of mechanical manufacture
    • Y10T29/49002Electrical device making
    • Y10T29/49117Conductor or circuit manufacturing
    • Y10T29/49124On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49126Assembling bases
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10TTECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00Metal working
    • Y10T29/49Method of mechanical manufacture
    • Y10T29/49002Electrical device making
    • Y10T29/49117Conductor or circuit manufacturing
    • Y10T29/49124On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/4913Assembling to base an electrical component, e.g., capacitor, etc.
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10TTECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00Metal working
    • Y10T29/49Method of mechanical manufacture
    • Y10T29/49002Electrical device making
    • Y10T29/49117Conductor or circuit manufacturing
    • Y10T29/49204Contact or terminal manufacturing
    • Y10T29/49208Contact or terminal manufacturing by assembling plural parts
    • Y10T29/49222Contact or terminal manufacturing by assembling plural parts forming array of contacts or terminals

Abstract

一种用于球网格阵列(BGA)组装件的多串印刷电路板衬底包括一个带有多个排列成N行(14)和M列(16)形成N×M阵列的BGA衬底(12)的印刷电路板(11)。N和M都大于或等于2,且N×M阵列的大小选定为多个BGA衬底(12)中的每一个保持平整度起伏小于约0.15mm(约6密尔)。印刷电路板(11)的厚度(26)足以减小平整度变化并使厂家能够使用自动组装设备而无需采用支持托盘。

Description

球网格阵列组装件的多串 衬底及其组装件的安装方法
技术领域
本发明涉及半导体封装,具体涉及球网格阵列半导体封装。
背景技术
球网格阵列(BGA)半导体封装已为电子工业界所公知。与四边形平面封装(QFP)相比,BGA封装具有更密集的表面安装互连。工业界普遍认为对于输入/输出(I/O)要求大于250来说,BGA封装比QFP封装的“成本和效果”更合算。但强烈要求使成本实惠的BGA解决方案降到100I/O。
在BGA封装的组装过程中,厚度为0.35mm数量级的有机树脂印刷电路板衬底被置于金属托盘即支持装置上。在大部分组装步骤中,金属托盘为印刷电路板提供支持。印刷电路板包含一个单一的BGA衬底或一排或一串的多个BGA衬底。可获得的最大的单串印刷电路板是具有最大总长度约为20mm的1×6印刷电路板。然后将带有多个连接焊盘的半导体管心连接到位于BGA衬底顶侧的管心焊盘上,再将引线连接到焊盘和BGA衬底顶侧上的焊接部位。接着用有机材料包封半导体管心和引线。包封之后,在提高的温度下固化包封材料。再用回流焊工艺使导电焊球连接到位于BGA衬底下侧的接触焊盘并通过导电的迹线(trace)电连接到焊接部位。然后对各BGA封装进行划线。当采用单串多个BGA封装时,使用冲压之类的分割工艺将多个BGA封装分割成单个单元。
上述组装工艺有一些缺点。因上述工艺在大部分组装步骤过程中需要用金属托盘来支持薄的BGA衬底,故此工艺无助于大规模自动化组装。结果,为了组装BGA封装,生产厂家就必须购买额外的设备,这需要设备投资和额外的厂房。而且,又因只采用单个衬底或单串几个衬底,厂家也难以高效率地大批量生产BGA封装。此外,为了在多个工艺步骤中装卸金属托盘即支持装置,需要大量的劳动投入。这对制造周期和质量都有不良影响。再则,托盘与自动化设备一起使用时要求精确的公差而使托盘很昂贵,为了支持生产线的运行,还要求厂家有大量的库存。
组装之后,工业标准要求在横穿衬底的三个点上测量时,每个BGA衬底须保持小于约0.15mm(约6密尔)的平整度起伏。换言之,各BGA衬底不过分弯曲即成为非平整状。由于这一严格的标准和对弯曲的关切,印刷电路板供应商和BGA半导体厂家对于突破现有的1×6单串印刷电路板不感兴趣。
随着对BGA封装迅速增长的要求,显然对有助于大规模自动化组装的、支持现有自动化组装设备的并在组装工序中不弯曲的、且成本和效果合算的印刷电路板有所需求。
发明内容
本发明提供一种用于球网格阵列组装件的多串衬底,其特征在于:一个印刷电路板,具有一个外缘,一个厚度以及安排成N×M阵列的多个BGA衬底,其中N和M大于或等于2,并且其中选择N×M阵列的尺寸以及厚度,使得多个BGA衬底中的每个在组装后在多个BGA衬底中的每个上维持小于大约0.15mm的平整度变化;与多个BGA衬底中的每个相连的半导体管芯;包封每个半导体管芯的覆盖铸模封装件;以及与多个BGA衬底中的每个相连的多个导电焊球。
本发明提供一种用于球网格阵列组装件的衬底,其特征在于:一个印刷线路板,具有两个相对的边、两个相对的端,和多个BGA衬底,所述多个BGA衬底被安排成N×M模式,其中N和M是对应于分别位于印刷线路板内的BGA衬底的行数和列数的整数,其中N和M大于或等于2,并且其中选择N和M,使得多个BGA衬底中的每个在组装时不会弯曲到大于约0.15mm的不平整状况,并且其中印刷线路板的具有的厚度足以支持自动化的组装并使多个BGA衬底中的每个的弯曲最小;与多个BGA衬底中的每个相连的半导体管芯;包封每个半导体管芯的覆盖铸模封装件;以及与多个BGA衬底中的每个相连的多个导电焊球。
本发明还提供一种组装球网格阵列封装件的方法,其特征在于包括以下步骤:提供在具有厚度的印刷电路板中排列成N×M阵列的多个BGA衬底,其中N和M≥2,并且其中N×M阵列的大小以及厚度使得多个BGA衬底中的每一个在组装之后保持平整度变化小于约0.15mm,多个BGA衬底中的每一个都在一侧带有多个焊接部位而在相对侧带有多个接触焊盘;将半导体管芯连接到多个BGA衬底的每一个,此半导体管芯有多个焊接焊盘;用包封剂包封半导体管芯;固化包封剂;将导电焊球连接到多个接触焊盘的每一个;以及将N×M阵列分割成分立的BGA封装件。
附图说明
图1示出了用于根据本发明的BGA组装件的印刷电路板衬底
实施例的俯视图;
图2示出了根据图1的BGA组装件的放大的剖面侧视图。
具体实施方式
参照图1和2可更好地了解本发明。图1示出了多串衬底的印刷电路板(PCB)11的俯视图。PCB 11通常包含一个诸如BT(bis-malein ide-triaz in)树脂、FR-4板之类的有机环氧玻璃树脂基材料。PCB 11包括排列成N行14和M列16组成一个N×M阵列的BGA衬底即图形化封装。每个BGA衬底12包括一个管心安装或连接焊盘13,焊盘13通常含铜或镀金的铜。管心安装焊盘13是一个实心金属化区或一个形似十字、联结插座或其它特定几何形状的图形化金属化区。为避免图中过分拥挤,未示出导线(导线示于图2中)。PCB 11用公知的印刷电路板制造技术来制作。
为了支持有效的大规模自动化组装,N和M最好至少大于或等于2。根据BGA衬底12的最终尺寸,N和M选择成全部组装步骤完成之后,每个BGA衬底12的平整度起伏在各BGA衬底12上都小于0.15mm左右。换言之,在组装过程中,每个BGA衬底12的弯曲不超过约0.15mm。而且,PCB 11的厚度26(示于图2)足以将弯曲减为最小。如下所述,厚度26最好为至少0.5mm数量级。根据标准的工业实践,在一个给定元件中的弯曲是借助于测定支座平面(由三个距离BGA衬底最远的导电焊球形成(见图2)和距离衬底最近的导电焊球之间的最大差值来确定的。弯曲测量在PCB11被分成单个BGA单元之后进行。
PCB 11最好还包括多个位于PCB 11上不同位置处的应力释放槽19。槽19最好伸过PCB 11。槽19的尺寸全部相同或彼此不同。槽19使各BGA衬底12的弯曲进一步减小。PCB 11最好还包括沿PCB 11一边或二个边的对准孔21。对准孔21从PCB 11的上表面延伸到下表面。根据管心安装和引线设备的要求来安置对准孔以支持自动化组装。此外,PCB 11最好包括PCB 11周边附近的孔22和沿PCB 11一个边的孔23。孔22提供了自动定向特点,以使制作人不致于将PCB 11反插入组装设备。孔23提供了定向特点,以使制作人可将PCB 11遥控置入夹具中。
在27mm×27mm BGA器件的最佳实施例中,N=2,M=6,而PCB 11的长度17大约为187mm,宽度18大约为63mm。上述指标对23mm×23mm以及25mm×25mm的BGA器件也是最佳的。在9mm×9mm BGA器件的最佳实施例中,N=4,M=12,而长度17约为200mm,宽度18约为63mm。在10.4mm×10.4mmBGA器件的最佳实施例中,N=4,M=12,而长度17约为212mm,宽度18约为63mm。在15mm×15mm BGA器件的最佳实施例中,N=3,M=9,而长度17约为187mm,宽度18约为63mm。在14mm×22mm BGA器件的最佳实施例中,N=2,M=9,而长度17约为187mm,宽度18约为63mm。对14mm×22mm的BGA器件,也可选N=3,M=6,而长度17和宽度18同上。在35mm×35mm BGA器件的最佳实施例中,N=1,M=4,而长度17约为187mm,宽度18约为63mm。上述尺寸有利于利用标准自动组装设备的要求。这使厂家可利用现有的工具和设备。上述尺寸可方便地修正以满足不同类型自动组装设备的要求。
图2示出了组装之后但在分割成为单个封装件之前的BGA结构物、组件或封装件22的放大的剖面图。BGA结构物22包含一个在PCB 11之中的BGA衬底12。带有BGA结构物12的PCB 11的厚度26最好使PCB 11能够承受连珠式(magazine-to-maga-zine)自动组装工序而不采用金属支持托盘。现今可获得的单个BGA的衬底PCB和单串BGA衬底的PCB的厚度约为0.35mm,若不采用托盘或载体,这一厚度对可靠的自动组装来说是太薄了。厚度26也被选定来使各BGA衬底12的平整度起伏减为最小。厚度26最好大于约0.5mm。厚度26最好在-0.5mm到0.8mm的范围内。
BGA结构物22还包括一个安装在各BGA衬底12上表面上管心安装焊盘13上的半导体管心24。半导体管心24有多个焊接焊盘28。各BGA衬底12都有一个导电连接结构,它包含焊接部位31、上导线32、通孔33、下导线36和接触焊盘38。导电焊球41连接于接触焊盘38。导线43将连接焊盘28电连接到焊接部位31。或者,在倒装片实施例中,半导体管心24用焊接焊盘28直接连接到焊盘28下面的连接部位,省去了导线43和管心连接焊盘13。包封层即包封剂46将半导体管心24和引线43覆盖以保护有源电路元件免遭物理损伤或腐蚀。
以下描述使带有BGA衬底12的PCB 11组成BGA结构物22的典型BGA组装工艺。首先提供带有所需的N×M图形的PCB11。将PCB 11装在ESEC 2006之类的自动管心连接机上。这种管心连接机是一种厂家用来将半导体管心连接到诸如塑料双列直插式(PDIP)、小外线集成电路(SOIC)和QFP封装件之类的其它类型半导体封装件的工业标准机器。管心连接机自动地将一个半导体管心24连接到PCB 11上的一个管心连接焊盘13。最好用管心连接环氧树脂来将半导体管心24连接到管心连接焊盘13。
管心连接之后,用自动清洗系统来清洗PCB 11。接着,将PCB 11置于自动引线机上,将引线43连接到焊接焊盘22和焊接部位31。在常规BGA工艺中,引线是用半自动操作来安装的相似的引线机来完成的。
接着,用包装剂46覆盖半导体管心24和引线43。包封剂46包含一种有机材料,用覆盖铸模(overmold)工艺或球状工艺包敷。可以采用自动模具来进行覆盖铸模工艺。当采用覆盖铸模工艺时,包封剂46最好含有一种有机成模化合物。当采用球状工艺时,包封剂46最好含有一种脱水环氧有机化合物。选为包封剂46的材料的热膨胀系数(TCE)最好接近PCB 11材料和半导体管心的TCE(差别在百万分之几以内)。这进一步有助于在剩下的安装工序中减小BGA衬底12的弯曲。
接着,最好用带式炉、垂直炉或批量处理炉来固化包封剂46,使用的温度随用作包封剂46的材料类型而不同。在固化工序中,最好用退火箱或其它某种保护方法来保护接触焊盘38免遭外来物质的沾污。
在包封之后,用室温连接工艺将导电焊球41连接到接触焊盘38。接着用自动回流焊工艺来回流导电焊球41。自动回流设备为带式炉。回流之后,用自动清洗设备再次清洗PCB11,用含水的或萜烯溶剂来清除导电焊球安装工序引起的各种腐蚀性残渣。然后在自动划片机(如自动激光划片机)上对各BGA结构22进行划片。也可任选地在包封之后立即划片。最后将各BGA衬底12分成分立封装件。采用冲压工艺来分割封装件。也可采用常规切割折断分割工艺。
至此,显然已提供了一种多串PCB,它包含一个用来制造BGA型半导体封装件的BGA衬底的N×M阵列。N、M及PCB的厚度的选定原则是要能提高制造效率。制造效率的提高从一个多串PCB制造更多的BGA封装件的能力以及采用标准自动组装设备的能力。制造效率提高的同时,还要使BGA衬底的平整度起伏小于约0.15mm。由于根据本发明的多串PGB可使用标准的自动组装设备,BGA厂家就可使用相同类型的设备来制造不同类型的封装件,从而降低了基建投资和所需的厂房面积。由于降低了处置要求,从而也减小了劳力成本并提高了质量。

Claims (10)

1.一种用于球网格阵列(BGA)组装件的多串衬底,其特征在于:
一个印刷电路板(11),具有一个外缘,一个厚度(26)以及安排成N×M阵列的多个BGA衬底(12),其中N和M大于或等于2,并且其中选择N×M阵列的尺寸以及厚度(26),使得多个BGA衬底(12)中的每个在组装后在多个BGA衬底中的每个上维持小于大约0.15mm的平整度变化;
与多个BGA衬底中的每个相连的半导体管芯;
包封每个半导体管芯的覆盖铸模封装件;以及
与多个BGA衬底中的每个相连的多个导电焊球。
2.权利要求1的多串衬底,其特征在于,印刷电路板(11)还包括印刷电路板(11)中不同位置处的多个槽(19),用以进一步减小平整度变化。
3.权利要求1的多串衬底,其特征在于,印刷电路板(11)包含一种有机树脂。
4.权利要求1的多串衬底,其特征在于,厚度(26)大于约0.5mm。
5.一种用于球网格阵列(BGA)组装件的衬底,其特征在于:
一个印刷线路板(11),具有两个相对的边、两个相对的端,和多个BGA衬底(12),所述多个BGA衬底(12)被安排成N×M模式,其中N和M是对应于分别位于印刷线路板内的BGA衬底的行数和列数的整数,其中N和M大于或等于2,并且其中选择N和M,使得多个BGA衬底(12)中的每个在组装时不会弯曲到大于约0.15mm的不平整状况,并且其中印刷线路板的(11)具有的厚度(26)足以支持自动化的组装并使多个BGA衬底(12)中的每个的弯曲最小;
与多个BGA衬底中的每个相连的半导体管芯;
包封每个半导体管芯的覆盖铸模封装件;以及
与多个BGA衬底中的每个相连的多个导电焊球。
6.权利要求5的衬底,其特征在于,印刷电路板(11)沿二个相对的边的至少一个边有一个对准孔(21)。
7.一种组装球网格阵列(BGA)封装件的方法,其特征在于包括以下步骤:
提供在具有厚度(26)的印刷电路板(11)中排列成N×M阵列的多个BGA衬底(12),其中N和M≥2,并且其中N×M阵列的大小以及厚度(26)使得多个BGA衬底(12)中的每一个在组装之后保持平整度变化小于约0.15mm,多个BGA衬底(12)中的每一个都在一侧带有多个焊接部位(31)而在相对侧带有多个接触焊盘(38);
将半导体管芯(24)连接到多个BGA衬底(12)的每一个,此半导体管芯有多个焊接焊盘(28);
用包封剂(46)包封半导体管芯(24);
固化包封剂;
将导电焊球(41)连接到多个接触焊盘(31)的每一个;以及
将N×M阵列分割成分立的BGA封装件(22)。
8.权利要求7的方法,其特征在于,包封半导体管芯(24)的步骤包括采用TCE接近半导体管芯(18)和印刷电路板(11)的TCE的包封剂来包封。
9.权利要求7的方法,其特征在于,提供在印刷电路板(11)中排列成N×M阵列的多个BGA衬底(12)的步骤包括在其中不同位置处带有多个应力释放槽(19)的一个印刷电路板中提供多个BGA衬底(12)。
10.权利要求7的方法,其特征在于,提供多个在印刷电路板(11)中排列成N×M阵列的BGA衬底(12)的步骤包括在厚度(26)大于约0.5mm的印刷电路板(11)中提供多个BGA衬底(12)。
CNB951202707A 1994-12-05 1995-11-27 球网格阵列组装件的多串衬底及其组装件的安装方法 Expired - Lifetime CN1155080C (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US349,281 1989-05-08
US349281 1994-12-05
US08/349,281 US6465743B1 (en) 1994-12-05 1994-12-05 Multi-strand substrate for ball-grid array assemblies and method

Publications (2)

Publication Number Publication Date
CN1132462A CN1132462A (zh) 1996-10-02
CN1155080C true CN1155080C (zh) 2004-06-23

Family

ID=23371679

Family Applications (1)

Application Number Title Priority Date Filing Date
CNB951202707A Expired - Lifetime CN1155080C (zh) 1994-12-05 1995-11-27 球网格阵列组装件的多串衬底及其组装件的安装方法

Country Status (6)

Country Link
US (5) US6465743B1 (zh)
JP (1) JP3493088B2 (zh)
KR (1) KR100400949B1 (zh)
CN (1) CN1155080C (zh)
MY (1) MY119990A (zh)
TW (1) TW280019B (zh)

Families Citing this family (55)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6465743B1 (en) * 1994-12-05 2002-10-15 Motorola, Inc. Multi-strand substrate for ball-grid array assemblies and method
US5776798A (en) * 1996-09-04 1998-07-07 Motorola, Inc. Semiconductor package and method thereof
JP4311774B2 (ja) * 1998-03-11 2009-08-12 富士通株式会社 電子部品パッケージおよびプリント配線板
US6501157B1 (en) * 1998-04-15 2002-12-31 Micron Technology, Inc. Substrate for accepting wire bonded or flip-chip components
KR100365054B1 (ko) * 1999-09-07 2002-12-16 앰코 테크놀로지 코리아 주식회사 반도체패키지용 섭스트레이트 및 이를 이용한 반도체패키지의 제조방법
DE10010979A1 (de) * 2000-03-07 2001-09-13 Bosch Gmbh Robert Elektrische Schaltung und Substrat hierzu
KR100456817B1 (ko) * 2000-06-13 2004-11-11 앰코 테크놀로지 코리아 주식회사 반도체 패키지 제조용 부재와 이것을 이용한 반도체패키지 제조방법
US6931298B1 (en) 2001-02-27 2005-08-16 Cypress Semiconductor Corporation Integrated back-end integrated circuit manufacturing assembly
US6901984B1 (en) 2001-02-27 2005-06-07 Cypress Semiconductor Corporation Method and system for controlling the processing of an integrated circuit chip assembly line using a central computer system and a common communication protocol
JP4626919B2 (ja) * 2001-03-27 2011-02-09 ルネサスエレクトロニクス株式会社 半導体装置
US20020170897A1 (en) * 2001-05-21 2002-11-21 Hall Frank L. Methods for preparing ball grid array substrates via use of a laser
US7276802B2 (en) * 2002-04-15 2007-10-02 Micron Technology, Inc. Semiconductor integrated circuit package having electrically disconnected solder balls for mounting
JP4283514B2 (ja) * 2002-09-24 2009-06-24 株式会社日立製作所 電子回路装置
TW575931B (en) * 2002-10-07 2004-02-11 Advanced Semiconductor Eng Bridge connection type of chip package and process thereof
JP4079874B2 (ja) * 2003-12-25 2008-04-23 沖電気工業株式会社 半導体装置の製造方法
DE102004015091B4 (de) * 2004-03-25 2006-05-04 Infineon Technologies Ag Flächenhafter Verdrahtungsträger
US7105377B1 (en) * 2004-04-13 2006-09-12 Cypress Semiconductor Corporation Method and system for universal packaging in conjunction with a back-end integrated circuit manufacturing process
JP5430066B2 (ja) * 2004-07-07 2014-02-26 プロメラス, エルエルシー 絶縁樹脂組成物及びその使用
US7223923B2 (en) * 2004-10-26 2007-05-29 Hannstar Display Corporation PCB capable of releasing thermal stress
US20090008792A1 (en) * 2004-11-19 2009-01-08 Industrial Technology Research Institute Three-dimensional chip-stack package and active component on a substrate
TWI256694B (en) * 2004-11-19 2006-06-11 Ind Tech Res Inst Structure with embedded active components and manufacturing method thereof
US7148560B2 (en) * 2005-01-25 2006-12-12 Taiwan Semiconductor Manufacturing Co., Ltd. IC chip package structure and underfill process
US7656172B2 (en) 2005-01-31 2010-02-02 Cascade Microtech, Inc. System for testing semiconductors
JP2006278610A (ja) * 2005-03-29 2006-10-12 Sanyo Electric Co Ltd 半導体装置及びその製造方法
US7521781B2 (en) * 2005-04-25 2009-04-21 Stats Chippac Ltd. Integrated circuit package system with mold clamp line critical area having widened conductive traces
KR100695065B1 (ko) 2006-03-27 2007-03-14 삼성전기주식회사 기판의 표면 평탄도 측정용 쿠폰 및 이를 이용한 기판의표면 평탄도 측정방법
US20070253179A1 (en) * 2006-04-27 2007-11-01 Briggs Randall D Method and apparatus for removing surface mount device from printed circuit board
KR100728989B1 (ko) 2006-06-30 2007-06-15 주식회사 하이닉스반도체 Fbga 패키지 제조용 기판
BRPI0719890A2 (pt) * 2006-10-10 2014-05-06 Tir Technology Lp Painel de circuito impresso e métodos de preparar e de montar um painel de circuito impresso
JP5194471B2 (ja) * 2007-02-06 2013-05-08 パナソニック株式会社 半導体装置
JP4569683B2 (ja) * 2007-10-16 2010-10-27 東芝ライテック株式会社 発光素子ランプ及び照明器具
JP2010010428A (ja) * 2008-06-27 2010-01-14 Fujitsu Ltd プリント基板及び電子機器
JP5223571B2 (ja) * 2008-09-30 2013-06-26 富士通株式会社 半導体装置、基板設計方法、基板設計装置
TWI428995B (zh) * 2008-10-20 2014-03-01 United Test & Assembly Ct Lt 板上縮小封裝
JP5333758B2 (ja) 2009-02-27 2013-11-06 東芝ライテック株式会社 照明装置および照明器具
US8159830B2 (en) * 2009-04-17 2012-04-17 Atmel Corporation Surface mounting chip carrier module
JP5348410B2 (ja) 2009-06-30 2013-11-20 東芝ライテック株式会社 口金付ランプおよび照明器具
JP5354191B2 (ja) * 2009-06-30 2013-11-27 東芝ライテック株式会社 電球形ランプおよび照明器具
JP2011049527A (ja) 2009-07-29 2011-03-10 Toshiba Lighting & Technology Corp Led照明装置
JP2011071242A (ja) * 2009-09-24 2011-04-07 Toshiba Lighting & Technology Corp 発光装置及び照明装置
CN102032481B (zh) 2009-09-25 2014-01-08 东芝照明技术株式会社 附带灯口的照明灯及照明器具
CN102032480B (zh) 2009-09-25 2013-07-31 东芝照明技术株式会社 灯泡型灯以及照明器具
CN102032479B (zh) * 2009-09-25 2014-05-07 东芝照明技术株式会社 灯泡型灯以及照明器具
JP2011091033A (ja) 2009-09-25 2011-05-06 Toshiba Lighting & Technology Corp 発光モジュール、電球形ランプおよび照明器具
JP5257622B2 (ja) 2010-02-26 2013-08-07 東芝ライテック株式会社 電球形ランプおよび照明器具
CN102881804B (zh) * 2011-07-15 2015-06-10 光宝电子(广州)有限公司 基板结构、半导体装置阵列及其半导体装置
US8884427B2 (en) * 2013-03-14 2014-11-11 Invensas Corporation Low CTE interposer without TSV structure
US9099363B1 (en) 2014-02-12 2015-08-04 Freescale Semiconductor, Inc. Substrate with corner cut-outs and semiconductor device assembled therewith
US20180130768A1 (en) * 2016-11-09 2018-05-10 Unisem (M) Berhad Substrate Based Fan-Out Wafer Level Packaging
US20190259731A1 (en) * 2016-11-09 2019-08-22 Unisem (M) Berhad Substrate based fan-out wafer level packaging
US10181447B2 (en) 2017-04-21 2019-01-15 Invensas Corporation 3D-interconnect
US10880995B2 (en) * 2017-12-15 2020-12-29 2449049 Ontario Inc. Printed circuit board with stress relief zones for component and solder joint protection
CN111465312A (zh) * 2020-04-14 2020-07-28 杭州洛微科技有限公司 基于周期性阵列排布的光电产品封装生产方法
TW202232708A (zh) * 2021-02-09 2022-08-16 群創光電股份有限公司 電子裝置
US20230126272A1 (en) * 2021-10-25 2023-04-27 Nanya Technology Corporation Semiconductor device with interface structure

Family Cites Families (102)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US500689A (en) * 1893-07-04 Lifting-jack
US3413713A (en) 1965-06-18 1968-12-03 Motorola Inc Plastic encapsulated transistor and method of making same
US3444441A (en) 1965-06-18 1969-05-13 Motorola Inc Semiconductor devices including lead and plastic housing structure suitable for automated process construction
US3606673A (en) 1968-08-15 1971-09-21 Texas Instruments Inc Plastic encapsulated semiconductor devices
JPS5218069B2 (zh) * 1972-08-09 1977-05-19
FR2524707B1 (fr) 1982-04-01 1985-05-31 Cit Alcatel Procede d'encapsulation de composants semi-conducteurs, et composants encapsules obtenus
US4508758A (en) * 1982-12-27 1985-04-02 At&T Technologies, Inc. Encapsulated electronic circuit
US4808990A (en) * 1983-11-11 1989-02-28 Sharp Kabushiki Kaisha Liquid crystal display assembly
US4518631A (en) * 1983-11-14 1985-05-21 Dow Corning Corporation Thixotropic curable coating compositions
JPS60116191A (ja) * 1983-11-29 1985-06-22 イビデン株式会社 電子部品搭載用基板の製造方法
US4654290A (en) * 1985-02-01 1987-03-31 Motorola, Inc. Laser markable molding compound, method of use and device therefrom
US4595647A (en) * 1985-02-01 1986-06-17 Motorola, Inc. Method for encapsulating and marking electronic devices
JPS61222151A (ja) * 1985-03-27 1986-10-02 Ibiden Co Ltd 半導体搭載用プリント配線板の製造方法
DE3606283A1 (de) * 1985-07-31 1987-02-12 Mtu Muenchen Gmbh Buerstendichtung
US4703984A (en) * 1985-10-28 1987-11-03 Burroughs Corporation Flexible access connector with miniature slotted pads
US4674811A (en) * 1986-07-10 1987-06-23 Honeywell Inc. Apparatus for connecting pin grid array devices to printed wiring boards
EP0261324A1 (en) 1986-09-26 1988-03-30 Texas Instruments Incorporated Plastic package for large chip size integrated circuit
JPS63148670A (ja) * 1986-12-12 1988-06-21 Texas Instr Japan Ltd リ−ドフレ−ム材
JPS63169752A (ja) * 1986-12-31 1988-07-13 テキサス インスツルメンツ インコーポレイテッド 多段icパッケージを製造するためのマトリクスリードフレーム
US4821007A (en) * 1987-02-06 1989-04-11 Tektronix, Inc. Strip line circuit component and method of manufacture
KR960006710B1 (ko) * 1987-02-25 1996-05-22 가부시기가이샤 히다찌세이사꾸쇼 면실장형 반도체집적회로장치 및 그 제조방법과 그 실장방법
US4734820A (en) * 1987-04-16 1988-03-29 Ncr Corporation Cryogenic packaging scheme
JPH0834264B2 (ja) 1987-04-21 1996-03-29 住友電気工業株式会社 半導体装置およびその製造方法
GB2209867B (en) * 1987-09-16 1990-12-19 Advanced Semiconductor Package Method of forming an integrated circuit chip carrier
US4871317A (en) * 1987-12-02 1989-10-03 A. O. Smith Corporation Surface mounted component adaptor for interconnecting of surface mounted circuit components
US4890383A (en) 1988-01-15 1990-01-02 Simens Corporate Research & Support, Inc. Method for producing displays and modular components
JPH0247855A (ja) 1988-08-10 1990-02-16 Nec Corp 半導体装置
JPH0710496Y2 (ja) 1989-01-30 1995-03-08 日本航空電子工業株式会社 Icパッケージ用コネクタ
US4930216A (en) * 1989-03-10 1990-06-05 Microelectronics And Computer Technology Corporation Process for preparing integrated circuit dies for mounting
US4999700A (en) * 1989-04-20 1991-03-12 Honeywell Inc. Package to board variable pitch tab
JPH02301155A (ja) 1989-05-16 1990-12-13 Citizen Watch Co Ltd Icモジュールの固定方法
US5200362A (en) * 1989-09-06 1993-04-06 Motorola, Inc. Method of attaching conductive traces to an encapsulated semiconductor die using a removable transfer film
US4961821A (en) 1989-11-22 1990-10-09 Xerox Corporation Ode through holes and butt edges without edge dicing
US5006673A (en) 1989-12-07 1991-04-09 Motorola, Inc. Fabrication of pad array carriers from a universal interconnect structure
US5071375A (en) * 1990-01-22 1991-12-10 Savage John Jun Electrical contact and multiple contact assembly
US4994936A (en) * 1990-02-12 1991-02-19 Rogers Corporation Molded integrated circuit package incorporating decoupling capacitor
US5061657A (en) 1990-07-18 1991-10-29 The United States Of America As Represented By The Secretary Of The Navy Method of making integrated circuit to package electrical connections after encapsulation with an organic polymer
US5679977A (en) * 1990-09-24 1997-10-21 Tessera, Inc. Semiconductor chip assemblies, methods of making same and components for same
US5148266A (en) * 1990-09-24 1992-09-15 Ist Associates, Inc. Semiconductor chip assemblies having interposer and flexible lead
US5148265A (en) * 1990-09-24 1992-09-15 Ist Associates, Inc. Semiconductor chip assemblies with fan-in leads
JP2967215B2 (ja) 1990-10-12 1999-10-25 株式会社村田製作所 チップ型電子部品の製造方法
US5136366A (en) 1990-11-05 1992-08-04 Motorola, Inc. Overmolded semiconductor package with anchoring means
JPH04196253A (ja) * 1990-11-28 1992-07-16 Mitsubishi Electric Corp 半導体装置用パッケージ
US5216278A (en) * 1990-12-04 1993-06-01 Motorola, Inc. Semiconductor device having a pad array carrier package
JP2564707B2 (ja) * 1991-01-09 1996-12-18 ローム株式会社 電子部品用リードフレームにおけるモールド部のマルチ式成形方法及び成形装置
JPH04254363A (ja) 1991-02-06 1992-09-09 Hitachi Ltd リードフレーム及びそれを用いた半導体集積回路装置
US5172214A (en) * 1991-02-06 1992-12-15 Motorola, Inc. Leadless semiconductor device and method for making the same
US5153385A (en) * 1991-03-18 1992-10-06 Motorola, Inc. Transfer molded semiconductor package with improved adhesion
US5341039A (en) * 1991-04-19 1994-08-23 Mitsubishi Denki Kabushiki Kaisha High frequency integrated circuit device including a circuit for decreasing reflected signals in wiring formed on a semiconductor substrate
WO1992020097A1 (en) * 1991-04-26 1992-11-12 Citizen Watch Co., Ltd. Semiconductor device and manufacturing method therefor
KR940003560B1 (ko) 1991-05-11 1994-04-23 금성일렉트론 주식회사 적층형 반도체 패키지 및 그 제조방법.
JPH04362091A (ja) * 1991-06-05 1992-12-15 Mitsubishi Heavy Ind Ltd プラズマ化学気相成長装置
US5164817A (en) * 1991-08-14 1992-11-17 Vlsi Technology, Inc. Distributed clock tree scheme in semiconductor packages
JPH05190737A (ja) 1992-01-13 1993-07-30 Ngk Insulators Ltd リードフレーム
US5334857A (en) * 1992-04-06 1994-08-02 Motorola, Inc. Semiconductor device with test-only contacts and method for making the same
US5280193A (en) 1992-05-04 1994-01-18 Lin Paul T Repairable semiconductor multi-package module having individualized package bodies on a PC board substrate
JPH05315515A (ja) 1992-05-07 1993-11-26 Nec Corp 半導体装置
JP2617402B2 (ja) 1992-06-10 1997-06-04 オリジン電気株式会社 半導体装置、電子回路装置、およびそれらの製造方法
US5248903A (en) * 1992-09-18 1993-09-28 Lsi Logic Corporation Composite bond pads for semiconductor devices
US5729894A (en) * 1992-07-21 1998-03-24 Lsi Logic Corporation Method of assembling ball bump grid array semiconductor packages
US5592025A (en) * 1992-08-06 1997-01-07 Motorola, Inc. Pad array semiconductor device
JP3046151B2 (ja) * 1992-08-10 2000-05-29 ローム株式会社 リードフレーム
US5612576A (en) * 1992-10-13 1997-03-18 Motorola Self-opening vent hole in an overmolded semiconductor device
JPH06132423A (ja) 1992-10-19 1994-05-13 Sharp Corp 半導体装置の製造方法
US5535101A (en) * 1992-11-03 1996-07-09 Motorola, Inc. Leadless integrated circuit package
KR100280762B1 (ko) 1992-11-03 2001-03-02 비센트 비.인그라시아 노출 후부를 갖는 열적 강화된 반도체 장치 및 그 제조방법
JPH06169051A (ja) 1992-11-27 1994-06-14 Sumitomo Special Metals Co Ltd リードフレームとその製造方法並びに半導体パッケージ
US5363075A (en) 1992-12-03 1994-11-08 Hughes Aircraft Company Multiple layer microwave integrated circuit module connector assembly
JPH06216179A (ja) 1993-01-21 1994-08-05 Hitachi Ltd 半導体装置の製造方法およびその製造に用いるリードフレームならびにトランスファモールド型
US5371404A (en) * 1993-02-04 1994-12-06 Motorola, Inc. Thermally conductive integrated circuit package with radio frequency shielding
US5353498A (en) * 1993-02-08 1994-10-11 General Electric Company Method for fabricating an integrated circuit module
US5355283A (en) * 1993-04-14 1994-10-11 Amkor Electronics, Inc. Ball grid array with via interconnection
US5316965A (en) * 1993-07-29 1994-05-31 Digital Equipment Corporation Method of decreasing the field oxide etch rate in isolation technology
US5336931A (en) * 1993-09-03 1994-08-09 Motorola, Inc. Anchoring method for flow formed integrated circuit covers
US5346118A (en) * 1993-09-28 1994-09-13 At&T Bell Laboratories Surface mount solder assembly of leadless integrated circuit packages to substrates
JPH07111254A (ja) * 1993-10-12 1995-04-25 Sumitomo Electric Ind Ltd 半導体装置の製造方法
US5467252A (en) * 1993-10-18 1995-11-14 Motorola, Inc. Method for plating using nested plating buses and semiconductor device having the same
US5446625A (en) * 1993-11-10 1995-08-29 Motorola, Inc. Chip carrier having copper pattern plated with gold on one surface and devoid of gold on another surface
GB2283863A (en) * 1993-11-16 1995-05-17 Ibm Direct chip attach module
US5462636A (en) 1993-12-28 1995-10-31 International Business Machines Corporation Method for chemically scribing wafers
TW272311B (zh) * 1994-01-12 1996-03-11 At & T Corp
US5435482A (en) * 1994-02-04 1995-07-25 Lsi Logic Corporation Integrated circuit having a coplanar solder ball contact array
FR2716555B1 (fr) 1994-02-24 1996-05-15 Gemplus Card Int Procédé de fabrication d'une carte sans contact.
US5635671A (en) * 1994-03-16 1997-06-03 Amkor Electronics, Inc. Mold runner removal from a substrate-based packaged electronic device
EP1213754A3 (en) * 1994-03-18 2005-05-25 Hitachi Chemical Co., Ltd. Fabrication process of semiconductor package and semiconductor package
US5468999A (en) * 1994-05-26 1995-11-21 Motorola, Inc. Liquid encapsulated ball grid array semiconductor device with fine pitch wire bonding
JP3541491B2 (ja) 1994-06-22 2004-07-14 セイコーエプソン株式会社 電子部品
US5467253A (en) * 1994-06-30 1995-11-14 Motorola, Inc. Semiconductor chip package and method of forming
US5436203A (en) * 1994-07-05 1995-07-25 Motorola, Inc. Shielded liquid encapsulated semiconductor device and method for making the same
US5525834A (en) * 1994-10-17 1996-06-11 W. L. Gore & Associates, Inc. Integrated circuit package
US5491111A (en) 1994-10-26 1996-02-13 Tai; George Method of making a semiconductor diode
US5541450A (en) * 1994-11-02 1996-07-30 Motorola, Inc. Low-profile ball-grid array semiconductor package
US6465743B1 (en) * 1994-12-05 2002-10-15 Motorola, Inc. Multi-strand substrate for ball-grid array assemblies and method
JP3438369B2 (ja) 1995-01-17 2003-08-18 ソニー株式会社 部材の製造方法
US5652185A (en) * 1995-04-07 1997-07-29 National Semiconductor Corporation Maximized substrate design for grid array based assemblies
US5612513A (en) 1995-09-19 1997-03-18 Micron Communications, Inc. Article and method of manufacturing an enclosed electrical circuit using an encapsulant
US5700981A (en) * 1996-02-08 1997-12-23 Micron Communications, Inc. Encapsulated electronic component and method for encapsulating an electronic component
US5604160A (en) 1996-07-29 1997-02-18 Motorola, Inc. Method for packaging semiconductor devices
US5776798A (en) * 1996-09-04 1998-07-07 Motorola, Inc. Semiconductor package and method thereof
US5981314A (en) 1996-10-31 1999-11-09 Amkor Technology, Inc. Near chip size integrated circuit package
US6172419B1 (en) * 1998-02-24 2001-01-09 Micron Technology, Inc. Low profile ball grid array package
US6302101B1 (en) * 1999-12-14 2001-10-16 Daniel Py System and method for application of medicament into the nasal passage

Also Published As

Publication number Publication date
US7397001B2 (en) 2008-07-08
US7199306B2 (en) 2007-04-03
JP3493088B2 (ja) 2004-02-03
US20030027377A1 (en) 2003-02-06
US20040129452A1 (en) 2004-07-08
KR960026504A (ko) 1996-07-22
CN1132462A (zh) 1996-10-02
US20070137889A1 (en) 2007-06-21
US20080289867A1 (en) 2008-11-27
MY119990A (en) 2005-08-30
TW280019B (zh) 1996-07-01
KR100400949B1 (ko) 2003-12-06
JPH08222654A (ja) 1996-08-30
US6465743B1 (en) 2002-10-15
US6710265B2 (en) 2004-03-23

Similar Documents

Publication Publication Date Title
CN1155080C (zh) 球网格阵列组装件的多串衬底及其组装件的安装方法
CN100350601C (zh) 多行引线框架
KR20020027233A (ko) 반도체 장치 및 그의 제조 방법
WO2006077452A1 (en) Leadframe, semiconductor package and methods of producing the same
US8283762B2 (en) Lead frame based semiconductor package and a method of manufacturing the same
KR100214544B1 (ko) 볼 그리드 어레이 반도체 패키지
CN106206326B (zh) 用于制造表面安装类型半导体器件的方法以及对应的半导体器件
US20020113301A1 (en) Leadless semiconductor package
US5270570A (en) Lead frame for a multiplicity of terminals
CN100378992C (zh) 一种半导体封装件及其制法
CN101378023B (zh) 半导体封装件及其制法
KR19990065532A (ko) Cob형 반도체 패키지의 제조방법
US6291309B1 (en) Semiconductor device and method for manufacturing the same
US6281026B1 (en) Semiconductor device and method for manufacturing the same
KR100233864B1 (ko) 리드프레임을 이용한 에어리어 어레이 범프드 반도체 패키지의 입출력 범프 형성방법
KR100251860B1 (ko) Csp (칩 스케일 패키지)의 구조 및 제조방법
KR100271180B1 (ko) F-bga 반도체패키지의 제조방법 및 몰드금형 구조
KR100331069B1 (ko) 반도체 패키지의 저면으로 입출력 단자가 배열되는 리드프레임 제조방법
KR100280412B1 (ko) 버틈 리드 패키지의 표면 실장용 인쇄 회로기판 및 표면 실장방법
KR100390946B1 (ko) 반도체 소자의 패키지 방법
JPH07307408A (ja) Icパッケージおよびその組立方法
KR19980039674A (ko) 반도체 패키지의 저면으로 솔더볼이 융착된 리드프레임 제조방법
US20060258058A1 (en) Surface-mounted device with leads
KR20040070926A (ko) Pcb 패드 구조와 그 형성방법, 및 그 패드 구조 위에표면 실장 부품을 탑재하는 실장 방법
KR20000041703A (ko) 패키지의 부분조립이 이루어지는 칩 검사방법

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
ASS Succession or assignment of patent right

Owner name: FREEDOM SEMICONDUCTORS CO.

Free format text: FORMER OWNER: MOTOROLA, INC.

Effective date: 20040820

C41 Transfer of patent application or patent right or utility model
TR01 Transfer of patent right

Effective date of registration: 20040820

Address after: Texas in the United States

Patentee after: FreeScale Semiconductor

Address before: Illinois, USA

Patentee before: Motorola, Inc.

C56 Change in the name or address of the patentee

Owner name: FISICAL SEMICONDUCTOR INC.

Free format text: FORMER NAME: FREEDOM SEMICONDUCTOR CORP.

CP01 Change in the name or title of a patent holder

Address after: Texas in the United States

Patentee after: FREESCALE SEMICONDUCTOR, Inc.

Address before: Texas in the United States

Patentee before: FreeScale Semiconductor

CX01 Expiry of patent term

Granted publication date: 20040623

EXPY Termination of patent right or utility model