CN1160934A - 半导体器件及其制造方法 - Google Patents

半导体器件及其制造方法 Download PDF

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CN1160934A
CN1160934A CN96117912A CN96117912A CN1160934A CN 1160934 A CN1160934 A CN 1160934A CN 96117912 A CN96117912 A CN 96117912A CN 96117912 A CN96117912 A CN 96117912A CN 1160934 A CN1160934 A CN 1160934A
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semiconductor device
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石井秀基
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Mitsubishi Electric Corp
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Abstract

一种可实现薄型化、可改善散热性，并可多层化的半导体器件及其制造方法。用铸模树脂5b把IC芯片1、金丝2、芯片焊盘3b的一部分盖起来。芯片焊盘3b从铸模树脂5b中露出来。把外部引线4b形成为从与芯片焊盘3b的外露面同一平面，沿着铸模树脂5b一直到与芯片焊盘3b相反一侧的铸模树脂5b的表面一侧。因此，可实现半导体器件的薄型化。因使芯片焊盘外露，故可以改善散热性，并借助于把外部引线4b形成于铸模树脂5b的上下，故使半导体器件的多层化成为可能。

Description

半导体器件及其制造方法
本发明涉及用IC封装密封起来的半导体器件及其制造方法，特别是涉及可实现薄型化，改善散热性及可以实现多层化的半导体器件及其制造方法。
图18是现有的半导体器件的IC封装的断面图。在图18中，1是IC(半导体集成电路)芯片，2是金丝，3a是芯片焊盘、4a是介以金丝2与IC芯片电连并与基板等进行外部连接的外部引线，5a是铸模树脂。
示于图18的现有的半导体器件中存在着下述I-III的问题。
I.由于与基板等进行电连的外部引线4a被配置为比芯片焊盘3的位置往下，故半导体器件难于薄型化。
II.由于芯片焊盘3设于IC封装主体(铸模树脂5a)内部，故散热性差。
III.由于与基板等进行外部接触的外部引线4a仅仅配置在半导体器件的下边的一个方向，故半导体器件的多层化是困难的。
本发明就是为了解次这些问题而创造出来的，目的是提供一种可实现半导体器件的薄型化、可改善散热性、可实现多层化的半导体器件及其制造方法。
本发明的第1方面的课题解决方法具备有半导体集成电路芯片，把上述半导体集成电路芯片设置于一侧的主面上的连接板，把上述半导体集成电路芯片和上述连接板的上述一侧的主面覆盖起来的半导体器件的封装主体，并使上述连接板的另一侧的主面从上述封装主体中露出来。
本发明的第2方面的课题解决方法还具备有外部端子，该外部端子与上述半导体集成电路芯片电连，并被形成为从与上述连接板的上述另一侧的主面的同一平面一直到与该另一侧的主面相反一侧的上述封装主体的表面一侧。
本发明的第3方面的课题解决方法中，形成于上述外部端子的上述封装主体的表面一侧的部分和上述封装主体的表面是同一平面。
本发明的第4方面的课题解决方法在上述外端子之内还具备有把与外部之间进行连接部分之外的部分盖住的保护材料。
本发明的第5方面的课题解决方法，在上述外部端子的与外部之间的连接部分上还具备有用于把上述外部端子与上述外部进行电连的连接材料。
本发明的第6方面的课题解决方法中，上述外部端子在与外部之间的连接部分上有凸出部分。
本发明的第7方面的课题解决方法中。上述外部端子由多个外部端子构成，每一上述外部端子都在与外部之间的连接部分上有凸出部分，而且每一上述凸出部分都被配置为交错状(stagger)。
本发明的第8方面的课题解决方法还具备有与上述半导体集成电路芯片尚未电连的虚设端子。
本发明的第9方面的课题解决方法把多个第2方面所述的半导体器件堆叠起来并把各自的外部端子电连起来。
本发明的第10方面的课题解决方法还具备有用于把多个第2方面所述的半导体器件连接起来的框架。
本发明的第11方面的课题解决方法具有下述工序：在与连接板同一平面上准备外部端子的工序；把半导体集成电路芯片设置到上述连接板的表面上并进行电连的工序；电连上述半导体集成电路芯片和上述外部端子的工序；形成半导体器件的封装主体，把上述连接板的表面一侧和与其同侧的上述外部端子的一部分覆盖起来的工序；把上述外部端子沿着上述封装主体一直弯曲到该封装主体的表面一侧的工序。
倘采用本发明的第1方面的发明，由于连接板的另一侧的主面从封装主体中露了出来，故具有可以改善散热性的效果。
倘采用本发明的第2方面的发明，则借助于已把连接板和连接到外部端子的外部的连接部分形成于同一平面上故可实现半导体器件的薄型化，由于外部端子被形成为从与连接板的另一侧的主面相同的平面一直到与该另一侧的主面相反一侧的封装主体的表面一侧，故具有可使半导体器件多层化的效果。
倘采用本发明的第3方面的发明，则具有可以防止外部端子弯曲封装主体的外侧方向且在把连接材料供给到与外部端子的外部之间的连接部分上时可以采用通常的网板印刷法的效果。
倘采用本发明的第4方面的发明，则具有可以防止连接材料在与外部的基板连接时流入连接板与外部端子之间的间隙中去的效果。
倘采用本发明的第5方面的发明，则由于已在外部端子上形成了用于进行与外部的基板等连接的连接材料，故具有在装配时不用供给连接材料就可以进行与外部的基板等的连接的效果。
倘采用本发明的第6方面的发明，则由于外部端子在与外部之间的连接部分上有凸出部分故具有可以吸收装配时的半导体器件的偏移并可在装配时得到充分的连接材料的连接性的效果。
倘采用本发明的第7方面的发明，由于把凸出部分设置为交错(stagger)状，故具有使一侧的外部端子的凸出部分与另一侧的相邻外部端子之间的距离变宽，从而可以改善焊锡的桥接的效果。
倘采用本发明的第8方面的发明，则在已把具有虚设端子的第2方面的发明所述的半导体器件多层化了的情况下，具有可以防止本来尚未连接的外部端子彼此之间电连的效果。
倘采用本发明的第9方面的发明，由于把第2方面的发明所述的半导体器件多个堆叠而多层化，故可以减小装配面积且可实现高密度装配化和大容量化。
倘采用本发明的第10方面的发明，则由于用框架进行连接。故具有抑制多层时的半导体器件的位置偏离的效果。
倘采用本发明的第11方面的发明，则具有可以得到第2方面的发明所述的半导体器件。
下边简单说明附图。
图1是本发明的实施形态1的半导体器件的断面图。
图2示出了本发明的实施形态1的半导体器件的制造方法。
图3示出了本发明的实施形态1的半导体器件的制造方法。
图4示出了本发明的实施形态1的半导体器件的制造方法。
图5示出了本发明的实施形态1的半导体器件的制造方法。
图6是本发明的实施形态2的半导体器件的断面图。
图7是本发明的实施形态3的半导体器件的断面图。
图8是本发明的实施形态4的半导体器件的断面图。
图9是本发明的实施形态5的半导体器件的断面图。
图10是本发明的实施形态6的半导体器件的断面图和进行与基板等之间的外部连接的外部引线的连接部分的放大图。
图11是本发明的实施形态7的半导体器件的断面图和进行与基板等之间的外部连接的外部引线的连接部分的放大图。
图12是本发明的实施形态8的半导体器件的多层装配时的断面图。
图13是本发明的实施形态9的半导体器件的多层装配时的断面图。
图14的示意图给出了在本发明的半导体器件的多层装配时，用分配印刷法向半导体器件供给焊锡的方法。
图15的示意图给出了在本发明的半导体器件的多层装配时，用网板印刷法向半导体器件供给焊锡的方法。
图16的示意图给出了在本发明的半导体器件的多层装配时，用电镀法向半导体器件供给焊锡的方法。
图17是用于说明本发明的半导体器件的虚设引线的平面图。
图18是现有的半导体器件的断面图。
实施形态
实施形态1
图1是本发明的实施形态1的半导体器件的断面图。在该图中，1是IC(半导体集成电路)芯片、2是金丝、3b是作为要搭载IC芯片1的连接板的芯片焊盘、4b是介以金丝2和IC芯片1电连并进行与基板等之间的外部连接的外部引线(外部端子)、5b是作为IC封装主体的铸模树脂。
其次，对本实施形态中的半导体器件的构成进行说明。IC芯片1被连接到芯片焊盘3b上。铸模树脂5b把IC芯片1、金丝2和芯片焊盘3b覆盖起来。但是，芯片焊盘的背面(图的下侧)从铸模树脂中露出来。外部引线4b介以金丝2与IC芯片电连、并形成为从与芯片焊盘3b之间的同一平面沿着铸模树脂5b的侧壁一直到与芯片焊盘3b相反一侧的铸模树脂5b的表面一侧(图的上侧)的形状。另外，在与外部的基板(没有画出来)之类之间进行装配时，外部引线4b连接到该外部基板等等上。
其次对示于图1的半导体器件的制造方法进行说明。首先参看图2，在与芯片焊盘3b同一平面上准备外部引线4b，并把IC芯片1连到芯片焊盘3b的表面(图中上侧)上(粘芯片)。接着，参看图3，形成使IC芯片1与外部引线4b电连的金丝2(金丝压焊)。其次参看图4，形成把芯片焊盘3b的表面一侧和芯片焊盘3b的表面一侧的外部引线4b的一部分盖起来的铸模树脂5b(铸模形成)使得把IC芯片1和金丝2盖起来。其次参看图5，把外部引线4b切断成必要的长度(切引线)。接着，沿着铸模树脂5b弯曲外部引线4b，使外部引线4b存在于从芯片焊盘3b的背面到其相反一侧的铸模树脂5b的表面一侧(弯引线)，这样，示于图2的半导体器件就完成了。
倘采用本实施形态的半导体器件，则有下述①～③的效果。①由于在同一平面上形成芯片焊盘3b和把外部引线4b连到外部的基板等等上去的连接部分，故可以实现半导体器件的薄型化；②由于使芯片焊盘3b从铸模树脂5b中露出来，故可以改善散热性；③由于使外部引线4b沿着铸模树脂5b在半导体器件的上下(铸模树脂5b的表面一侧和芯片焊盘的外露一侧)，故可使半导体器件多层化。
实施形态2
图6是本发明的实施形态2的半导体器件的断面图。在图6中，5c是作为IC封装主体的铸模树脂，其他的标号与图1中的标号相对应。
其次对本实施形态中的半导体器件的构成进行说明。把外部引线4b的在铸模树脂5c的表面一侧(图中上侧)上形成的部分构成为与铸模树脂5c的表面为同一平面。其余的构成与实施形态1的半导体器件的构成相同。在图6的半导体器件的铸模树脂5c的表面一侧，例如如后边要讲的实施形态8所示，用焊锡之类的连接材料把本发明的半导体器件连接上去。
倘采用本实施形态的半导体器件，则除了上述①～③的效果之外，由于把外部引线4b在铸模树脂5c的表面一侧上形成的部分作成为与铸模树脂5c的表面为同一平面，故可以防止引线弯曲(外部引线4b弯向铸模树脂5c的外侧方向)，且在供给焊锡之类的连接材料时可以采用通常的网板印刷法。
实施形态3
图7是本发明的实施形态3的半导体器件的断面图。在图7中，6是作为保护材料的铸模树脂，它把芯片焊盘3b的外露面一侧的外部引线4b的与外部的基板等等(未画出)之间的连接部分之外的部分覆盖起来。其他的标号与图1中的标号相对应。
其次对本实施形态中的半导体器件的构成进行说明。外部引线4b之内，除去与外部基板等(未画出)相连接部分之外的部分用铸模树脂6盖了起来。其余的构成与实施形态1的构成一样。特别是在图7所示的半导体器件中，示出的是在外部引线4b的与外部基板等的连接部分之外的部分之内，把存在于芯片焊盘3b的外露面一侧的外部引线4b与芯片焊盘3b之间的间隙用铸模树脂6盖起来的情况。
倘采用本实施形态的半导体器件，则除了上述①～③之外，还由于已用铸模树脂6把外部引线4b的与外部的基板等之间的连接部分之外的部分盖了起来，故可以防止用于把外部的基板等与外部引线4b之间连接起来的焊锡之类的连接材料流入到芯片焊盘3b与外部引线4b之间的间隙中去。
实施形态4
图8是本发明的实施形态4的半导体器件的断面图。在图8中，7是作为保护材料的阻焊剂，用于把芯片焊盘3b的外露面一侧的外部引线4b的与外部的基板等之间的连接部分以外的部分覆盖起来，其余的标号与图1中的标号对应。
其次对本实施形态中的半导体器件的构成进行说明。外部引线4b之内，把与外部的基板等等(未画出)之间的连接部分以外的部分用阻焊剂盖了起来。除此之外的构成与实施形态1的半导体器件的构成一样。特别是在示于图8的半导体器件中，示出的是把在外部引线4b的与外部的基板等等之间的连接部分以外的部分之内，存在于芯片焊盘3b的外露面一侧的外部引线4b与芯片焊盘3b之间的间隙用阻焊剂盖起来的情况。
倘采用本实施形态的半导体器件，则除了上述①～③之外，由于已用阻焊剂7把外部引线4b的与外部的基板等之间的连接部分以外的部分盖了起来。故可以防止用于把外部引线4b与外部的基板等等之间连接起来的焊锡之类的连接材料流入到芯片焊盘3b与外部引线4b之间的间隙中去。
实施形态5
图9是本发明的实施形态5的半导体器件的断面图。在图9中，8是作为用于与外部的基板等等进行连接的连接材料的焊锡球，其余的标号与图1中的标号相对应。
其次对本实施形态中的半导体器件的构成进行说明。这是一种在外部引线4b的与外部的基板等之间的连接部分上形成了焊锡球8的构成。除此之外的构成与实施形态1的半导体器件的构成一样。特别是示于图9的半导体器件的焊锡球形成于外部引线4b的芯片焊盘3b的外露面一侧。
倘采用本实施形态的半导体器件，则除了上述①～③之外，由于在外部引线4b上已形成了用于与外部的基板等进行连接的焊锡球8，故在装配时无需供给焊锡就可以进行与外部的基板等等之间的连接。
实施形态6
图10是本发明的实施形态6的半导体器件的外部引线4b的放大图。在图10中，4c是是设于外部引线4b的与外部的基板等之间的连接部分上的凸出部分，除此之外的标号与图1中的标号相对应。
其次对本实施形态中的半导体器件的构成进行说明。这是一种在外部引线4b的与外部之间的连接部分上有凸出部分的构成。除此之外的构成与实施形态1的半导体器件的构成一样。特别是图10所示的半导体器件的外部引线4b，在铸模树脂5b的表面一侧(图中上侧)和芯片焊盘3b的外露面一侧上，在各自的外部引线4b的与外部的基板等之间的连接部分上有凸出部分4c。
倘采用本实施形态的半导体器件，则除去上述①～③之外，还要加上④由于外部引线4b在与外部之间的连接部分上有凸出部分4c，故可以吸收装配时的半导体器件偏离且可以得到装配时充分的焊锡连续性。
实施形态7
图11是本发明的实施形态7的半导体器件的外部引线4b的放大图。在图11中，4d是设于外部引线4b的与外部的基板等的连接部分上的凸出部分，除此之外的标号与图1中的标号相对应。
其次对本实施形态中的半导体器件的构成进行说明。这是一种外部引线4b的与外部之间的连接部分有凸出部分4d且相邻的外部引线4b的凸出部分4d形成为相互配置不相同的交错状的构成。此外的构成与实施形态1的半导体器件的构成相同。特别是示于图11的半导体器件的外部引线4b，在铸模树脂5b的表面一侧(图中上侧)和芯片焊盘3b的外露面一侧，在各自的外部引线4b的与外部的基板等之间的连接部分上有交错状地配置的凸出部分4d。
倘采用本实施形态的半导体器件，则除去上述①～③之外，还要加上④由于已把相邻的外部引线4b的凸出部分4d配置为交错状，故一侧的外部引线4b的凸出部分4d与另一侧的外部引线4b之间的距离变宽，故可以改善焊锡之类的连接材料的桥接。
实施形态8
图12是一断面图，它示出了本发明的实施形态8的半导体器件，且示出的是把图1的半导体器件半导体器件多层地重叠起来并装到了基板上的情况。在图12中，9是用于把已重叠成多层半导体器件的半导体彼此之间物理性地、电气性地连接起来的焊锡，10是外部的基板，除此之外的标号与图1中的标号相对应。
其次对本实施形态中的半导体器件的构成进行说明。如图12所示，这是一种把多个图1中的半导体器件用焊锡9把各自的外部引线4b彼此之间进行物理的、电气的连接，使半导体器件上下式地重叠成多层化的构成。此外，除去图1中的半导体器件之外，也可使图6～图11的半导体器件半导体器件多层化。此外，也可把图6～图11的若干种半导体器件组合起来形成多层化。
倘采用本实施形态的半导体器件，则借助于多层化可以缩小装配面积且可大容量化。
实施形态9
图13是本发明的实施形态9的半导体器件的断面图，示出的是把图1的半导体器件堆叠成多层而装配在基板上的情况。在图12中，10是基板，11是连接半导体器件的引线框架，除此之外的标号与图1中的标号相对应。
其次对图13的半导体器件的构成进行说明。如图13所示，这是一种采用把多个图1中所示的半导体器件，用引线框架11把各自的外部引线4b彼此之间进行物理的和电气的连接的办法把半导体器件上下地堆叠起来形成多层化的构成。另外，除去图1的半导体器件之外，也可使图6～图11的半导体器件多层化。另外，也可以把图1～图11的若干种半导体器件组合起来多层化。
倘采用本实施形态的半导体器件，由于多层化，故可以缩小装配面积且可以大容量化。此外，采用引线框架11进行连接。故可以抑制多层时的半导体器件的位置偏离。
作为用于把本发明的半导体器件堆叠成多层时的连接的焊锡的供给方法，可以使用图14所示的那种应用分配器12来供给焊锡的分配法，用图15所示的那种涂刷器(スキ一ジ)13a介以掩模13c供给焊锡13b的网板印刷法，和图16所示的在与外部之间的连接部分上形成焊锡镀层14的电镀法。
此外，如实施形态8，9所示，在把半导体器件作成多层化的情况下，把物理上配置在相同位置上的外部引线彼此之间进行物理的和电气的连接。但是，因外部引线的不同，有时候不进行电连(令这种外部引线为4e，4f)。图17中示出了防止这种情况的实施形态1～实施形态7的半导体器件的变形例。还有，图17是从没有画出来的铸模树脂的表面方向看的图，半导体器件100，101相当于实施形态1～实施形态7的任何一个实施形态的半导体器件。半导体器件100的虚设引线(引线端子)4g与在实施形态1～7中已说明过的外部引线4b主要部分是一样的，但没有与IC芯片1a电连。半导体器件101的虚设引线(引线端子)4h也与此相同。当使半导体器件100的表面与半导体器件101的背面相向地多层化时，则虚设引线4g与外部引线4f，外部引线4e与虚设引线4h将分别物理上连接。因此外部引线4e和4f不进行电连。

Claims (11)

1.一种半导体器件，
具备：
半导体集成电路芯片；
把上述半导体集成电路芯片设置于一侧的主面上的连接板；
把上述半导体集成电路芯片，上述连接板的上述一侧的主面盖起来的半导体器件的封装主体；
上述连接板的另一侧的主面从上述封装主体中露出。
2.权利要求1所述的半导体器件，还具备有外部端子，该外部端子与上述半导体集成电路芯片电连，并形成为从与上述连接板的上述另一侧主面的同一平面一直到与该另一侧的主面相反一侧的上述封装主体的表面一侧。
3.权利要求2所述的半导体器件，上述外部端子的形成于上述封装主体的表面一侧的部分与上述封装主体的表面为同一平面。
4.权利要求2所述的半导体器件，还具备把上述外部引线之中，与外部之间的连接部分以外的部分盖起来的保护材料。
5.权利要求2所述的半导体器件，在上述外部端子的与外部之间的连接部分上还具备有用于把上述外部端子与上述外部电连起来的连接材料。
6.权利要求2所述的半导体器件，上述外部端子在与外部之间的连接部分上有凸出部分。
7.权利要求2所述的半导体器件：
上述外部端子由多个外部端子构成；
每一上述外部端子都在与外部之间的连接部分上有凸出部分，且每一个上述凸出部分都被配置成交错状。
8.权利要求2所述的半导体器件，还具备有与上述半导体集成电路芯片未进行电连的虚设端子。
9.一种半导体器件，它把多个权利要求2的半导体器件堆叠起来，并把各自的上述外部端子电连起来。
10.权利要求9所述的半导体器件，还具备有用于把多个权利要求2所述的半导体器件连接起来的框架。
11.一种半导体器件的制造方法，
具备下述工序：
在与连接板同一平面上准备外部端子的工序；
把半导体集成电路芯片设置于上述连接板的表面上并进行电连的工序；
把上述半导体集成电路芯片与上述外部端子电连的工序；
形成把上述连接板的表面一侧以及与之处于相同一侧的上述外部端子的一部分盖起来的半导体器件的封装主体的工序；
把上述外部端子沿着上述封装主体一直弯到该封装主体的表面一侧的工序。
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