CN1178280C - 处理绝缘层的方法 - Google Patents

处理绝缘层的方法 Download PDF

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CN1178280C
CN1178280C CNB008002231A CN00800223A CN1178280C CN 1178280 C CN1178280 C CN 1178280C CN B008002231 A CNB008002231 A CN B008002231A CN 00800223 A CN00800223 A CN 00800223A CN 1178280 C CN1178280 C CN 1178280C
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����˹�и�����ά���಼ɭ
克里斯托弗·戴维·多布森
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Abstract

本发明涉及一种加热例如半导体器件中的绝缘层的方法,其中透过一层抗蚀剂蚀刻形成物,包括反应蚀刻抗蚀剂,防止吸收或除去蚀刻形成物的裸露表面上的水蒸气和/或氧气,在没有上述水蒸气和/或氧气的情况下用导电金属填充形成物。

Description

处理绝缘层的方法
本发明涉及一种处理例如使用在半导体器件中的绝缘层的方法。
当半导体设计者将半导体内的器件越来越紧凑地安装在一起时,在连接金属线路之间形成的绝缘层的介电常数就变得更加重要。因此生产出介电常数(k)越来越低的绝缘材料就成为今后发展的趋势。一种制成这种材料的方法是将碳添加进绝缘材料中,我们正在进行的国际专利申请PCT/GB97/02240对这种方法进行了描述。本文将对该发明中的公开内容作概括说明。
为了形成被绝缘层分割开的金属线路,或者将这些线路与其他在半导体内形成的线路或器件相连接,其中,上述绝缘层沉积在半导体材料上,必须对绝缘层进行蚀刻或完全蚀刻,随后将导电金属填充进侵蚀后的凹槽中。一般通过将绝缘层的上表面涂上光致抗蚀剂,利用光刻法除去抗蚀剂的特定部分,再浸蚀抗蚀剂中裸露的开口从而形成凹槽,随后利用氧气通过反应蚀刻来除去抗蚀剂层,这样就形成了上述的凹槽。
然而却发现在含碳的绝缘层中,介电常数由于反应氧气蚀刻而提高,形成物中的侧壁被蚀刻会产生凸度,同时当把金属填充进凹槽时,还会产生一系列问题。
一方面,本发明包括一种处理含碳有机绝缘层的方法,该方法包括:通过一层抗蚀剂将含碳有机绝缘层蚀刻成一形成物;将反应蚀刻气体供应到含有上述抗蚀剂和形成物的室中,使上述反应蚀刻气体与上述抗蚀剂和形成物反应;将上述反应蚀刻气体、氢气和/或氮气供应到上述室中,以除去抗蚀剂,并由此防止在上述形成物裸露表面上吸收水蒸气和/或氧气;在没有上述水蒸气和/或氧气的情况下将导电金属填充进上述形成物中。
防止吸收的步骤可以包括给氢供蚀刻气体(如氧气)或给蚀刻气体供氢,并且或者可以包括给氮供蚀刻气体或给蚀刻气体供氮。更好的防止步骤包括给蚀刻气体供一种气体或给该气体供蚀刻气体,该气体是反应氢和/或氮的来源,在实施例中,该气体可以是NH3,蚀刻气体为氧气,氧气与该气体的比例大约为3∶1,在其它蚀刻气体的情况下,相似的比例同样合适。
在一个可替换的布置中,防止步骤可以这样实现:通过在真空环境下维持基底直至完成金属喷镀或者还可以增加一包括在金属喷镀之前加热绝缘层以排出绝缘层材料中的气体的去除步骤。
优选地,绝缘层的介电常数小于4并且/或者绝缘层包含碳。更具体地,介电常数小于3.5,最好小于3.0。
介质层中的碳浓度最好大于10%。
本发明尽管已由上文所限,但它仍应理解为包括上述或以下描述的步骤的任何创造性组合。
本发明可以用许多方式来实现,以下参照附图,结合实施例对本发明进行描述,附图中:
图1为使用本发明方法的装置的垂直截面图;
图2为一个具有若干个使用已有技术填充的凹槽的绝缘层的视图;
图3为图2中这些凹槽的放大图;
图4为利用本发明方法填充的凹槽的视图;
图5为单个凹槽的放大图。
如图1所示,真空室10包括一支撑薄膜的薄膜基底11,薄膜正对着等离子源12,反应气体通过气体进口13能从等离子源流出来。加热灯14用于加热薄膜16,室内可以通过高压真空阀15抽成真空。等离子区是由等离子管中的薄膜通过一高频线圈17远程产生的。
为了蚀刻绝缘层,薄膜16安装在基底11上,在已有技术中,氧气通过等离子管12流入室内,在薄膜16上通过反应蚀刻光致抗蚀剂,这一点前文已经进行了描述。
接下来的实验是这样进行的:
为了除去光致抗蚀剂和剥去抗反射涂层材料,在开始进行上述方法时仅使用氧气,随后使用一包括氨的混合气体。
适用于下列条件:
仅使用氧气的过程(传统去除抗蚀剂)
150mm薄膜,使用1千瓦的灯
    步骤1     步骤2
    气体流量     496sccm氧气     496sccm氧气
    压力     750mT     750mT
    等离子强度     500W ICP     500W ICP
    灯式加热器     80%灯的强度     45%灯的强度
    进行时间     60sec’s     120sec’s
包含氨的过程(本发明实施例)
150mm薄膜,使用1千瓦的灯
    步骤1     步骤2
    气体流量     496sccm氧气50sccm氮气150sccm氨     496sccm氧气50sccm氮气150sccm氨
    压力     750mT     750mT
    等离子强度     500W ICP     500W ICP
    灯式加热器     80%灯的强度     45%灯的强度
    进行时间     40sec’s     90sec’s
(ICP:电感耦合等离子体)
基底的实际温度并未测量,但估计在250摄氏度左右。
随后为了用绝缘层/接触层和铝给凹槽喷镀,进行如下过程:
预热:1.5千瓦,5分钟
绝缘层沉积 Ti/TiN 200℃下沉积300A/700A
铝合金沉积 Al/0.5%Cu 450℃下沉积1微米
Forcefill 440℃,1分钟 1200巴 进气孔压力720巴 室内压力
(Forcefill是我们的欧洲专利申请No.92304633.8和美国专利5527861中描述的金属喷镀过程的注册商标。)
使用上述金属喷镀方法,在用氨去除抗蚀剂过程中100%的凹槽被填满,而在仅有氧气去除抗蚀剂过程中70%的凹槽被填满。同样可获知在绝缘层/接触层后使用的商业用钨填入物会因为当绝缘层含有碳时被填充的凹槽不可靠而遭受损害,同时根据本发明,实施一般的去除抗蚀剂方法无需进一步过程。
图2、图3、图4和图5分别是仅用氧气和使用混合气体的方法下的扫描电子显微照片。在这些扫描电子照片中,亮区代表空隙,由此可看出传统金属喷镀方法很不成功。相反,混合气体方法却提供了很好的金属喷镀效果。
标准的氧气等离子去除抗蚀剂过程为何会产生金属喷镀问题尚未被完全理解,而且为何引入氨会解决这个问题同样未被完全理解。然而,这个问题却为那些意图使低K值的绝缘材料,特别是碳低于10%的绝缘材料整合在一起的人们所熟悉。在氧气反应蚀刻法中除去碳而使形成物的裸露表面易于受到例如有在随后的大气暴露中吸收的水蒸气的侵袭和污染是可能发生的。这种暴露一般是因为光致抗蚀剂去除区和金属喷镀区被制造成独立的单元而发生的。然而,如果这个分析是正确的,可以设想以上见到的好处同样可以通过如下方式获得:进行显著加热,例如在真空下,在金属喷镀前使绝缘层中的气体得以除去,或者在真空环境中,在去除抗蚀剂过程和完成金属喷镀过程之间保留薄膜。预热的方案由于热量预算的原因和低的生产量而无法批量生产。
假设因为氨中的氢通过与游离硅的键相结合而替换了被氧去除的碳,所以将氨引入氧气中可以克服仅用氧气时的方法存在问题。这种氢替换被去除的碳从而稳定了绝缘材料的结构,防止了随后的水蒸汽和吸收。此外或者可替代地,在碳的替换过程中,氮可以替换碳或者在氢和氮之间也许仍有目前未知的相互作用。
此外或者可替代地,氢和/或氮的存在会抑制氧气对碳的替换。
尽管这曾经是一个不太具有吸引力的解决方案,但在金属喷镀之前分别进行氢/氮的处理步骤是可行的。

Claims (13)

1.一种处理含碳有机绝缘层的方法,该方法包括:
通过一层抗蚀剂将含碳有机绝缘层蚀刻成一形成物;
将反应蚀刻气体供应到含有上述抗蚀剂和形成物的室中,使上述反应蚀刻气体与上述抗蚀剂和形成物反应;
将上述反应蚀刻气体、氢气和/或氮气供应到上述室中,以除去抗蚀剂,并由此防止在上述形成物裸露表面上吸收水蒸气和/或氧气;
在没有上述水蒸气和/或氧气的情况下将导电金属填充进上述形成物中。
2.按照权利要求1所述的方法,其特征在于,上述氢气与反应蚀刻气体混合在一起供应。
3.按照权利要求1所述的方法,其特征在于,上述氢气独立于反应蚀刻气体分别供应。
4.按照权利要求1所述的方法,其特征在于,上述防止的步骤包括把反应蚀刻气体供应给作为反应氢气源的气体。
5.按照权利要求4所述的方法,其特征在于,上述源气体为氨气。
6.按照权利要求4所述的方法,其特征在于,上述反应蚀刻气体包括氧气,其中,氧气与上述源气体的比例为3∶1。
7.按照权利要求1所述的方法,其特征在于,上述氮气与反应蚀刻气体混合在一起供应。
8.按照权利要求1所述的方法,其特征在于,上述氮气独立于反应蚀刻气体分别供应。
9.按照权利要求1所述的方法,其特征在于,所述防止的步骤包括把反应蚀刻气体供应给作为反应氮气源的气体。
10.按照权利要求9所述的方法,其特征在于,上述反应蚀刻气体包括氧气,其中,氧气与上述源气体的比例为3∶1。
11.按照上述权利要求1-10任一所述的方法,其特征在于,还包括在用导电金属填充蚀刻的形成物之前加热绝缘层。
12.按照上述权利要求1-10任一所述的方法,其特征在于,还包括在真空条件下保持绝缘层直至蚀刻的形成物被填充有导电金属。
13.按照上述权利要求1-10任一所述的方法,其特征在于,上述绝缘层的介电常数小于4。
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Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB9904427D0 (en) * 1999-02-26 1999-04-21 Trikon Holdings Ltd Method treating an insulating layer
US6933246B2 (en) * 2002-06-14 2005-08-23 Trikon Technologies Limited Dielectric film
US7344991B2 (en) 2002-12-23 2008-03-18 Tokyo Electron Limited Method and apparatus for multilayer photoresist dry development
CN100521088C (zh) * 2002-12-23 2009-07-29 东京毅力科创株式会社 双层光刻胶干法显影的方法和装置
JP4594235B2 (ja) 2002-12-23 2010-12-08 東京エレクトロン株式会社 Arc層をエッチングする方法
US8048325B2 (en) 2003-03-31 2011-11-01 Tokyo Electron Limited Method and apparatus for multilayer photoresist dry development
EP1609175A1 (en) * 2003-03-31 2005-12-28 Tokyo Electron Limited Method and apparatus for multilayer photoresist dry development
US7598176B2 (en) * 2004-09-23 2009-10-06 Taiwan Semiconductor Manufacturing Co. Ltd. Method for photoresist stripping and treatment of low-k dielectric material
US20090078675A1 (en) * 2007-09-26 2009-03-26 Silverbrook Research Pty Ltd Method of removing photoresist

Family Cites Families (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3985597A (en) 1975-05-01 1976-10-12 International Business Machines Corporation Process for forming passivated metal interconnection system with a planar surface
JPS63127551A (ja) 1986-11-17 1988-05-31 Toshiba Corp 半導体装置の製造方法
US5254213A (en) 1989-10-25 1993-10-19 Matsushita Electric Industrial Co., Ltd. Method of forming contact windows
CA2032763C (en) 1990-12-20 2001-08-21 Mitel Corporation Prevention of via poisoning by glow discharge induced desorption
JP3351802B2 (ja) 1991-01-01 2002-12-03 忠弘 大見 薄膜形成装置
AU3726593A (en) 1992-02-26 1993-09-13 Materials Research Corporation Ammonia plasma treatment of silicide contact surfaces in semiconductor devices
US5643407A (en) * 1994-09-30 1997-07-01 Taiwan Semiconductor Manufacturing Company, Ltd. Solving the poison via problem by adding N2 plasma treatment after via etching
EP0720223B1 (en) * 1994-12-30 2003-03-26 STMicroelectronics S.r.l. Process for the production of a semiconductor device having better interface adhesion between dielectric layers
JPH10125782A (ja) 1996-10-15 1998-05-15 Sony Corp 半導体装置の製造方法
US5935334A (en) * 1996-11-13 1999-08-10 Applied Materials, Inc. Substrate processing apparatus with bottom-mounted remote plasma system
JPH10214892A (ja) 1997-01-30 1998-08-11 Sony Corp 半導体装置の製造方法
US6351039B1 (en) * 1997-05-28 2002-02-26 Texas Instruments Incorporated Integrated circuit dielectric and method
JP3226021B2 (ja) 1997-09-02 2001-11-05 日本電気株式会社 半導体装置の製造方法
US5866945A (en) 1997-10-16 1999-02-02 Advanced Micro Devices Borderless vias with HSQ gap filled patterned metal layers
US5958798A (en) 1997-12-18 1999-09-28 Advanced Micro Devices, Inc. Borderless vias without degradation of HSQ gap fill layers
US6114250A (en) 1998-08-17 2000-09-05 Lam Research Corporation Techniques for etching a low capacitance dielectric layer on a substrate
US6696366B1 (en) 1998-08-17 2004-02-24 Lam Research Corporation Technique for etching a low capacitance dielectric layer
US6168726B1 (en) * 1998-11-25 2001-01-02 Applied Materials, Inc. Etching an oxidized organo-silane film
US6361837B2 (en) * 1999-01-15 2002-03-26 Advanced Micro Devices, Inc. Method and system for modifying and densifying a porous film
GB9904427D0 (en) * 1999-02-26 1999-04-21 Trikon Holdings Ltd Method treating an insulating layer
US6114259A (en) * 1999-07-27 2000-09-05 Lsi Logic Corporation Process for treating exposed surfaces of a low dielectric constant carbon doped silicon oxide dielectric material to protect the material from damage
US7029826B2 (en) 2000-06-23 2006-04-18 Honeywell International Inc. Method to restore hydrophobicity in dielectric films and materials
EP1195801B1 (en) 2000-09-29 2014-01-29 Imec Process for plasma treating an isolation layer with low permittivity

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