CN1184335A - Semiconductor device and method for forming metal interconnection in semiconductor device - Google Patents
Semiconductor device and method for forming metal interconnection in semiconductor device Download PDFInfo
- Publication number
- CN1184335A CN1184335A CN97122986A CN97122986A CN1184335A CN 1184335 A CN1184335 A CN 1184335A CN 97122986 A CN97122986 A CN 97122986A CN 97122986 A CN97122986 A CN 97122986A CN 1184335 A CN1184335 A CN 1184335A
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- CN
- China
- Prior art keywords
- tungsten
- layer
- tungsten layer
- semiconductor device
- contact hole
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- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
Abstract
A semiconductor device includes: a semiconductor substrate which is equipped with an insulation layer; a contact hole which forms in the insulation layer; a first tungsten layer for burying the contact hole and is equipped with adulterants for reducing the resistance rate; a second tungsten layer for covering the first tungsten layer and is equipped with adulterants for reducing the resistance rate. The invention also relates to the manufacturing method of the semiconductor device. Metal interconnect of the invention adopts double layers of tungsten layer. And through the adulterants, the resistance rate of the tungsten layer is lowered, and the speed of the device is improved. Compared with the method of forming a tungsten plug first and then forming an aluminum layer, the manufacturing process of the invention is also simplified.
Description
The present invention relates to a kind of semiconductor device and the method that is used to form the metal interconnecting wires of semiconductor device.
In traditional integrated circuit, generally be to adopt aluminium to connect various half guiding element devices.Semiconductor device is embedded under the insulating barrier, and the interconnection line that is used for constituting required circuit is by being arranged on realizing with the corresponding contact hole of this semiconductor device on the insulating barrier.Preferably use aluminum metal layer in the technology that forms interconnection line, this is because the resistivity of aluminium is low, and aluminium can form firm being connected with the insulating barrier of its lower floor.
But, because the densification of semiconductor device, thereby the contact hole size is reduced, and depth-width ratio (Aspect Ratio) increases.Because the difference in height covering property of aluminium is bad, in the technology that metal interconnecting wires forms, in contact hole, may be short-circuited, the reliability of device is reduced.
A kind of improved method is to use the good tungsten of difference in height covering property to replace aluminium, with the embedding material as contact hole.At this moment, generally be with SiH
4, WF
6, H
2And the chemical vapour deposition technique under the environment of Ar gas forms tungsten film.
But because the resistivity (about 6 μ Ω cm to 12 μ Ω cm) of tungsten itself is very big, so increase the time of delay of the response cycle of device, promptly the service speed of device reduces.In addition because high approximately to aluminium about 6 times to 7 times of the resistivity of tungsten, so tungsten generally is used as connector, promptly form tungsten plug after, again in the top of tungsten AM aluminum metallization, form the metal interconnecting wires of duplex, can make technology become complicated like this.
The objective of the invention is to solve above-mentioned prior art problems, metal interconnecting wires of a kind of semiconductor device and forming method thereof is provided, when using tungsten film, can form tungsten film, and can reduce the time of delay of response cycle with low-resistivity as the metal interconnecting wires of the semiconductor device of conduction.
For achieving the above object, one aspect of the present invention provides a kind of semiconductor device, comprising: the semiconductor-based end with an insulating barrier; A contact hole that is formed in the insulating barrier; First tungsten layer of a described contact hole of landfill, it has alloy to reduce its resistivity; Second tungsten layer that covers described first tungsten layer, it has alloy to reduce its resistivity.
The present invention provides a kind of method that is used to form the interconnection line of semiconductor device on the other hand, may further comprise the steps: form an insulating barrier in a basic unit; Pass described insulating barrier and form a contact hole, in described contact hole and be lower than and form one first tungsten layer under the atmosphere with boron and phosphorus of 450 ℃ of temperature; And on described first tungsten layer and be higher than and form one second tungsten layer under 450 ℃ the atmosphere with boron and phosphorus.
Metal interconnecting wires of the present invention is to adopt double-deck tungsten layer, and by doping the resistivity of tungsten layer is reduced, thereby the speed of device is improved.With respect to forming the mode that tungsten plug forms aluminium lamination again, its manufacture craft is also simplified greatly.
By the description below in conjunction with accompanying drawing, above-mentioned and other purpose, advantage of the present invention, feature can be clearer.In the accompanying drawing:
Figure 1A to 1C is the cutaway view of the metal interconnecting line forming method of expression semiconductor device of the present invention;
Fig. 2 is expressed as the schematic diagram of realizing the chemical vapor depsotition equipment that method of the present invention adopted;
Fig. 3 is the schematic diagram of expression tungsten interconnection line forming process of the present invention.
Hereinafter with reference to accompanying drawing the preferred embodiments of the present invention are described.Should be noted that structure shown in the drawings is the form of simplifying.Actual device architecture and interconnection line will comprise a lot of structures shown in the drawings in same substrate.
At first with reference to Figure 1A-1C, it represents a preferred embodiment of the method for interconnection line formed according to the present invention.Figure 1A shows a contact hole 11 that will form interconnection line thereon.Above-mentioned contact hole passes an insulating barrier 12 and forms, and this insulating barrier can be formed in the substrate (for example silicon base) 10.Can be formed with a lot of devices in the substrate 10.Here, insulating barrier 12 silicon dioxide preferably.Contact hole 11 is to adopt traditional photoetching and corrosion technology to be formed in the insulating barrier 12.Then, adopt traditional titanium depositing operation to deposit a titanium layer 13, it covers the part that expose in hole 11 that is touched of insulating barrier 12 and substrate 10 equably.The titanium depositing operation can adopt for example physics or chemical gas phase sedimentation.Adopt traditional titanium depositing operation, for example physics or chemical vapour deposition technique deposit titanium nitride layer 14 on titanium layer 13.After titanium nitride layer 14 deposition, carry out annealing process thereupon, rapid thermal annealing (RTA---rapid thermalannealing) for example, general temperature range is at 500 ℃ to 700 ℃.Titanium nitride layer 14 provides a protection barrier layer for titanium layer 13 during chemical vapour deposition (CVD) tungsten, and helps the formation of tungsten contact hole.
Shown in Figure 1B, contact hole 11 is by the landfill first tungsten layer 15a, and it covers whole titanium nitride layer 14.The first tungsten layer 15a is optionally formed by chemical vapour deposition technique, in order to optionally to form tungsten plug.The second tungsten layer 15b is formed on the first tungsten layer 15a.The second tungsten layer 15b that is formed by chemical vapour deposition technique is used for forming the interconnection line of tungsten.The depositing temperature of the first tungsten layer 15a is preferably lower than 450 ℃, and the depositing temperature of the second tungsten layer 15b preferably is higher than 450 ℃, so that obtain low resistance and low stress.
In above-mentioned chemical vapor deposition method, the surface that tungsten is deposited on substrate comprises to be put into substrate CVD (Chemical Vapor Deposition) chamber and heats the process of substrate.The deposition process of tungsten will be utilized SiH
4, WF
6With vector gas such as H
2Or the mixture of Ar.In order to reduce the resistivity of tungsten layer 15a and 15b, with B
2H
6And PH
3Gas adds above-mentioned SiH
4, WF
6In the mist of vector gas.Because boron and the even distribution of phosphorus in tungsten layer make the resistivity of tungsten layer reduce half, promptly are lower than about 6 μ Ω cm.
Fig. 2 schematically shows the apparatus structure of realizing above-mentioned technology.Wafer 22 is put into deposition chamber 20, is placed on the pedestal 21 of a heating.To be mixed with B by a water-cooled injector head 23
2H
6And PH
3Reacting gas SiH
4, WF
6With vector gas such as H
2Or Ar feeds in the deposition chamber 20.
Fig. 3 represents to form with method of the present invention the schematic diagram of the process of tungsten interconnection line.As shown in Figure 3, after wafer 22 enters loading and unloading closed chambers (load lock chamber) 31, enter one first settling chamber 33, and the first tungsten layer 15a in the contact hole forms in the depositing temperature deposit that is lower than 450 ℃ by a surge chamber 32.Then, wafer 22 has deposited after first tungsten layer, enters one second settling chamber 34 by surge chamber 32, and second tungsten layer on the first tungsten layer 15a is being higher than 450 ℃ of not temperature deposit formation.Then, the wafer 22 that has deposited the second tungsten layer 15b is got back to loading and unloading closed chamber 31 by surge chamber 32 again.
At last, shown in Fig. 1 C, owing in the photoetching process that is used to form metal interconnecting wires scattering taking place, so can on the second tungsten layer 15b, deposit a titanium nitride layer 16 as the anti-scatter layer.
Below only described the present invention, but the invention is not restricted to the foregoing description in conjunction with a preferred embodiment.Protection scope of the present invention should claims and equivalence change and limit.
Claims (9)
1. semiconductor device comprises:
Semiconductor-based end with an insulating barrier;
A contact hole that is formed in the insulating barrier;
First tungsten layer of a described contact hole of landfill, it has alloy to reduce its resistivity;
Second tungsten layer that covers described first tungsten layer, it has alloy to reduce its resistivity.
2. device according to claim 1 wherein has a metal barrier between described insulating barrier and described first tungsten layer.
3. device according to claim 1, wherein, the surface of described second tungsten layer has an anti-scatter layer.
4. device according to claim 1, wherein, the alloy of described first and second tungsten layers comprises boron and phosphorus.
5. device according to claim 1, wherein, the atmosphere that forms described first and second tungsten layers comprises B
2H
6And PH
3
6. method that is used to form the interconnection line of semiconductor device may further comprise the steps:
In a substrate, form an insulating barrier;
Pass described insulating barrier and form a contact hole, in described contact hole and be lower than and form one first tungsten layer under the atmosphere with boron and phosphorus of 450 ℃ of temperature; And
On described first tungsten layer and be higher than and form one second tungsten layer under 450 ℃ the atmosphere with boron and phosphorus.
7. method according to claim 6 wherein, also comprised the step that forms a metal barrier and annealed in described barrier layer before forming described first tungsten layer.
8. method according to claim 6 wherein, is formed with an anti-scatter layer on described second tungsten layer.
9. method according to claim 6, wherein, the step that forms described first and second tungsten layers is to have B
2H
6And PH
3Atmosphere under carry out.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019960059024A KR100255516B1 (en) | 1996-11-28 | 1996-11-28 | A metal wire of semiconductor device and forming method thereof |
| KR59024/96 | 1996-11-28 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1184335A true CN1184335A (en) | 1998-06-10 |
| CN1096117C CN1096117C (en) | 2002-12-11 |
Family
ID=19484290
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN97122986A Expired - Fee Related CN1096117C (en) | 1996-11-28 | 1997-11-28 | Semiconductor device and method for forming metal interconnection in semiconductor device |
Country Status (3)
| Country | Link |
|---|---|
| JP (1) | JPH10163132A (en) |
| KR (1) | KR100255516B1 (en) |
| CN (1) | CN1096117C (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1319164C (en) * | 2002-10-10 | 2007-05-30 | 松下电器产业株式会社 | Semiconductor device and its manufacturing method |
| CN100405610C (en) * | 2002-03-05 | 2008-07-23 | 三洋电机株式会社 | Conductor arrangement layering structure formed in contact hole, manufacturing method of conductor arrangement layering structure and display device having said conductor arrangement layering |
| CN103811411A (en) * | 2012-11-13 | 2014-05-21 | 上海华虹宏力半导体制造有限公司 | Through hole manufacturing method |
| CN107611018A (en) * | 2017-09-26 | 2018-01-19 | 上海华虹宏力半导体制造有限公司 | A kind of method and crystal circle structure for improving wafer stress |
Families Citing this family (17)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100298648B1 (en) * | 1998-12-05 | 2002-06-20 | 황 철 주 | Method for forming wiring thin film for semiconductor device |
| US9076843B2 (en) | 2001-05-22 | 2015-07-07 | Novellus Systems, Inc. | Method for producing ultra-thin tungsten layers with improved step coverage |
| JP2003332058A (en) | 2002-03-05 | 2003-11-21 | Sanyo Electric Co Ltd | Electroluminescence panel and its manufacturing method |
| CN100517422C (en) | 2002-03-07 | 2009-07-22 | 三洋电机株式会社 | Distributing structure, its manufacturing method and optical equipment |
| WO2005073987A1 (en) * | 2004-01-30 | 2005-08-11 | Greenvalley R & D Innovations Limited | A method of altering the resistivity of a metal wire |
| KR100705936B1 (en) | 2006-06-30 | 2007-04-13 | 주식회사 하이닉스반도체 | Method for forming bitline of semiconductor device |
| US20100267230A1 (en) | 2009-04-16 | 2010-10-21 | Anand Chandrashekar | Method for forming tungsten contacts and interconnects with small critical dimensions |
| US9159571B2 (en) | 2009-04-16 | 2015-10-13 | Lam Research Corporation | Tungsten deposition process using germanium-containing reducing agent |
| US10256142B2 (en) | 2009-08-04 | 2019-04-09 | Novellus Systems, Inc. | Tungsten feature fill with nucleation inhibition |
| CN113862634A (en) | 2012-03-27 | 2021-12-31 | 诺发系统公司 | Tungsten feature fill |
| US9589808B2 (en) | 2013-12-19 | 2017-03-07 | Lam Research Corporation | Method for depositing extremely low resistivity tungsten |
| US9953984B2 (en) | 2015-02-11 | 2018-04-24 | Lam Research Corporation | Tungsten for wordline applications |
| US9613818B2 (en) | 2015-05-27 | 2017-04-04 | Lam Research Corporation | Deposition of low fluorine tungsten by sequential CVD process |
| US9754824B2 (en) | 2015-05-27 | 2017-09-05 | Lam Research Corporation | Tungsten films having low fluorine content |
| US9978605B2 (en) | 2015-05-27 | 2018-05-22 | Lam Research Corporation | Method of forming low resistivity fluorine free tungsten film without nucleation |
| US11348795B2 (en) | 2017-08-14 | 2022-05-31 | Lam Research Corporation | Metal fill process for three-dimensional vertical NAND wordline |
| CN112262457A (en) | 2018-05-03 | 2021-01-22 | 朗姆研究公司 | Methods of depositing tungsten and other metals in 3D NAND structures |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4884123A (en) * | 1987-02-19 | 1989-11-28 | Advanced Micro Devices, Inc. | Contact plug and interconnect employing a barrier lining and a backfilled conductor material |
-
1996
- 1996-11-28 KR KR1019960059024A patent/KR100255516B1/en not_active IP Right Cessation
-
1997
- 1997-11-05 JP JP9303074A patent/JPH10163132A/en not_active Withdrawn
- 1997-11-28 CN CN97122986A patent/CN1096117C/en not_active Expired - Fee Related
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100405610C (en) * | 2002-03-05 | 2008-07-23 | 三洋电机株式会社 | Conductor arrangement layering structure formed in contact hole, manufacturing method of conductor arrangement layering structure and display device having said conductor arrangement layering |
| CN1319164C (en) * | 2002-10-10 | 2007-05-30 | 松下电器产业株式会社 | Semiconductor device and its manufacturing method |
| CN103811411A (en) * | 2012-11-13 | 2014-05-21 | 上海华虹宏力半导体制造有限公司 | Through hole manufacturing method |
| CN103811411B (en) * | 2012-11-13 | 2016-08-17 | 上海华虹宏力半导体制造有限公司 | The manufacture method of through hole |
| CN107611018A (en) * | 2017-09-26 | 2018-01-19 | 上海华虹宏力半导体制造有限公司 | A kind of method and crystal circle structure for improving wafer stress |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH10163132A (en) | 1998-06-19 |
| KR19980039906A (en) | 1998-08-17 |
| CN1096117C (en) | 2002-12-11 |
| KR100255516B1 (en) | 2000-05-01 |
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| SE01 | Entry into force of request for substantive examination | ||
| C06 | Publication | ||
| PB01 | Publication | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C17 | Cessation of patent right | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20021211 Termination date: 20101128 |