CN1184673C - 使用原子层沉积在基片上沉积高介电常数材料的方法 - Google Patents
使用原子层沉积在基片上沉积高介电常数材料的方法 Download PDFInfo
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Abstract
提供形成氧化铪、氧化锆以及氧化铪和氧化锆的叠层制品的方法。这些方法利用引入硝酸盐基前体,例如硝酸铪和硝酸锆的原子层沉积方法。使用这些硝酸盐基前体特别适于在氢钝化的硅表面上形成高介电常数的材料。
Description
发明背景
本发明涉及一种集成电路(IC)的制造方法,特别是在硅上形成高介电常数(k)材料的方法。
当前的Si VLSI技术使用二氧化硅作为MOS设备中的栅极介质。随着设备尺寸持续的小型化,二氧化硅层的厚度也必须降低以在栅极区和通道区之间保持相同的电容。将来预计厚度会小于2纳米(nm)。然而,通过这么薄的二氧化硅层会出现大的隧道电流,这就需要考虑其它的材料。具有高介电常数的材料可以使栅极介质层做得更薄,从而减轻隧道电流问题。本文中将这些所谓的高-k介电薄膜定义为相对于二氧化硅具有大的介电常数。典型地,二氧化硅具有约为4的介电常数,而理想的是使用介电常数约大于10的栅极介质材料。
由于高直接隧道电流的缘故,厚度小于1.5纳米的二氧化硅薄膜一般不能用作CMOS设备中的栅极介质。目前的焦点集中在寻找用引起很大注意的TiO2和Ta2O5替换SiO2。然而,高温后沉积退火和形成界面SiO2层使获得小于1.5纳米的等效SiO2厚度(也称为等效氧化物厚度(EOT))非常困难。预计约1.0纳米及更低的EOT可以用于0.07毫米设备的生产。
诸如氧化铪(HfO2)和氧化锆(ZrO2)这样的材料是高-k介电材料的主要候选物。这些材料的介电常数约为20到25,该值是二氧化硅的5-6倍,假设整个薄膜基本上由高-k材料组成,那么就意味着使用5-6纳米厚的这些材料就可以实现约1.0纳米的EOT。使用高-k材料的一个问题是:在标准加工过程中形成具有较低介电常数的二氧化硅界面层或硅酸盐层。
已经报道了用原子层沉积(ALD)和四氯化物前体沉积ZrO2或HfO2。将加热至300℃到400℃的基片交替暴露于ZrCl4或HfCl4前体与水蒸汽下,试图分别形成ZrO2或HfO2薄膜。然而,难以在氢封端的硅表面上引发沉积。氢封端的硅表面是标准工业清洗方法形成的。常被称作HF最终清洗的这些标准清洗方法典型的是以HF的快速浸渍结束。这就产生氢封端的,也被称为氢钝化的表面。随着硅表面充分暴露于反应物下,最终会引发沉积。但是,这会形成均匀性差的粗糙表面。使用四氯化物前体的另一个问题是在薄膜中引入残余的氯。氯杂质会导致长期的稳定性和性能问题。
其它前体使用与有机配位体,例如异丙醇盐,TMHD(2,2,6,6-四甲基-3,5-庚二酸盐)(heptanedionate),或与带氯的有机配位体结合的Hf或Zr金属。这些前体也存在在氢封端的硅表面上引发薄膜沉积的问题,并且会在薄膜中引入碳残余物。大的配位体还会占据足够的空间,而空间位阻会妨碍均匀的单层沉积。直到现在,已经在二氧化硅、氮氧化硅的起始层上或以介电常数下降的硅酸盐,例如ZrSiO4或HfSiO4的形式成功实现了ALD Zr和Hf氧化物。这些起始层对整个EOT有非常重要的贡献。
发明概述
因此,本发明提供一种形成高介电常数材料,ZrO2或HfO2的方法。该方法特别适合于在氢封端的硅表面上形成高介电常数材料,而且,该方法也可用于在各种基片上形成这些材料。
提供一种在基片上形成氧化锆的方法。该方法包括:在原子层沉积室内提供一半导体基片,在原子层沉积范围(regime)内将基片加热到一定温度,向沉积室中引入无水硝酸锆,用氮气清洗沉积室,并向沉积室中引入水蒸汽,从而沉积单层(monolayer)氧化锆。可以按需要重复引入无水硝酸锆,用氮气清洗沉积室和引入水蒸汽的步骤以制备所需厚度的氧化锆薄膜。
提供一种在基片上形成氧化铪的方法。该方法包括:在原子层沉积室内提供一半导体基片,在原子层沉积范围内将基片加热到一定温度,向沉积室中引入无水硝酸铪,用氮气清洗沉积室,并向沉积室中引入水蒸汽,从而沉积单层氧化铪。可以按需要重复引入无水硝酸铪,用氮气清洗沉积室和引入水蒸汽的步骤以制备所需厚度的氧化铪薄膜。
提供一种形成含氧化铪和氧化锆的纳米叠层制品的方法。该方法包括重复上述与形成氧化锆有关的步骤,重复上述与形成氧化铪有关的步骤,并按照需要交替进行这些步骤以制造纳米叠层制品,例如HfO2/ZrO2/HfO2/ZrO2。
附图简述
图1是沉积HfO2或ZrO2方法的流程图。
图2是沉积HfO2和ZrO2纳米叠层制品方法的流程图。
发明详述
图1是说明沉积HfO2或ZrO2薄膜方法步骤的流程图。步骤110在ALD室内提供半导体基片。目前商业化的ALD刀具已经能够买到。芬兰的Microchemistry有限公司(现在是ASM的一个部门)制造的ALD刀具,F120型,可以用在本文所描述的方法中。在一个优选的实施方案中,半导体基体具有氢封端的硅表面。尽管本文所描述的方法特别适合于解决在氢封端的硅表面上沉积HfO2或ZrO2的问题,但是也完全能够使用这种方法在其它表面,包括二氧化硅、氧氮化硅、SiGe表面和诸如ZrSiO4和HfSiO4这样的硅酸盐上沉积HfO2或ZrO2。
将半导体基片加热至一定温度以形成原子层沉积范围。例如,在大约160到200℃的温度下使用无水硝酸铪时,在原子层沉积范围内发现氢钝化的硅表面。
步骤120将无水硝酸铪(Hf(NO3)4)或无水硝酸锆(Zr(NO3)4)引入ALD室内。即使基片表面是氢封端的硅表面,硝酸铪或硝酸锆也会吸附到半导体基片表面上。
尽管目前无水硝酸铪和无水硝酸锆还不能买到,但这些材料的合成和提纯方法却是已知的。在1962年就报道了硝酸锆的合成。由于铪和锆之间的相似性,所以也可以通过相似的合成方法析出硝酸铪。可以这样制备硝酸铪:在30℃、五氧化二氮下回流四氯化铪,然后在100℃/0.1mmHg下通过升华提纯以获得硝酸铪。相似地,可以在95℃/0.1mmHg下提纯硝酸锆。
步骤130用氮气或例如氡、氦或氖这样的惰性气体清洗ALD室以减少或消除过多的无水硝酸铪或无水硝酸锆或不需要的反应物。
步骤140将含水气体引入ALD室。含水气体提供氢以便于去掉含硝酸盐和二氧化氮的氮气。含水气体有助于用用于形成氧化铪或氧化锆薄膜的氧原子去掉NO3形式或NO2形式的NO3配位体。含水气体可以是水蒸汽、甲醇或氢气。虽然还没有充分理解确切的化学机理,但这并不限制任何权利要求的范围。
步骤145用氮气或惰性气体清洗ALD室以减少或消除室内的含水气体或可能不需要的反应物。
步骤150说明重复步骤120、130、140和145以制备所需厚度的薄膜。用适当的清洗,通过交替暴露于硝酸盐、硝酸铪或硝酸锆和含水气体下的循环次数限制ALD方法固有的生长速率。
完成所需的循环次数后,步骤160退火该薄膜以调节薄膜和其它界面。
例如,通过将基片置于10毫托的ALD室内并将基片加热至约180℃而在具有氢封端的硅表面的硅基片上形成氧化铪薄膜。使用若干次ALD循环处理基片。每次ALD循环包括:引入无水硝酸铪,用氮气清洗并引入水蒸汽。用大约7次、13次、17次和400次循环制备样品。
使用光谱椭圆仪测量每个样品的厚度。400次循环样品具有128.1nm的测量厚度,这相当于约3.2/循环的沉积速率。在其它较薄的样品上,沉积速率为3.6/循环。鉴于氧化铪的堆积密度标为9.68g/cm3,对应于一个分子的降低的薄膜厚度为36.1,一层单层预计为约3.3厚。因此,介于3.2/循环到3.6/循环之间的沉积速率正好相当于每次循环沉积一层单层。也可以确定:沉积速率是温度敏感的。在170℃下操作的样品导致2.8/循环的沉积速率。
现在参考图2,其是制备包括氧化铪和氧化锆层的纳米叠层制品或层状薄膜的流程图。步骤210在ALD室内提供半导体基片。将半导体基片加热至一定温度以获得原子层沉积范围。
步骤220将无水硝酸铪(Hf(NO3)4)或无水硝酸锆(Zr(NO3)4)(第一硝酸盐)引入ALD室中。在此步骤220中无论引入的是硝酸铪还是硝酸锆都会吸附到半导体基片表面上。
步骤230是用氮气或惰性气体清洗ALD室以减少或消除过多的无水硝酸铪或无水硝酸锆或不需要的反应物。
步骤240将含水气体引入ALD室。含水气体有助于用用于形成氧化铪薄膜或氧化锆薄膜的氧原子去掉NO3形式或NO2形式的NO3配位体。
步骤245用氮气或惰性气体清洗ALD室以减少或消除沉积室内的含水气体或可能不需要的反应物。
步骤250说明重复步骤220、230、240和245以制备一层所需厚度的第一硝酸盐材料,氧化铪或氧化锆。借助适当的清洗,通过交替暴露于硝酸盐、硝酸铪或硝酸锆和含水气体下循环的次数限制ALD方法固有的生长速率。通过重复步骤250所示的循环可以形成所需厚度的每层材料,氧化铪或氧化锆。
步骤320将在步骤220中未引入的无水硝酸铪(Hf(NO3)4)或无水硝酸锆(Zr(NO3)4)(第二硝酸盐)引入ALD室内。在此步骤320中无论引入的是硝酸铪还是硝酸锆都会吸附到半导体基片表面上。
步骤330用氮气或惰性气体清洗ALD室以减少或消除过多的无水硝酸铪或无水硝酸锆或不需要的反应物。
步骤340将含水气体引入ALD室。含水气体有助于用用于形成氧化铪薄膜或氧化锆薄膜的氧原子去掉无论是NO3形式的还是NO2形式的NO3配位体,而在步骤240中未形成这些薄膜。
步骤345用氮气或惰性气体清洗ALD室以减少或消除室内的含水气体或可能不需要的反应物。
步骤350说明重复步骤320、330、340和345以制备一层所需厚度的材料,氧化铪或氧化锆。此外,步骤350说明重复以220开始的步骤。这可以形成具有多层交替层的薄膜,例如分别确定每层厚度以及总厚度的
HfO2/ZrO2/HfO2/ZrO2或ZrO2/HfO2/ZrO2/HfO2/ZrO2。
完成所需的循环和亚循环次数后,步骤360退火薄膜以调节薄膜和其它界面。
Claims (19)
1.一种在基片上形成高-k介电薄膜的方法,包括以下步骤:
a)在原子层沉积室内提供在半导体基片上的氢钝化的硅表面;
b)将基片加热到低于200℃的温度;
c)向沉积室中引入无水硝酸铪;
d)用氮气或惰性气体清洗沉积室;和
e)向沉积室中引入含水气体,从而沉积单层氧化铪。
2.权利要求1的方法,其中含水气体是水蒸汽、甲醇或氢气。
3.权利要求1的方法,其中将基片加热到160和200℃之间的温度。
4.权利要求1的方法,进一步包括将无水硝酸铪引入沉积室中,清洗沉积室和将含水气体引入沉积室中的重复步骤。
5.权利要求4的方法,其中重复以上步骤直至氧化铪薄膜具有小于20埃的等效氧化物厚度。
6.一种在基片上形成高-k介电薄膜的方法,包括以下步骤:
a)在原子层沉积室内提供在半导体基片上的氢钝化的硅表面;
b)将基片加热到低于200℃的温度;
c)向沉积室中引入无水硝酸锆;
d)用氮气清洗沉积室;和
e)向沉积室中引入含水气体,从而沉积单层氧化锆。
7.权利要求6的方法,其中含水气体是水蒸汽、甲醇或氢气。
8.权利要求6的方法,其中将基片加热至160和200℃之间的温度。
9.权利要求6的方法,进一步包括将无水硝酸锆引入沉积室中,清洗沉积室和将含水气体引入沉积室中的重复步骤。
10.权利要求9的方法,其中重复以上步骤直至氧化铪薄膜具有小于20埃的等效氧化物厚度。
11.一种形成含氧化铪和氧化锆的纳米叠层制品的方法,包括以下步骤:
a)在原子层沉积室内提供在半导体基片上的氢钝化的硅表面;
b)将基片加热到低于200℃的温度;
c)通过包括如下步骤的方法形成一层氧化铪:
i)向沉积室中引入无水硝酸铪;
ii)清洗沉积室;
iii)向沉积室中引入含水气体,从而沉积单层氧化铪;
iv)清洗沉积室;和
d)通过包括如下步骤的方法形成一层氧化锆:
i)向沉积室中引入无水硝酸锆;
ii)清洗沉积室;
iii)向沉积室中引入含水气体,从而沉积单层氧化锆;和
iv)清洗沉积室。
12.权利要求11的方法,进一步包括重复c)形成氧化铪层的步骤直至达到所需的厚度。
13.权利要求11的方法,进一步包括重复d)形成氧化锆层的步骤直至达到所需的厚度。
14.权利要求11的方法,进一步包括重复c)形成氧化铪层和d)形成氧化锆层的步骤,从而形成所需总厚度的纳米叠层制品。
15.权利要求3的方法,其中将基片加热到170℃。
16.权利要求3的方法,其中将基片加热到180℃。
17.权利要求8的方法,其中将基片加热到170℃。
18.权利要求8的方法,其中将基片加热到180℃。
19.权利要求11的方法,其中将基片加热到160和200℃之间的温度。
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KR100531464B1 (ko) * | 2000-06-30 | 2005-11-28 | 주식회사 하이닉스반도체 | 원자층 증착법을 이용한 하프니움산화막 형성방법 |
KR100467366B1 (ko) * | 2000-06-30 | 2005-01-24 | 주식회사 하이닉스반도체 | 원자층 증착법을 이용한 지르코늄산화막 형성방법 |
KR100396694B1 (ko) * | 2000-07-27 | 2003-09-02 | 주식회사 하이닉스반도체 | 원자층 증착법을 이용한 박막 제조 방법 |
KR20020064126A (ko) * | 2001-01-31 | 2002-08-07 | 주식회사 다산 씨.앤드.아이 | 원자층 화학기상증착을 이용한 게이트 산화막 형성방법 |
-
2001
- 2001-06-28 US US09/894,941 patent/US6420279B1/en not_active Expired - Lifetime
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2002
- 2002-06-20 JP JP2002180523A patent/JP4055941B2/ja not_active Expired - Lifetime
- 2002-06-25 TW TW091113864A patent/TW577130B/zh not_active IP Right Cessation
- 2002-06-27 KR KR10-2002-0036308A patent/KR100432411B1/ko not_active IP Right Cessation
- 2002-06-28 CN CNB021418268A patent/CN1184673C/zh not_active Expired - Fee Related
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TW577130B (en) | 2004-02-21 |
JP4055941B2 (ja) | 2008-03-05 |
JP2003068732A (ja) | 2003-03-07 |
CN1396638A (zh) | 2003-02-12 |
KR100432411B1 (ko) | 2004-05-22 |
US6420279B1 (en) | 2002-07-16 |
KR20030003046A (ko) | 2003-01-09 |
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