CN1207667C - Mass high-speed digital signal source based on microcomputer PCI bus - Google Patents
Mass high-speed digital signal source based on microcomputer PCI bus Download PDFInfo
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- CN1207667C CN1207667C CN 01131693 CN01131693A CN1207667C CN 1207667 C CN1207667 C CN 1207667C CN 01131693 CN01131693 CN 01131693 CN 01131693 A CN01131693 A CN 01131693A CN 1207667 C CN1207667 C CN 1207667C
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Abstract
The present invention relates to a mass high-speed digital signal source based on a microcomputer PCI bus, which comprises a microcomputer, a PCI bus controller, a signal storage device, a local bus controller and a high-speed output port, wherein the microcomputer is used for producing various waveforms of signals of the signal source and storing the signals in a hard disk, the PCI bus controller is used for PCI bus interface work between the signal source and the microcomputer, the signal storage device is used for temporarily caching data transmitted by the PCI bus from the hard disk, the local bus controller is used for the harmonious work in the signal source, and the high-speed output port is used for providing an interface corresponding to a debugging system to ensure the stable and accurate output of the data stream in transmission. The mass high-speed digital signal source can develop a corresponding application program to control the data transmission of a board card of the signal source by using the characteristic of friendly man-machine interface of a Windows operating system, which makes the operation of the signal source convenient and visual. The design method makes full use of various software sources and hardware sources in the microcomputer and has low cost, good compatibility and convenient and easy use.
Description
Technical field
The present invention relates to digital signaling system, particularly a kind of mass high-speed digital signal system based on microcomputer PCI bus.
Background technology
Development along with microelectric technique and large scale integrated circuit, increasing large scale digital signal processing system has dropped into operation, for example video on-demand system VOD (Video-On-Demand), high-definition television HDTV (High-Definition TV), wireless communication system and synthetic-aperture radar SAR (Synthetic Aperture Radar) real time imagery disposal system etc.These systems all need the mass high-speed digital signal system in development, debugging, integrating process, signal acquisition with replace complex, costliness, or simulated hazard, do not allow the process tested, produce the needed high-speed digital signal of real system and be input in the system, the various functions and the performance of test and verification system.Because the desired input signal of these systems is a large amount of digital signals at a high speed, with SAR is example, when pulse repetition rate PRF is 2000Hz, to each echo with 8192 points of 66.6MHz frequency sampling, when each point is got I, each 8bits of Q two-way, the per second average amount is about 32MB, and the crest frequency of burst mode output is 66.6MHz.Common signal system obviously is difficult to meet the demands, therefore need exploitation to be suitable for the universal signal system of this type systematic, the sort signal system is not only a kind of common random waveform digital signal generator, more can produce the actual signal that output is applicable to various debug systems.
Summary of the invention
The object of the present invention is to provide a kind of mass high-speed digital signal system based on universal microcomputer.
For achieving the above object, the mass high-speed digital signal system based on microcomputer PCI bus comprises:
Pci bus controller is used for the pci bus interface work between signal system and the microcomputer;
Signal storage equipment is used for the data that temporary cache transmits from hard disk via pci bus;
Local bus control is used for the co-ordination of control signal internal system;
The high-speed output end mouth is used to provide and the debug system corresponding interface, steady, the errorless output of data stream when guaranteeing transmission;
Described digital signaling system is by the pci bus collaborative work that links to each other with microcomputer, will be stored in various waveform signals in the hard disk of microcomputer by certain format, sequential output.
The present invention utilizes the processor of configuration in the microcomputer to produce the various waveform signals of signal system and is stored in the interior hard disk of microcomputer, or directly the actual signal that will transmit is stored in the hard disk, when needing transmission at first by microcomputer bus with in the storeies such as SDRAM of data transmission to the signal system integrated circuit board, send through the output port of signal system integrated circuit board again.Utilize Windows operating system close friend's man-machine interface characteristic, can develop the data transmission that corresponding application is come control signal system integrated circuit board, make the easy and simple to handle directly perceived of signal system.This method for designing makes full use of various soft, hardware resources in the microcomputer, and cost is low, and is compatible good, convenient easy-to-use.
Description of drawings
Fig. 1 is a high-speed digital signal service system block diagram;
Fig. 2 is radar return data time sequence figure.
Embodiment
As shown in Figure 1, have better compatibility and extensibility, the interface of necessary careful selection signal system integrated circuit board and microcomputer in order to make signal system.PCI (peripheral element extension interface) bus is a kind of for host CPU and peripheral hardware provide the local bus of high-performance data bus, has advantages such as high-performance, low cost, high reliability, use be flexible, has occupied the microsystem leading position gradually.Consider these superior functions of pci bus, therefore adopt pci bus to be used as the interface of digital signaling system and microsystem.This integrated circuit board reads the mass data that is stored in the hard disk of microcomputer, in the storer of microcomputer PCI bus high-speed transfer to the integrated circuit board, and frequency on request, form output again.Because the peak rate of pci bus is 132MB/s, therefore, as long as R/W speed of hard disc is enough fast, the output speed of signal system can be approached the peak rate 132MB/s of pci bus in theory, can satisfy the performance requirement of SAR, HDTV mass data processing systems such as (mean speed are no more than 20MB/s) fully.Data layout can be controlled by programming software on computers neatly simultaneously.
The high-speed digital signal service system mainly is made up of four parts, and the function of each several part is as follows:
1.PCI bus controller: mainly finish the pci bus interface work between signal system and the microcomputer, make that microcomputer can identification signal system integrated circuit board, and will be stored in data transmission in the hard disk to the signal storage equipment of signal system integrated circuit board by the programming under the Windows, the transmission of enabling signal realizes the control to signal system.
2. signal storage equipment: be mainly used to the data that temporary cache transmits from hard disk via pci bus, stable with the data stream that guarantees the output of signal system integrated circuit board, adopt SDRAM usually.When the speed of needed data stream is lower than the read-write speed of hard disk, can splice on high capacity signal storage equipment, only need use a spot of buffer memory, and carry out control corresponding and get final product at the high-speed output end mouth.When required output speed is higher than the pci bus transfer rate, use signal storage equipment can not be subjected to the restriction of pci bus transmission speed, the data among the output SDRAM in cycle are for the expansion of signal system performance is allowed some leeway.
3. local bus control: the co-ordination of control signal system integrated circuit board inside, with the pci bus controller co-operation, with the data storage in the hard disk in the signal storage of integrated circuit board, and, control the high-speed output end mouth and send by the frequency of real system requirement with the form that the data-switching in the storer becomes to require.
4. output at a high speed: steady, the errorless output of data stream when guaranteeing transmission mainly is provided and the debug system corresponding interface.Can require to make corresponding change according to the difference of various debug systems.When not having signal storage on the signal system integrated circuit board, have certain buffer memory ability to guarantee the steady of output stream.
The pci bus standard is very complicated, can select special chip for use, the pci bus interface controller of modelled signal system, and microcomputer is read and write the configuration of finishing this PCI equipment by serial eeprom interface to the EERPOM on the expansion board.It supports the peak value of the reached 132MB/s of the PCI2.2 version transfer rate of bursting in pci interface part.Special chip provides an internal bus interface to finish the transmission of signal, and in the design of signal system, the use interface is finished the control to local bus in the signal system.
Local bus control can adopt the dedicated cpu chip; Also can adopt the EPLD chip, write the design that code is realized hardware control logic with VHDL language, as the series of ALTERA company.According to actual needs configuration is programmed, wipes, revised to chip, than simple, quick with the CPU exploitation.In the design of this signal system, adopt the EPLD chip, realize to the control of the local bus on the signal system, in memory device SDRAM on the data tablet.When output data, with corresponding Data Format Transform and control output frequency.These functions all realize by the VHDL language programming.
Memory device can be selected the SDRAM of a constant volume according to the actual requirements for use on the signal system plate.When being applied to the HDTV system debug, can select for use the SDRAM of 64MB to be convenient to rolling output test to store several width of cloth view data.When if data transfer rate is lower than the read-out speed of hard disk, also can save SDRAM with simplified design.
The data that depend on real application systems fully of choosing of high-speed output end mouth are imported requirement.Usually can select FIFO (first in first out) for use, obtain the data stream of different frequency, realize and the asynchronous communication of real system by the clock of control FIFO output terminal.The output interface definition of FIFO is by realizing local bus control's EPLD chip programming with VHDL language, like this for the test macro of distinct interface, as long as EPLD is carried out the change that software programming just can realize interface protocol, needn't change hardware circuit fully with VHDL language.
The software design of high-speed digital signal system mainly is to be driver of signal system exploitation, thereby the data that will be stored in the hard disk of microcomputer are exported through signal system.In order to improve the versatility of system, develop a driver and control and finish the signal system various operations directly related with hardware based on the Win95/98 of widespread use.The exploitation of driver can be used some special-purpose tool software bags.
Driver operates in the bottom of system, calls by application program, and be that the signal system exploitation has the application program of window interface therefore with MicrosoftVC++.In application program, at first want the load driver program, by calling program hardware is carried out various operation controls then, as preparing the transmission data, start transmission, finish transmission etc., unloading driver when application program withdraws from.The user needs only corresponding button on the window interface, can realize above-mentioned functions.
After finishing all soft, hardware design, also need to generate a hardware description file My Card.INF, add in the system, make operating system can correctly discern high-speed digital signal system integrated circuit board, and when system initialization, distribute needed system resource.
Embodiment
In the development process of real time imagery disposal system, the digital signaling system of a guinea pig echoed signal need be arranged at the input end of imaging processor.Because radar works in the mode of transmit burst, so radar echo signal also is train of impulses, and promptly signal is a burst mode.In each duration of pulse, with 8192 points of 66.6M clock sampling, each point minute I, each 8bits of Q two-way (as shown in Figure 2), pulse transmission frequency (PRF) is up to 2000Hz.This shows that the data volume of radar signal output is very big, peak velocity is very high (to reach 66.6 * 2MB/s).Although owing to only send at impulse duration, make mean speed descend to some extent, but when PRF=2000, the per second average amount still reach about 32MB/s, requiring signal system accordingly is a kind of data-source device of high speed, finishes bursting high-speed data output.
Adopt the designed digital signaling system in front based on microcomputer PCI bus, select PCI32 bit address, data multiplex bus run for use, clock frequency is 33MHz, the zero-waiting cycle bursts when transmitting, the bus hardware circuit solution can reach 132MB, be four times that radar signal system data rate requires, can finish receiving radar data that microcomputer transmits and to the task of Real Time Image System by the output of radar mode of operation guinea pig data.
The SAR original data volume is very big, is the image of a width of cloth 8Kbytes*1Kbytes of 11: 1 for down-sampled rate generally, and its original data volume is 176Mbytes, and when the position line of image increased, its data volume also can be bigger.If it is the sdram size that disposes on the signal system integrated circuit board is excessive, then very complicated to its management meeting.Be simplified design, can on the signal system integrated circuit board, do not dispose SDRAM, directly utilize the internal memory of microcomputer, and at output port configuration high-speed FIFO.At first data are read microcomputer memory, be sent among the FIFO through pci bus again and export.
In the work of debugging real time imagery processor, we leave true radar data in the hard disk of microcomputer in by certain format earlier.When simulating the transport process of true radar data, at first the data in the hard disk are called in the internal memory, re-use control channel data are sent on the signal system integrated circuit board from internal memory, the control capacity is that the FIFO of 8192*16bits receives data.FIFO with the output of 66.6MHz clock, receives following data, so circulation with the data among the FIFO again after Data Receiving is full.If the data volume that transmits then can be set up the transmission chained list earlier less than the memory size of system, total data is read in the internal memory of chained list connection, export repeatedly through pci bus again.These are all realized by the driver of application call signal system.
Through actual test, the test result that obtains signal system is as shown in table 1 below.As seen, the transmission of signal system
| The shared internal memory of data | Transmission chained list node number | Every node points to internal memory | The signal system transfer rate |
| ?1MB | ?16 | ?64KB | ?72MB/s |
| ?1MB | ?16*4 | ?16KB | ?70MB/s-72MB/s |
| ?8MB | ?16*32 | ?16KB | ?71MB/s |
| ?16MB | ?16*16 | ?64KB | ?72MB/s |
| ?32MB | ?16*128 | ?16KB | ?71MB/s |
| ?128MB | ?16*128 | ?16KB | ?71MB/s |
| ?176MB | ?16*176 | ?64KB | ?71MB/s |
Table 1 signal system transfer rate test result
Speed is for the transmission quantity of the number of node of transmission chained list and every node and insensitive.Its average transmission speed can reach 70MB/s, satisfies the test request to High Speed Systems such as HDTV system, SAR Real Time Image System fully.
When data volume surpasses the Installed System Memory capacity, can only be on one side from the hard disk reading of data, Yi Bian transmit data.Application program is made corresponding change, and after having set up the transmission chained list, application program is read in a part of data earlier and filled up transmission chained list memory block pointed, start transmission, after the end of transmission (EOT), read in the next part data again to same memory block, restart transmission, so circulation is gone down.Obviously as long as the average read-out speed of hard disk can meet the requirements of 32MB/s, then the mean speed of signal system output just can satisfy the debugging requirement of SAR real time imagery disposal system.For the IDE hard disk that can not reach this rate requirement, RAID (Redundant Arrayof Independent Disks) card that can PCI allocation-ide interface, make it to be operated in RAID 0 pattern, be that data leave on member's disk of forming this array in proper order, thereby can read the data on a plurality of hard disks simultaneously, improve the reading rate of data.In order further to improve speed, can set up two transmission chained lists simultaneously, when application program when one of them reads in data, another chained list is transmitted, two chained lists alternately write, transmit data, can make the transmission average data rate of signal system maintain 30MB/b (two IBM 60GXP 40G hard disks, 7200 change, ide interface), can satisfy SAR real time imagery processor substantially and be 2000 o'clock rate requirement at PRF.
Compare with existing other signal systems, this signal system has following several respects characteristic:
1, is a kind of high speed, mass digital signal system.Its output momentary rate is 66.6 * 2MB/s, can reach 70MB/s to the circulation of the static data in internal memory output mean speed, and flow-data (reading from hard disk of microcomputer) output mean speed also can reach about 50MB/s (depending on the hard disk reading rate).
2, simple in structure, cost is lower.Because signal system has made full use of soft, the hardware resources such as processor, storer, hard disk and Windows operating system of the microcomputer of present widespread usage, so the structure of signal system is very simple, used components and parts are less, and cost of development is lower, and the cycle is short.
3, has good versatility.Because signal system meets the microcomputer PCI bus standard, inserts any microcomputer PCI bus slot, as long as correct install driver, signal system gets final product operate as normal.The sort signal system is not only a kind of common random waveform digital signal generator, more can produce output and be applicable to the actual signal of various debug systems, with replace complex, expensive signal acquisition, or simulated hazard, does not allow the process tested.For example can provide test signal for various signal processing systems such as HDTV system, wireless communication system, pulse Doppler radar systems.
4, has good dirigibility.As long as in advance with the various data storage of actual needs in hard disk of microcomputer, signal system just can be exported various signal.Test macro for various distinct interfaces, only need according to different interface protocols, with VHDL language EPLD is programmed and to change definition, and needn't hardware circuit be changed, just can provide required test signal for various test macro to the FIFO output interface.
5, be with good expansibility.For different test macros, can on the signal system integrated circuit board, dispose the memory device that needs on demand.Because signal system in strict conformity with the PCI standard, can be done improvement along with the upgrading of PCI agreement.
6, easy and simple to handle.Owing to developed the window interface application program based on Windows operating system, the button above only needing to click can be finished function corresponding, does not need various complicated operations fully.
Claims (5)
1. mass high-speed digital signal system based on microcomputer PCI bus comprises:
Pci bus controller is used for the pci bus interface work between signal system and the microcomputer;
Signal storage equipment is used for the data that temporary cache transmits from hard disk via pci bus;
Local bus control is used for the co-ordination of control signal internal system;
The high-speed output end mouth is used to provide and the debug system corresponding interface, steady, the errorless output of data stream when guaranteeing transmission;
Described digital signaling system is by the pci bus collaborative work that links to each other with microcomputer, will be stored in various waveform signals in the hard disk of microcomputer by certain format, sequential output.
2. by the described signal system of claim 1, it is characterized in that described signal storage equipment is SDRAM.
3. by the described signal system of claim 1, it is characterized in that described microcomputer directly is stored in the actual signal that will transmit in the hard disk.
4. by the described signal system of claim 1, it is characterized in that described high-speed output end mouth adopts first-in first-out.
5. by the described signal system of claim 1, it is characterized in that described local bus control adopts the EPLD chip.
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| CN 01131693 CN1207667C (en) | 2001-12-27 | 2001-12-27 | Mass high-speed digital signal source based on microcomputer PCI bus |
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| US8426672B2 (en) | 2006-08-03 | 2013-04-23 | Velcro Industries B.V. | Outer cover engagement |
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Owner name: LIAONING PUTIAN PHOTOELECTRIC CO., LTD. Free format text: FORMER OWNER: INST. OF COMPUTING TECHNOLOGY, CHINESE ACADEMY OF SCIENCES Effective date: 20110117 |
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