CN1218298A - 高速/高性能金属氧化物半导体晶体管及其制造方法 - Google Patents
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 16
- 239000004065 semiconductor Substances 0.000 claims abstract description 44
- 239000000758 substrate Substances 0.000 claims abstract description 43
- 229910045601 alloy Inorganic materials 0.000 claims description 44
- 239000000956 alloy Substances 0.000 claims description 44
- 238000000034 method Methods 0.000 claims description 22
- 239000002019 doping agent Substances 0.000 claims description 15
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 11
- 229920005591 polysilicon Polymers 0.000 claims description 11
- 238000009792 diffusion process Methods 0.000 claims description 7
- 229910052785 arsenic Inorganic materials 0.000 claims description 6
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical group [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 claims description 6
- 230000003647 oxidation Effects 0.000 claims description 5
- 238000007254 oxidation reaction Methods 0.000 claims description 5
- 238000010301 surface-oxidation reaction Methods 0.000 claims description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical group [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 2
- 229910052796 boron Inorganic materials 0.000 claims description 2
- 229910015900 BF3 Inorganic materials 0.000 claims 3
- WTEOIRVLGSZEPR-UHFFFAOYSA-N boron trifluoride Chemical group FB(F)F WTEOIRVLGSZEPR-UHFFFAOYSA-N 0.000 claims 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical group [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims 2
- 229910052698 phosphorus Inorganic materials 0.000 claims 2
- 239000011574 phosphorus Substances 0.000 claims 2
- 230000035755 proliferation Effects 0.000 claims 1
- 230000000694 effects Effects 0.000 abstract description 8
- 239000012535 impurity Substances 0.000 abstract 4
- 125000006850 spacer group Chemical group 0.000 abstract 2
- 229910044991 metal oxide Inorganic materials 0.000 description 15
- 150000004706 metal oxides Chemical class 0.000 description 15
- 150000002500 ions Chemical class 0.000 description 11
- 238000002347 injection Methods 0.000 description 6
- 239000007924 injection Substances 0.000 description 6
- 230000008020 evaporation Effects 0.000 description 5
- 238000001704 evaporation Methods 0.000 description 5
- 239000002131 composite material Substances 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 208000014413 Maternally-inherited diabetes and deafness Diseases 0.000 description 1
- 229910001096 P alloy Inorganic materials 0.000 description 1
- 230000004913 activation Effects 0.000 description 1
- 238000004458 analytical method Methods 0.000 description 1
- 229910052787 antimony Inorganic materials 0.000 description 1
- WATWJIUSRGPENY-UHFFFAOYSA-N antimony atom Chemical compound [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000014509 gene expression Effects 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 238000005036 potential barrier Methods 0.000 description 1
- 238000004151 rapid thermal annealing Methods 0.000 description 1
- 230000001105 regulatory effect Effects 0.000 description 1
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Abstract
一种可抑制伴随元件的微小化而产生的短沟道效应的高速/高性能金属氧化物晶体管及其制造方法,该金属氧化物晶体管包括半导体衬底、栅绝缘膜、栅电极、氧化膜、第一隔离区、第二隔离区、第一掺杂层、第二掺杂层、第三掺杂层、以及第四掺杂层。
Description
本发明涉及一种MOS(金属氧化物)晶体管及其制造方法,特别涉及一种可抑制伴随小于0.25μm的高速半导体装置中的元件的微小化而产生的短沟道现象并维持元件的高速/高性能的MOS晶体管及其制造方法。
随着半导体制造技术的发展,元件的尺寸达到四分之一微米级,从而,在MOS晶体管中出现的现象不同于在长沟道时产生的现象。其具代表性的现象就是短沟道效应,该短沟道效应是指,在小于0.5微米的栅长度时,同长沟道相比,通常是短沟道中的阈值电压减小。
这样的短沟道效应可用一维电荷分配模型(1-Dimensional ChargeSharing Method)来简单地分析,还可以用依据二维势垒降低(2-DimensionalPotential Barrier Lowering)的数值分析法来准确地建立模型。
为了抑制所述短沟道效应,可从数学公式中推导出减小栅氧化膜的厚度、减小栅下部的耗尽层最大宽度(Depletion Maximum Width)、且减小衬底浓度等方法,但最好应形成薄接合(shallow iunction)。
因此,在现在的ULSI(Ultra Large Scale Integration:超大规模集成)技术中,试着导入了薄离子注入设备,用RTA(Rapid Thermal Annel:快速热退火)方法进行后续热处理以实现薄接合,且正在应用于批量生产中。
虽然导入了上述的两个用于形成薄接合的方法,但四分之一微米级的元件所要求的标准越来越高,如果考虑涉及设备的限度与批量生产化的工序可控制性(process controllability),则可知道,为简单结构下的薄接合而进行的努力也达到了极限。
现有的MOS晶体管是具代表性的LDD(lightly doped drain:轻掺杂漏极)结构。这样的LDD结构是在薄接合结构中以MDD(moderate dopeddrain:中度掺杂漏极)进行着。
同LDD结构相比,所述MDD结构将LDD区域的掺杂水平从~E14/cm2增加到~E15/cm2,而欲提高元件性能。但是,在MIDD区域中的掺杂水平的增加,会作为伴随短沟道化产生的短沟道效应的主要原因而起作用。
本发明是为解决上述问题而提供的,其目的在于提供可抑制伴随元件的微小化而产生的短沟道效应的高速/高性能MOS晶体管及其制造方法。
为实现上述目的,本发明的一种高速/高性能MOS晶体管包括:包含第一导电型掺杂物的半导体衬底;在所述半导体衬底上形成的栅绝缘膜;在所述栅绝缘膜上形成的栅电极;通过所述栅电极的表面氧化而形成的氧化膜;在所述栅电极的侧壁形成的第一隔离区;在所述第一隔离区的倾斜侧壁形成的第二隔离区;第一掺杂层,是向所述半导体衬底的表面附近倾斜注入第二导电型掺杂物、以使其自己排列在所述栅电极的边缘而形成的,并具有第一深度和低浓度;第二掺杂层,是向所述半导体衬底的表面附近倾斜注入第二导电型掺杂物、以使其自己排列在所述第一隔离区的边缘而形成的,并具有比所述第一深度更深的第二深度和中间浓度;第三掺杂层,是向所述半导体衬底的表面附近倾斜注入第一导电型掺杂物、以使其自己排列在所述第一隔离区的边缘而形成的,并具有围绕以中间浓度形成的所述第二掺杂层的第三深度和比所述半导体衬底的掺杂物浓度更高的掺杂物浓度;第四掺杂层,是向所述半导体衬底的表面附近注入第二导电型掺杂物、以使其自己排列在所述第二隔离区的边缘而形成的,并具有比所述第三深度更深的第四深度和高浓度。
并且,本发明的制造方法包括:在包含第一导电型掺杂物的半导体衬底上形成栅绝缘膜的步骤;在所述栅绝缘膜上形成栅电极的步骤;对所述栅电极的表面进行氧化而形成表面氧化膜的步骤;向所述半导体衬底的表面附近倾斜注入第二导电型掺杂物、以使其自己排列在表面被氧化的栅电极的边缘,从而形成具有第一深度的低浓度的第一掺杂层的步骤;在表面被氧化的所述栅电极的侧壁形成第一隔离区的步骤;向所述半导体衬底的表面附近倾斜注入第二导电型掺杂物、以使其自己排列在所述第一隔离区的边缘,从而形成具有比第一深度更深的第二深度的中间浓度的第二掺杂层的步骤;向所述半导体衬底的表面附近倾斜注入第一导电型掺杂物、以使其自己排列在所述第一隔离区的边缘,从而形成具有围绕所述中间浓度的第二掺杂层的第三深度和比所述半导体衬底的掺杂物浓度更高的掺杂物浓度的第三掺杂层的步骤;在所述第一隔离区的倾斜侧壁形成第二隔离区的步骤;向所述半导体衬底的表面附近注入第二导电型掺杂物、以使其自己排列在所述第二隔离区的边缘,从而形成具有比所述第三深度更深的第四深度的高浓度的第四掺杂层的步骤。
附图的简要说明:
图1是本发明涉及的高速/高性能MOS晶体管的剖面图;
图2至图6是图1中的高速/高性能MOS晶体管的制造工序示意图。
下面说明本发明的优选实施例。
图1是本发明涉及的高速/高性能MOS晶体管的剖面图。
图1中的本发明涉及的MOS晶体管包括:包含第一导电型、例如P掺杂物的半导体衬底10;在该半导体衬底10的表面上形成的栅绝缘膜12;在该栅绝缘膜12上形成的栅电极14;在该栅电极14的表面通过氧化方法形成的氧化膜16;在栅电极14的侧壁形成的第一隔离区18;在第一隔离区18的倾斜侧壁上形成的第二隔离区20;第一掺杂层的LDD区域22,是向所述半导体衬底10的表面附近倾斜注入第二导电型例如N型掺杂物、以使其自己排列在所述栅电极14的边缘而形成的,具有第一深度和低浓度;第二掺杂层的MDD区域24,是向所述半导体衬底10的表面附近倾斜注入第二导电型掺杂物、以使其自己排列在所述第一隔离区18的边缘而形成的,具有比所述第一深度深的第二深度和中间浓度;第三掺杂层的P型罩26,是向所述半导体衬底10的表面附近倾斜注入第一导电型掺杂物、以使其自己排列在所述第一隔离区18的边缘而形成的,具有围绕所述中间浓度的第二掺杂层24的第三深度和比所述半导体衬底10的掺杂物浓度更高的掺杂物浓度,;第四掺杂层的源极/漏极区域28,是向所述半导体衬底10的表面附近注入第二导电型掺杂物、以使其自己排列在所述第二隔离区20的边缘而形成的,具有比所述第三深度更深的第四深度和高浓度。在图中,未说明的标号30表示用于调节沟道区域的阈值电压并防止击穿现象的掺杂物离子注入区域。
所述栅电极14的表面氧化膜16的厚度是3~8nm,所述第一隔离区18的宽度是10~30nm,所述第二隔离区20的宽度是50~100nm。
所述LDD区域22是通过浓度为1E13~1E14/cm2、能量为15~30KeV、倾斜角为7~45°的离子注入而形成的,所述MDD区域24是通过浓度为1E14~1E15/cm2、能量为20~30KeV、倾斜角为7~45°的离子注入而形成的。
并且,所述P型罩26是通过浓度为2E12~2E13/cm2、能量为20~40KeV、倾斜角为7~45°的离子注入而形成的,所述源极/漏极区域28是通过浓度为1E15~5E15/cm2、能量为10~50KeV的离子注入而形成的。
图2至图6是图1中的高速/高性能MOS晶体管的制造工序示意图。
下面,参照图2至图6说明本发明的制造方法。
首先,如图2所示,在P型半导体衬底10上形成约15nm厚的缓冲氧化膜之后,进行用于调节阈值电压的离子注入和用于防止击穿现象的离子注入,从而形成掺杂层30。接着,在去除缓冲氧化膜之后,在衬底10的表面上形成栅绝缘膜12,并在该栅绝缘膜12上蒸镀多晶硅,然后通过照相蚀刻工序用蒸镀的多晶硅形成栅电极14。
然后,如图3所示,对由多晶硅构成的栅电极14的表面进行氧化而形成约3~8nm厚的表面氧化膜16,再如图4所示,通过浓度为1E13~1E14/cm2、能量为15~30KeV、倾斜角为7~45°的离子注入方法注入第二导电型掺杂物例如砷(As)、以使其自己排列在进行了表面氧化的栅电极14的边缘,从而,在所述半导体衬底10的表面附近形成低浓度的第一掺杂层、即LDD区域22。此时,所述LDD区域22的侧面与栅多晶硅重叠。当以栅多晶硅边缘为基准的LDD区域22的垂直接合深度大于60nm时,可能会产生表面击穿现象,所以LDD区域22的垂直接合深度最好是小于60nm。
其次,如图5所示,在该制成物的整个表面上蒸镀10~30nm厚的绝缘膜之后,通过深腐蚀(etch back)工序在栅电极14的侧壁形成第一隔离区18。接着,通过浓度为1E14~1E15/cm2、能量为20~30KeV、倾斜角为7~45°的离子注入方法注入第二导电型掺杂物例如砷(As)或锑(Sb)、以使其自己排列在第一隔离区18的边缘,从而,在所述半导体衬底10的表面附近形成具有比所述第一深度更深的第二深度的中间浓度的第二掺杂层、即MDD区域24。此时,当该MDD区域24和栅多晶硅重叠的时候,在位于栅多晶硅的边缘下方的半导体衬底10处产生强电场,产生的该强电场会诱发热载流子(hot carrier)而导致降低元件特性的结果。所以,使MDD区域24的侧面扩散区域和栅多晶硅不重叠。并且,使所述MDD区域24的垂直接合深度比LDD区域22的垂直接合深度扩散更深。其原因是,同以LDD区域22的垂直接合深度形成的时候相比,此时的MDD区域24的垂直接合深度可减小寄生电阻,所以可流过相对更多的电流,并能够增加漏极的饱和电流。
然后,通过浓度为2E12~2E13/cm2、能量为20~40KeV、倾斜角为7~45°的离子注入方法注入第一导电型掺杂物即P型掺杂物、以使其自己排列在第一隔离区18的边缘,从而在所述半导体衬底10的表面附近形成具有围绕MDD区域24的第三深度和比所述半导体衬底10的掺杂物浓度更高的掺杂物浓度的第三掺杂层、即P型罩26。当该P型罩26的侧面区域围绕LDD区域22的时候,可使沟道区域的掺杂物浓度(dopant concentration)发生局部变化而引起阈值电压的特性变化。所以,不应使P型罩26的侧面区域比LDD区域22更深向里侧。并且,当P型罩26的垂直接合深度比MDD区域24深而围绕N+区域的时候,应抑制MDD区域24的蒸镀扩散,且由于在N+区域中的接合容量增加了,所以,不应使P型罩26的垂直接合深度比MDD区域24更深而围绕N+区域。
接着,如图6所示,在该制成物的整个表面上蒸镀50~100nm厚的绝缘膜之后,通过深腐蚀(etch back)工序在第一隔离区18的倾斜侧壁上形成第二隔离区20。然后,通过浓度为1E15~5E15/cm2、能量为10~50KeV的离子注入方法注入第二导电型掺杂物即N型掺杂物、以使其自己排列在该第二隔离区20的边缘,从而,在所述半导体衬底10的表面附近形成具有比所述第三深度更深的第四深度的高浓度的第四掺杂层、即源极/漏极区域28。之后,利用RTP方法进行1000℃下的30分钟的热处理,从而活化注入的掺杂物。
如上所述的本发明,通过在低浓度的LDD区域和高浓度的源极/漏极区域之间形成具有中间浓度的MDD区域、并利用该MDD区域来减小LDD的水平阻抗且增加漏极饱和电流,能够获得高速/高性能的MOS晶体管。
此外,通过利用LDD区域在栅极边缘的漏极附近减小电场的最大值,能够提高四分之一微米级的MOS晶体管的可靠性。
另外,具有由P型罩区域围绕MDD区域的结构,从而在垂直方向上形成LDD区域和MDD区域的较薄的接合,在水平方向上行使抑制由MDD区域和源极/漏极区域引起的击穿现象的固有功能,因此,能够改善短沟道效应。
本发明不仅仅限于上述的实施例,在权利要求中记载的本发明的技术思想和范围内,本领域技术人员可进行多种变形。
例如,上述实施例是对NMOS晶体管的情况进行的说明,也可应用于PMOS晶体管。而且,当应用于PMOS晶体管的时候,第一掺杂层22的掺杂物使用硼或BF2,第二掺杂层24的掺杂物使用BF2或铟(In)。
Claims (25)
1.一种高速/高性能金属氧化物晶体管,其特征在于,包括:包含第一导电型掺杂物的半导体衬底;在所述半导体衬底上形成的栅绝缘膜;在所述栅绝缘膜上形成的栅电极;通过所述栅电极的表面氧化而形成的氧化膜;在所述栅电极的侧壁形成的第一隔离区;在所述第一隔离区的倾斜侧壁形成的第二隔离区;第一掺杂层,是向所述半导体衬底的表面附近倾斜注入第二导电型掺杂物、以使其自己排列在所述栅电极的边缘而形成的,第一深度和并具有低浓度;第二掺杂层,是向所述半导体衬底的表面附近倾斜注入第二导电型掺杂物、以使其自己排列在所述第一隔离区的边缘而形成的,并具有比所述第一深度更深的第二深度和中间浓度;第三掺杂层,是向所述半导体衬底的表面附近倾斜注入第一导电型掺杂物、以使其自己排列在所述第一隔离区的边缘而形成的,并具有围绕以中间浓度形成的所述第二掺杂层的第三深度和比所述半导体衬底的掺杂物浓度更高的掺杂物浓度;第四掺杂层,是向所述半导体衬底的表面附近注入第二导电型掺杂物、以使其自己排列在所述第二隔离区的边缘而形成的,并具有比所述第三深度更深的第四深度和高浓度。
2.如权利要求1所述的高速/高性能金属氧化物晶体管,其特征在于,所述栅电极的表面氧化膜的厚度是3~8nm。
3.如权利要求1所述的高速/高性能金属氧化物晶体管,其特征在于,所述第一隔离区的宽度是10~30nm。
4.如权利要求1所述的高速/高性能金属氧化物晶体管,其特征在于,所述第二隔离区的宽度是50~100nm。
5.如权利要求1所述的高速/高性能金属氧化物晶体管,其特征在于,所述第一导电型是P型,第二导电型是N型。
6.如权利要求5所述的高速/高性能金属氧化物晶体管,其特征在于,所述第一掺杂层的掺杂物是砷(As)。
7.如权利要求5所述的高速/高性能金属氧化物晶体管,其特征在于,所述第二掺杂层的掺杂物是砷(As)。
8.如权利要求5所述的高速/高性能金属氧化物晶体管,其特征在于,所述第二掺杂层的掺杂物是磷(P)。
9.如权利要求5所述的高速/高性能金属氧化物晶体管,其特征在于,所述第三掺杂层的掺杂物是硼(B)。
10.如权利要求5所述的高速/高性能金属氧化物晶体管,其特征在于,所述第三掺杂层的掺杂物是氟化硼(BF2)。
11.如权利要求5所述的高速/高性能金属氧化物晶体管,其特征在于,所述第四掺杂层的掺杂物是砷(As)。
12.如权利要求1所述的高速/高性能金属氧化物晶体管,其特征在于,所述第一导电型是N型,第二导电型是P型。
13.如权利要求12所述的高速/高性能金属氧化物晶体管,其特征在于,所述第一掺杂层的掺杂物是氟化硼(BF2)。
14.如权利要求12所述的高速/高性能金属氧化物晶体管,其特征在于,所述第二掺杂层的掺杂物是氟化硼(BF2)。
15.如权利要求12所述的高速/高性能金属氧化物晶体管,其特征在于,所述第三掺杂层的掺杂物是磷(P)。
16.如权利要求12所述的高速/高性能金属氧化物晶体管,其特征在于,所述第三掺杂层的掺杂物是砷(As)。
17.如权利要求12所述的高速/高性能金属氧化物晶体管,其特征在于,所述第四掺杂层的掺杂物是BF2。
18.如权利要求1所述的高速/高性能金属氧化物晶体管,其特征在于,所述第一掺杂层,在栅多晶硅边缘以侧面扩散深度不超过70nm的状态同栅多晶硅重叠。
19.如权利要求1所述的高速/高性能金属氧化物晶体管,其特征在于,所述第二掺杂层的侧面扩散深度至栅多晶硅边缘的附近为止。
20.如权利要求1所述的高速/高性能金属氧化物晶体管,其特征在于,所述第三掺杂层以侧面扩散深度不超出第一掺杂层的状态围绕第二掺杂层,而垂直扩散深度不超出第四掺杂层的深度,所述第四掺杂层的侧面扩散深度至隔离区深度附近为止。
21.一种高速/高性能金属氧化物晶体管制造方法,其特征在于,它包括:在包含第一导电型掺杂物的半导体衬底上形成栅绝缘膜的步骤;在所述栅绝缘膜上形成栅电极的步骤;对所述栅电极的表面进行氧化而形成表面氧化膜的步骤;向所述半导体衬底的表面附近倾斜注入第二导电型掺杂物、以使其自己排列在表面被氧化的栅电极的边缘,从而形成具有第一深度的低浓度的第一掺杂层的步骤;在表面被氧化的所述栅电极的侧壁形成第一隔离区的步骤;向所述半导体衬底的表面附近倾斜注入第二导电型掺杂物、以使其自己排列在所述第一隔离区的边缘,从而形成具有比第一深度更深的第二深度的中间浓度的第二掺杂层的步骤;向所述半导体衬底的表面附近倾斜注入第一导电型掺杂物、以使其自己排列在所述第一隔离区的边缘,从而形成具有围绕所述中间浓度的第二掺杂层的第三深度和比所述半导体衬底的掺杂物浓度更高的掺杂物浓度的第三掺杂层的步骤;在所述第一隔离区的倾斜侧壁形成第二隔离区的步骤;向所述半导体衬底的表面附近注入第二导电型掺杂物、以使其自己排列在所述第二隔离区的边缘,从而形成具有比所述第三深度更深的第四深度的高浓度的第四掺杂层的步骤。
22.如权利要求21所述的高速/高性能金属氧化物晶体管制造方法,其特征在于,所述第一掺杂层是通过浓度为1E13~1E14/cm2、能量为15~30KeV、倾斜角为7~45°的离子注入而形成的。
23如权利要求21所述的高速/高性能金属氧化物晶体管制造方法,其特征在于,所述第二掺杂层是通过浓度为1E14~1E15/cm2、能量为20~30KeV、倾斜角为7~45°的离子注入而形成的。
24.如权利要求21所述的高速/高性能金属氧化物晶体管制造方法,其特征在于,所述第三掺杂层是通过浓度为2E12~2E13/cm2、能量为20~40KeV、倾斜角为7~45°的离子注入而形成的。
25.如权利要求21所述的高速/高性能金属氧化物晶体管制造方法,其特征在于,所述第四掺杂层是通过浓度为1E15~5E15/cm2、能量为10~50KeV的离子注入而形成的。
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KR1019970062573A KR100260044B1 (ko) | 1997-11-25 | 1997-11-25 | 고속/고성능 모스 트랜지스터 및 그 제조방법 |
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Publications (2)
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CN1135634C CN1135634C (zh) | 2004-01-21 |
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Application Number | Title | Priority Date | Filing Date |
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CNB981080294A Expired - Fee Related CN1135634C (zh) | 1997-11-25 | 1998-04-28 | 高速/高性能金属氧化物半导体晶体管及其制造方法 |
Country Status (7)
Country | Link |
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US (2) | US6274906B1 (zh) |
JP (1) | JPH11177083A (zh) |
KR (1) | KR100260044B1 (zh) |
CN (1) | CN1135634C (zh) |
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RU (1) | RU2197769C2 (zh) |
TW (1) | TW407323B (zh) |
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-
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- 1997-11-25 KR KR1019970062573A patent/KR100260044B1/ko not_active IP Right Cessation
-
1998
- 1998-04-15 JP JP10105010A patent/JPH11177083A/ja active Pending
- 1998-04-28 CN CNB981080294A patent/CN1135634C/zh not_active Expired - Fee Related
- 1998-11-19 DE DE19853441A patent/DE19853441A1/de not_active Withdrawn
- 1998-11-23 US US09/198,230 patent/US6274906B1/en not_active Expired - Lifetime
- 1998-11-24 TW TW087119469A patent/TW407323B/zh not_active IP Right Cessation
- 1998-11-24 RU RU98121328/28A patent/RU2197769C2/ru not_active IP Right Cessation
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CN100383935C (zh) * | 2002-11-22 | 2008-04-23 | 南亚科技股份有限公司 | 源极/漏极元件的制造方法 |
CN100442444C (zh) * | 2003-10-17 | 2008-12-10 | Imec公司 | 用于提供具有活性掺杂剂层结构的半导体衬底的方法 |
CN102054700B (zh) * | 2009-11-10 | 2012-06-06 | 中芯国际集成电路制造(上海)有限公司 | Pmos晶体管的制造方法 |
CN102738000A (zh) * | 2011-04-12 | 2012-10-17 | 中芯国际集成电路制造(上海)有限公司 | 一种超浅结形成方法 |
Also Published As
Publication number | Publication date |
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KR100260044B1 (ko) | 2000-07-01 |
US6461924B2 (en) | 2002-10-08 |
RU2197769C2 (ru) | 2003-01-27 |
US20010018255A1 (en) | 2001-08-30 |
US6274906B1 (en) | 2001-08-14 |
TW407323B (en) | 2000-10-01 |
CN1135634C (zh) | 2004-01-21 |
KR19990041898A (ko) | 1999-06-15 |
DE19853441A1 (de) | 1999-05-27 |
JPH11177083A (ja) | 1999-07-02 |
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