CN1219770A - 结合薄膜和体Si晶体管的合并逻辑和存储器 - Google Patents

结合薄膜和体Si晶体管的合并逻辑和存储器 Download PDF

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CN1219770A
CN1219770A CN98123962A CN98123962A CN1219770A CN 1219770 A CN1219770 A CN 1219770A CN 98123962 A CN98123962 A CN 98123962A CN 98123962 A CN98123962 A CN 98123962A CN 1219770 A CN1219770 A CN 1219770A
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CN1139126C (zh
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P·G·埃玛
黄威
S·M·盖茨
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International Business Machines Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
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    • H10B10/00—Static random access memory [SRAM] devices
    • H10B10/12—Static random access memory [SRAM] devices comprising a MOSFET load element
    • H10B10/125—Static random access memory [SRAM] devices comprising a MOSFET load element the MOSFET being a thin film transistor [TFT]
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    • Y10S257/00—Active solid-state devices, e.g. transistors, solid-state diodes
    • Y10S257/903—FET configuration adapted for use as static memory cell

Abstract

本发明描述了利用两种半导体层即薄膜层和体硅层形成高密度、高速合并逻辑和存储器IC芯片。存储单元利用三维(3D)SRAM结构。公开了两种3D逻辑单元。3D形式的差分级联电压开关(DCVS)结构和3D形式的具有旁路门的DCVS(DCVSPG)。描述一种高密度“芯片上系统”结构。通过在TF硅层上设置大PMOS晶体管,在体硅层设置快速NMOS晶体管,从而实现高密度。还记载了一种在IC芯片上同时制造逻辑和存储电路的单一工艺程序。

Description

结合薄膜和体Si晶体管的合并逻辑和存储器
本发明一般涉及在一个半导体集成电路(IC)芯片上设计和制造合并逻辑电路和存储器阵列，具体涉及“芯片上系统”电路及其制造方法，其中逻辑电路利用两种半导体层，薄膜层和体硅(Si)层，以及存储器阵列由静态随机存取存储器(SRAM)构成。
逻辑电路和存储阵列密度的增大使得电路运行速度更快，集成电路(IC)更小，因此降低了每个IC的成本。目前，逻辑和存储功能是制造作在分立的IC上，整个系统的速度受到逻辑和存储器间通信带宽的限制。约500MHz的性能极限是由通信带宽造成的，是逻辑和存储器通信距离较长(毫米)的直接结果。
另外，通过在Si晶片层设置四个n型金属氧化物半导体(NMOS)晶体管，在Si晶片层之上的薄膜(TF)多晶Si(p-Si)层设置两个p型金属氧化物半导体(PMOS)负载晶体管，目前16兆位(Mb)和64兆位(Mb)以及更高集成度的静态随机存取存储器(SRAM)阵列的密度增大。例如，见A.K.Sharma,Semiconductor Memories,IEEE Press,New York(1997)和Y.Takao,H.Shimada,N.Suzuki,Y.Matsukawa和N.Sasaki,IEEE Transactions on Electron Devices 39(1992),P2147。SRAM单元需要更小的Si晶片面积。这是一个三维(3D)集成以获得更高密度并因此得到更大集成SRAM阵列的例子。在3D SRAM的例子中，其它优点是增大抗噪声干扰能力和降低备用电流，如Sharma,supra所述的那样。
实现突破500MHz性能极限的方法是将逻辑电路和存储阵列集成在一个IC上。这些IC被称为“合并逻辑和存储器”，或“芯片上系统”结构。芯片上系统可以增强性能。目前，两类不同的工艺技术分别用于制造不同的逻辑和存储芯片。
需要的是增大密度比并增强性能的解决方法，及制造逻辑和存储电路的单一工艺技术。
因此，本发明的目的是提供一种设计和制造“芯片上系统”IC的简洁且经济的方法。
本发明再一目的是提供一种用于逻辑和存储电路的单一的工艺技术及3D集成方法。
根据本发明，提供一种合并逻辑和存储器IC，其中逻辑电路制造在两个半导体层上，薄膜(TF)层和体Si层。该逻辑电路为三维形式的差分级联电压开关(DVCS)逻辑，其中PMOS晶体管在位于NMOS晶体管之上的薄膜Si层中制作，而NMOS晶体管制作在体Si晶片层中。例如，L.G.Heller,W.R.Griffin,J.W.Davis和N.G.Thoma在DigestTech.Papers,ISSCC 1984,pp.16-17中，及Fang-shi Lai和Wei Hwang在IEEEJournal of Solid-State Circuits,32(1997)P.563中描述了这种逻辑电路。本发明的存储阵列由静态随机存储器(SRAM)构成，其中SRAM单元包括制造作在前述位于四个NMOS驱动器晶体管之上的薄膜Si层的两个PMOS负载晶体管，而所说的NMOS晶体管位于前述的体Si晶片层中。
从以下结合附图对本发明优选实施例的详细说明中，可以更好地理解本发明的上述和其它目的、方案及优点，其中：
图1A和1B分别是展示现有技术的平面SRAM单元的原理图和平面图；
图2A和2B分别是展示现有技术的三维SRAM单元的原理图和剖面图；
图3A和3B分别是展示现有技术的常规DCVS逻辑单元的原理图和平面图；
图4是展示本发明三维结构的互补金属氧化物半导体(CMOS)晶体管对的剖面图；
图5A和5B分别是展示三维DCVS逻辑AND/NAND门的原理图和剖面图；
图6A和6B分别是展示制作成具有3D DCVSPG(旁路门)逻辑的逻辑AND/NAND门的特殊情况的原理图和剖面图；
图7A是展示制作成具有3D DCVS逻辑的N树逻辑的一般情况的框图和原理图；
图7B是展示制作成具有DCVS逻辑的静态CMOS加法电路的常规(2D)情况的原理图；
图7C是展示利用两个PMOS薄膜晶体管(TFT)和十个NMOS晶体Si晶体管的DCVS加法电路的三维(3D)情况的原理图；
图7D是展示利用两个PMOSTFT和八个NMOS晶体Si晶体管的DCVSPG加法电路的三维(3D)情况的原理图；
图8A-8D分别是展示用于3D SRAM和3D DCVS逻辑电路的薄膜晶体管(TFT)层的工艺顺序的剖面图。
现参见附图，具体说是图1A和1B，它们示出了现有技术平面静态随机存取存储器(SRAM)阵列的实例。图1A是展示标准六晶体管CMOSSRAM单元的电路原理图。NMOS晶体管Q1和Q2是存取器件，NMOS晶体管Q3和Q4是驱动器晶体管，两个PMOS晶体管Q5和Q6是负载晶体管。
图1B展示了标准SRAM单元的布线平面图。Q1和Q2NMOS晶体管是由有源n型硅1与多晶硅层3和4的交叠区构成的。Q1和Q2的源接触10通过金属层6与Vss或地接触。同样地，Q3和Q4是由有源硅31与多晶层5的交叠区构成的，多晶层5构成字线(WL)。Q3和Q4的漏接触20分别接到位线 Bit和Bit。PMOS晶体管Q5和Q6接到金属层7到Vdd。Q5和Q6的漏接触40和42接到图1A中的实心点所示的节点。
图2A和2B展示了利用薄膜Si PMOS负载晶体管按三维(3D)方式制造的现有技术SRAM单元。图2A的电路基本上与图1A的相同。
2B展示了现有技术的三维(3D)SRAM单元的结构、用于提高存储阵列密度的制造方法。三维SRAM单元将PMOS晶体管Q5和Q6放置在薄膜晶体管(TFT)层，该层最好是通过准分子激光退火法形成的多晶Si(p-Si)。晶体管Q1-Q4制作在晶体Si晶片衬底上。更具体说，如图2B所示，Q1和Q2 NMOS晶体管是由有源N型硅21和23与第一多晶硅层16和15的交叠区分别构成的。同样，Q3和Q4是由有源硅11和12与第一多晶硅层17的交叠区构成的，其中第一多晶硅层17构成字线(WL)。Q3和Q4的漏接触18接到在铝(A1)金属层构成的位线(BL和BL)。第二多晶硅层28构成PMOS TFT Q5和Q6(底栅TFT结构)的栅。第三多晶硅层13和14构成TFT Q5和Q6的有源层，还构成Vdd线。第二多晶硅层28与第三多晶硅13和14的交叠区分别构成TFTQ5和Q6。
差分级联电压开关(DCVS)逻辑是一种双轨CMOS电路技术，与常规单轨NAND/NOR随机逻辑相比，在布线面积、电路延迟、功耗和逻辑灵活性等方面具有潜在的优势。DCVS由叠置的NMOS差分对构成，所说的差分对连接到用于上拉的一对交叉耦合的PMOS负载。在静态模式下不引出直流。因此，常规CMOS逻辑中需要几个门的复布尔逻辑功能可以由DCVS的单级门实现。
图3A和3B展示了与本发明有关的现有技术的单差分级联电压开关(DCVS)逻辑。图3A是常规DCVS AND/NAND门的原理电路图，图3B是布线平面图。这种情况下，所有的六个晶体管都制作在单一的Si晶片衬底层。有四个驱动器晶体管Q1-Q4，它们是NMOS器件，它们构成了N沟道逻辑求值(真值和补值)树。电路负载由两个交叉耦合的PMOS负载晶体管Q5和Q6构成，这两个晶体管对于本发明来说已足够，因为这些器件占居Si晶片的很大面积，所以妨碍了常规DCVS逻辑取得很大的面积密度。
图3A中，NMOS逻辑树的左边一枝由两个串联的NMOS晶体管Q2和Q1及接地的接点构成，形成一个下拉网络。Q2和Q1用作开关，它们分别由它们的栅信号A和B控制。NMOS逻辑树的右边一枝由两个并联的NMOS晶体管Q3和Q4构成。两个晶体管连接到地，构成另一下拉网络。Q3和Q4分别由它们的栅信号互补输入 A和 B控制。上拉网络由两个交叉耦合的PMOS晶体管Q5和Q6构成。在输入信号A和B从低变到高时，晶体管Q1和Q2导通。节点Y对地放电。节点Y在互补输入信号 A和 B从高变到低的过渡期间为浮置的。
NMOS晶体管Q3和Q4都截止。节点Y的地电平使得交叉耦合的PMOS负载晶体管Q6导通。输出节点Y被充电到高电平。于是实现了双AND/NAND逻辑功能。
图3B是单个DCVS AND/NAND门的布线平面图。Q1和Q2 NMOS晶体管由有源N硅31与多晶硅层36和37的交叠区构成。由此源和漏扩散自对准于栅A和B。Q1的源接触通过金属层41接到Vss或地。Q2的漏接触43接到节点①或 Y。同样，Q3和Q4 NMOS晶体管由有源硅31与多晶硅层38和39的交叠区构成。因此源和漏扩散与栅 A和 B自对准。Q1的源接触45和47通过金属层41接到Vss或地。Q3和Q4的共享漏接触49接到节点②或Y。Q5和Q6PMOS晶体管制作在注入到n阱区33的p+区中。n阱通常是一个比晶体管的源/漏注入更深的注入区，因此，对于外部尺寸来说必需在n阱边缘和相邻的n+扩散区间提供足够的间距。另外，Q5和Q6 PMOS晶体管由有源p-型硅32与多晶硅层34和35的交叠区构成。Q5和Q6的源接触51和53通过金属层50连接到Vdd。Q5和Q6的漏接触55和57分别接到节点①和②，或Y和 Y。
图4是展示本发明结构的剖面图。更具体说，图4是本发明最一般形式的剖面图，即用于形成逻辑和SRAM存储元件的三维(3D)CMOS晶体管对。为清楚起见，只展示了晶体管层(未示出布线层)。在该简化的剖面图中，单个NMOS晶体管400形成于结晶Si晶片衬底401上。PMOS负载晶体管411形成于NMOS器件之上的Si层上。用于PMOS TFT的Si层406最好是由准分子激光退火方法形成的多晶硅(p-Si)。可选择的是，这是一种通过快速热退火(RTA)法形成的p-Si。简单说，该结构的下面部分是厚绝缘层402、通孔403和填充通孔的导体404。
利用化学机械抛光(CMP)法平面化厚绝缘层402形成平整的表面，以便于PMOS晶体管411的后续制造。该结构上面部分是薄膜Si层406、栅介质层407、栅导体408和源漏接触409。源和漏金属层409靠厚绝缘层(钝化)层410绝缘。下面结合图8A-8D详细说明该结构的薄膜Si的上层的制造情况。
现结合图5A和5B说明本发明的一般情况和优选实施例，图5A和5B展示了本发明一个实施例的具体结构，一种DCVS逻辑的AND和NAND差分逻辑门3D的电路结构。图5A示出了其差分形式的DCVS电路原理，展示了DCVS逻辑的AND和NAND门的电路原理图(三维结构或3D DCVS)。另外，为清楚起见，只示出了晶体管层和上至M4的选定布线层(未示出完全的布线层)。有源晶体管Q1-Q4形成于结晶Si晶片衬底上。两个交叉耦合的PMOS负载晶体管Q5和Q6形成于TFT层，该层最好是由准分子激光退火法形成的多晶Si(p-Si)。根据差分输入，由NMOS组合逻辑求值树网络下拉一个输出(F或 F)。正反馈作用将PMOS锁定在稳态输出F和 F，或全差分Vdd和地逻辑电平。
3D DCVS的基本电路操作与以上结合图3A所述的2D DCVS相同。在3D的情况下，上拉负载网络由两交叉耦合的PMOS TFT构成。这对于所说负载器件的设计灵活性非常有益。复逻辑门的上拉性能即快速上升时间可以动态地增加。应该注意，双轨逻辑已专用于先进的高性能数字系统。构成2D或3D DCVS的复NMOS逻辑树的设计程序可以由卡诺图(Karnaugh图，K-图)合成。
图5B是展示制造该电路的详细剖面图。在p+衬底500上淀积p-外延层501。利用标准的NMOS工艺在p+衬底500上制造有源晶体管Q1-Q4。晶体管Q1-Q4的有源区503由N型掺杂剂的注入限定。然后浅沟槽隔离(STI)502将相邻器件Q2和Q3隔离开。将所淀积的多硅层构图，分别形成晶体管Q1-Q4的自对准的Si栅524、525、526和527。利用离子注入形成n型掺杂的源和漏区503。形成源和漏的接触505，并使它们与第一金属层(M1)连接。晶体管Q1、Q3和Q4的源结接触与M1，地连接。Q1、Q2、Q3和Q4的晶体管栅分别与输入信号A、B和A、 B连接。用化学汽相淀积(CVD)形成厚绝缘层506。如上所述，利用化学机械抛光(CMP)法平面化厚绝缘层506，形成平整的表面518，以便于PMOS负载晶体管的后续制造。
然后构图体NMOS晶体管和PMOS薄膜晶体管(TFT)间连接的重要通孔，并进行腐蚀。用导体530和532填充这些通孔。导体530连接Q2和Q5。导体532连接Q3、Q4和Q6。
PMOS负载晶体管形成于TFT Si层上，最好是由准分子激光退火法形成的多晶Si(p-Si)层上。该结构起始于薄膜Si层的淀积，然后构图成有源岛507。形成保形淀积的栅绝缘层508。然后淀积重掺杂的多晶硅层，形成自对准的硅栅509。利用离子注入形成p型掺杂的源和漏区。源和漏的接触连接到M2或M3金属层。TFT Q5的漏接触531与金属层M2连接，构成节点 F。TFT Q6的接触533与金属层M2连接，构成节点F。这些节点分别连接到输出信号线 F和F。另外，TFT Q5的源接触512和TFT Q6的接触511与M3层514连接，然后穿过通孔516到达第四金属层M4,517。通过互连511从薄膜布线514将Vdd施加到TFT Q6。通过互连512从薄膜布线514将Vdd施加到TFT Q5。所淀积的介质层510和515将各薄膜布线层隔离开。图中只示出了必要布线层。只示出了一个位于Vdd 514之上的布线层。利用标准VLSI技术，形成其余线连接的背端。
下面结合图6A和6B说明本发明的具体情况和优选实施例。要说明的是一种所谓的具有旁路门的3D差分级联电压开关(DCVSPG)逻辑的新型高性能低电源电路技术。利用旁路门逻辑树按DCVSPG设计这种电路，代替DCVS式的NMOS逻辑堆叠树。DCVS为比例电路。DCVSPG认为是无比例电路。图6A是利用DCVSPG逻辑按三维结构制造的简单AND/NAND门的电路图。
图6A中，旁路门逻辑树的左侧一枝是由并联的两个NMOS Q2和Q1构成的。注意，在DCVS中，这两个NMOS晶体管串联(图5A)，但在DCVSPG中，这两个NMOS晶体管是串联的。在设计复逻辑功能(见图7A-7D)时其优点是显而易见的。旁路门树的右边一枝也是由并联的两个NMOS晶体管Q3和Q4构成。可以通过循环地利用Karnaugh图按非常对称的方式合成这种旁路门逻辑树。图6A示也了具有两个输入变量A和B的基本逻辑。输入信号A或B可以是NMOS栅控或NMOS源连接。这种情况下，如果假定信号A是控制变量，则B信号将是功能变量。控制变量连接到栅，功能变量连接到NMOS器件的源。在控制信号 A和A的作用下，我们将各终端组合在一起，如图6A所示。 A连接到Q1和Q3的控制栅。A连接到Q2和Q4的控制栅。Q1、Q2、Q3和Q4的源分别连接到功能变量Vdd、 B、地和B。两个交叉耦合的TFT PMOS晶体管Q5和Q6构成上拉网络，如图5A所示。
图6A所示的3D DCVSPG AND/NAND电路通过用旁路门设计代替NMOS树实际上解决了节点浮置问题。由于与上述情况相同，在输入信号A和B从低变到高时，Q2和Q4导通。然后，在互补信号 A和 B均从高变到低时，节点 F对地放电。然而，输出节点F立即充电到高电平状态。于是实现了双AND/NAND逻辑功能。不发生节点浮置问题。
图6B是实现图6A的电路的结构的具体剖面图。为清楚起见，只示出了晶体管层和高至M4的选定布线M4(未示出完全的布线层)。该电路的具体制造情况与图5B所示的很类似。唯一的不同在于晶体管连接方式。图6A中，NMOS网络的左侧一枝是并联连接。在p+衬底600上淀积p-型外延层601。利用标准NMOS工艺，在p+衬底600上形成有源晶体管Q1-Q4。下面结合图6B说明该结构的形成。浅沟槽隔离(STI)602将相邻器件Q2和Q3隔离开。将所淀积的多晶硅层构图，分别形成自对准的Si栅604、624、625和626。利用离子注入形成N掺杂的源和漏区603。
利用第一金属层(M1)形成以下四种连接。晶体管Q1和Q2的源结接触分别加到Vdd和 B。晶体管Q3和Q4的源结接触分别加到地和B。这些连接是利用所淀积的多晶硅层实现的。Q1的晶体管栅604和Q3的晶体管栅625连接到输入信号 A。Q2的晶体管栅连接到输入信号A,Q4的栅也连接到输入信号A。然后CVD淀积厚绝缘层606。如前所述，利用化学机械抛光(CMP)平面化厚绝缘层606，形成平整的表面618，以便于PMOS负载晶体管的后续制造。构图并腐蚀通孔，淀积导体630，填充通孔。
另外，由晶体管岛607的有源区开始形成TFT Q5和Q6。然后，淀积薄绝缘栅介质层608。接着，淀积重掺杂的多晶硅层，形成自对准的硅栅609。利用离子注入，利用栅609作自对准的掩模形成p型掺杂的源和漏区。TFT Q5和Q6的漏接触631和633分别利用第二金属层(M2)连接到输出信号线 F和F。另外，TFT Q5和Q6的源接触612和611连接到第三金属层(M3)614。M3到第四金属层(M4)的连接显示为触头616。Vdd通过互连611从薄膜布线614加到TFT Q6。所淀积介质层610和615隔离各薄膜布线层。图中只展示了一个必要的布线层，只展示了一个位于Vdd 614上的布线层。利用标准VLSI技术形成其余线连接的背端。
下面结合图7A说明本发明的最普通形式，图7A展示了本发明的一般形式，包括具有多差分(双轨)输入的逻辑门构成组合逻辑网络。上面是两个交叉耦合的PMOS TFT 76和77。通过将NMOS器件差分对串接到能够处理复布尔逻辑功能的强组合逻辑树网络，利用DCVS或DCVSPG实现逻辑设计。因此，可能需要几个常规CMOS门的复逻辑可以以DCVS或DCVSPG形式的单级门实现。例如图7B所示，可以在常规CMOS电路中利用十六个晶体管实现逻辑加法电路(八个PMOS和八个NMOS晶体管)。另一方面，可以利用十二个DCVS形式的晶体管(两个PMOS和十个NMOS)，如图7C所示，和十个DCVSPG形式的晶体管(两上PMOS和八个NMOS晶体管)，制造逻辑门电路，如图7D所示。
可以用共享使用的非堆叠PMOS器件作为负载和缓冲电路中的上拉器件来设计组合逻辑器件。因此可以放松对PMOS器件的优化和PMOS对NMOS间距的优化，减轻器件和工艺复性对DCVS设计的妨碍。
下面结合图8A-8D详细说明制造本发明的逻辑和存储结构的一组工艺步骤，这些图示出了制造本发明的薄膜晶体管(TFT)PMOS层的工艺步骤。首先假设一个完成的NMOS晶体管802层在Si晶片衬底801上。淀积厚绝缘层803，通过化学机械抛光(CMP)平面化该层。于是提供了一种用于TFT制造的光滑表面800。光刻构图通孔804，腐蚀并用导体填充通孔，由此形成层间连接805。这最好是难熔金属，例如钨。平面化了连接805后，利用合适的方法(溅射，等离子增强CVD或LPCVD)淀积非晶Si层(厚约500-1000埃)，并光刻构图成岛，然后将之变成p-Si。尽管可以用快速热退火(RTA)，但准分子激光退火(ELA)是使TF Si结晶的最好方法。图8A展示了所得的多晶Si岛806。
图8B示出了淀积栅介质807的步骤，该层最好是非晶SiO2，厚约1000-1500埃，并在300-400℃进行化学汽相淀积(CVD)形成。淀积栅电极，作为地毡式金属层(铝或其它金属)，并光刻构图，形成栅808。利用离子注入或离子喷射掺杂法，在TF Si层806中注入p型掺杂剂硼809。B+离子的能量选择为使离子穿透介质807进入TF Si806。可以利用栅808掩蔽未掺入掺杂剂的层，所以栅可以是自对准的掩模。可以任意利用两步掺杂程序，形成轻掺杂漏结构。然后，利用RTA或ELA法加热此结构几秒钟，激活掺杂剂硼原子。
图8C展示了厚绝缘层810的淀积，该层是利用化学汽相淀积淀积的非晶SiO2或氮化硅。构图并腐蚀通孔811，以便接触TFT 812的源和漏区。
图8D展示了填充通孔811的导体层813的淀积步骤。尽管可以使用其它金属，但这里优选的材料是铝。淀积源/漏金属层814，并构图成薄膜布线(TFT源/漏金属层)。最后，淀积钝化绝缘层815。因为我们这里要强调的是电路图和TFT层，所以图中未具体展示布线层814。图5A和6B展示了必要的布线层。
尽管以上结合优选实施例说明了本发明，但所属领域的技术人员应该理解，在不背离本发明精神实质和范围的情况下，可以作出改型。

Claims (16)

1．多个制作于单个集成电路(IC)芯片上的两个不同半导体层中的晶体管，所说不同半导体层包括体硅(Si)层和薄膜Si层，它们被连接，在IC芯片的所选区形成逻辑电路，在IC芯片的其余区域形成静态随机存取存储器(SRAM)阵列。
2．如权利要求1所述的多个制作于两个不同半导体层中的晶体管，其特征在于，p型金属氧化物半导体(PMOS)负载器件制作于薄膜Si层，n型金属氧化物半导体(NMOS)驱动器件制作于体Si层。
3．如权利要求1所述的多个制作于两个不同半导体层的晶体管，其特征在于，连接形成逻辑电路的晶体管构成为差分级联电压开关(DCVS)逻辑。
4．如权利要求3所述的多个制作于两个不同半导体层的晶体管，其特征在于连接晶体管形成n树形网络复布尔逻辑功能元件。
5．如权利要求1所述的多个制作于两个不同半导体层的晶体管，其特征在于连接形成逻辑电路的晶体管构成为具有旁路门的差分级联电压开关(DCVSPG)逻辑。
6．如权利要求5所述的多个制作于两个不同半导体层的晶体管，其特征在于各晶体管连接形成n树形网络复布尔逻辑功能元件。
7．如权利要求1所述的多个制作于两个不同半导体层的晶体管，其特征在于SRAM阵列具有两个制作于薄膜Si层中的p型金属氧化物半导体(PMOS)负载晶体管，薄膜Si层中位于制作于体Si层的四个n型金属氧化物半导体(NMOS)晶体管之上。
8．如权利要求1所述的多个制作于两个不同半导体层的晶体管，其特征在于两个Si层由介质层隔离开，在制作薄膜Si层前，该介质层通过化学机械抛光(CMP)平面化。
9．如权利要求1所述的多个制作于两个不同半导体层的晶体管，其特征在于p型金属氧化物半导体(PMOS)晶体管制作于位于n型金属氧化物半导体(NMOS)晶体管上的薄膜Si层中，所说n型金属氧化物半导体(NMOS)晶体管制作于体Si层中，所说薄膜Si层通过准分子激光退火(ELA)法形成。
10．一种在单个集成电路(IC)芯片上的两个不同半导体层上制造多个晶体管的方法，包括以下步骤：
在体硅(Si)层中形成n型金属氧化物半导体(NMOS)晶体管；
淀积体硅层的厚绝缘层；
平面化所淀积的厚绝缘层；
在平面化的厚绝缘层上形成薄膜(TF)硅层；
在TF硅层中注入p型掺杂剂；
在TF硅层中形成p型金属氧化物半导体(PMOS)晶体管。
11．如权利要求10所述的在两个不同半导体层上制造多个晶体管的方法，其特征在于p型掺杂剂是硼。
12．如权利要求10所述的在两个不同半导体层上制造多个晶体管的方法，还包括以下步骤：
连接各晶体管，在IC芯片的所选区形成逻辑电路；及
连接各晶体管，在IC芯片的其余区形成静态随机存取存储器(SRAM)阵列。
13．如权利要求10所述的在两个不同半导体层上制造多个晶体管的方法，其特征在于连接构成逻辑电路的晶体管构成为差分级联电压开关(DCVS)逻辑。
14．如权利要求13所述的在两个不同半导体层上制造多个晶体管的方法，其特征在于各晶体管连接形成n树形网络复布尔逻辑功能元件。
15．如权利要求10所述的在两个不同半导体层上制造多个晶体管的方法，其特征在于连接形成逻辑电路的晶体管构成为具有旁路门的差分级联电压开关(DCVSPG)逻辑。
16．如权利要求15所述的在两个不同半导体层上制造多个晶体管的方法，其特征在于各晶体管连接形成n树形网络复布尔逻辑功能元件。
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Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100382319C (zh) * 2003-09-24 2008-04-16 株式会社东芝 静态随机存取存储器
CN100440513C (zh) * 2004-10-15 2008-12-03 中国科学院上海微系统与信息技术研究所 一种三维互补金属氧化物半导体器件结构的制备方法
CN102486806A (zh) * 2010-12-03 2012-06-06 北京晶智意达科技有限公司 网表子电路多级交换信息的描述方法
CN102487087A (zh) * 2010-12-01 2012-06-06 上海丽恒光微电子科技有限公司 应用于三维片上集成系统的薄膜晶体管及其制造方法
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Families Citing this family (274)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6849557B1 (en) 1997-04-30 2005-02-01 Micron Technology, Inc. Undoped silicon dioxide as etch stop for selective etch of doped silicon dioxide
US6271542B1 (en) 1997-12-08 2001-08-07 International Business Machines Corporation Merged logic and memory combining thin film and bulk Si transistors
US6277758B1 (en) 1998-07-23 2001-08-21 Micron Technology, Inc. Method of etching doped silicon dioxide with selectivity to undoped silicon dioxide with a high density plasma etcher
US6268228B1 (en) * 1999-01-27 2001-07-31 International Business Machines Corporation Electrical mask identification of memory modules
US6117722A (en) * 1999-02-18 2000-09-12 Taiwan Semiconductor Manufacturing Company SRAM layout for relaxing mechanical stress in shallow trench isolation technology and method of manufacture thereof
US6452856B1 (en) 1999-02-26 2002-09-17 Micron Technology, Inc. DRAM technology compatible processor/memory chips
US6838713B1 (en) * 1999-07-12 2005-01-04 Virage Logic Corporation Dual-height cell with variable width power rail architecture
JP3386038B2 (ja) * 2000-06-22 2003-03-10 セイコーエプソン株式会社 半導体記憶装置
US6831299B2 (en) * 2000-11-09 2004-12-14 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
JP4570811B2 (ja) * 2001-04-27 2010-10-27 ルネサスエレクトロニクス株式会社 半導体装置
KR100418089B1 (ko) * 2001-06-21 2004-02-11 주식회사 하이닉스반도체 반도체 소자의 박막 트랜지스터 제조 방법
US6989108B2 (en) * 2001-08-30 2006-01-24 Micron Technology, Inc. Etchant gas composition
SG102639A1 (en) 2001-10-08 2004-03-26 Micron Technology Inc Apparatus and method for packing circuits
JP2003243528A (ja) * 2002-02-13 2003-08-29 Toshiba Corp 半導体装置
KR100487521B1 (ko) * 2002-03-19 2005-05-03 삼성전자주식회사 부동체 효과를 제거하는 스태틱 랜덤 억세스 메모리 셀 및그 제조방법
US7129744B2 (en) * 2003-10-23 2006-10-31 Viciciv Technology Programmable interconnect structures
US20040004251A1 (en) * 2002-07-08 2004-01-08 Madurawe Raminda U. Insulated-gate field-effect thin film transistors
US6998722B2 (en) * 2002-07-08 2006-02-14 Viciciv Technology Semiconductor latches and SRAM devices
US7673273B2 (en) * 2002-07-08 2010-03-02 Tier Logic, Inc. MPGA products based on a prototype FPGA
US6992503B2 (en) * 2002-07-08 2006-01-31 Viciciv Technology Programmable devices with convertibility to customizable devices
US6856030B2 (en) * 2002-07-08 2005-02-15 Viciciv Technology Semiconductor latches and SRAM devices
US7112994B2 (en) * 2002-07-08 2006-09-26 Viciciv Technology Three dimensional integrated circuits
US20040004239A1 (en) * 2002-07-08 2004-01-08 Madurawe Raminda U. Three dimensional integrated circuits
US7812458B2 (en) * 2007-11-19 2010-10-12 Tier Logic, Inc. Pad invariant FPGA and ASIC devices
US8643162B2 (en) 2007-11-19 2014-02-04 Raminda Udaya Madurawe Pads and pin-outs in three dimensional integrated circuits
US7030651B2 (en) 2003-12-04 2006-04-18 Viciciv Technology Programmable structured arrays
US6876040B1 (en) * 2003-12-12 2005-04-05 International Business Machines Corporation Dense SRAM cells with selective SOI
US7176713B2 (en) * 2004-01-05 2007-02-13 Viciciv Technology Integrated circuits with RAM and ROM fabrication options
KR100615085B1 (ko) * 2004-01-12 2006-08-22 삼성전자주식회사 노드 콘택 구조체들, 이를 채택하는 반도체소자들, 이를채택하는 에스램 셀들 및 이를 제조하는 방법들
KR100564611B1 (ko) * 2004-02-14 2006-03-29 삼성전자주식회사 하드 디스크 드라이브의 완충 구조체
US7247528B2 (en) * 2004-02-24 2007-07-24 Samsung Electronics Co., Ltd. Methods of fabricating semiconductor integrated circuits using selective epitaxial growth and partial planarization techniques
CN2719043Y (zh) 2004-04-14 2005-08-24 韩力 雾化电子烟
KR100519801B1 (ko) * 2004-04-26 2005-10-10 삼성전자주식회사 스트레스 완충 스페이서에 의해 둘러싸여진 노드 콘택플러그를 갖는 반도체소자들 및 그 제조방법들
US7489164B2 (en) * 2004-05-17 2009-02-10 Raminda Udaya Madurawe Multi-port memory devices
US7149142B1 (en) 2004-05-28 2006-12-12 Virage Logic Corporation Methods and apparatuses for memory array leakage reduction using internal voltage biasing circuitry
US7315466B2 (en) * 2004-08-04 2008-01-01 Samsung Electronics Co., Ltd. Semiconductor memory device and method for arranging and manufacturing the same
US7312487B2 (en) * 2004-08-16 2007-12-25 International Business Machines Corporation Three dimensional integrated circuit
KR100580640B1 (ko) * 2004-12-17 2006-05-16 삼성전자주식회사 다결정 실리콘 필름의 제조방법 및 이를 이용한 적층형트랜지스터의 제조방법
US7372720B1 (en) * 2005-02-16 2008-05-13 Altera Corporation Methods and apparatus for decreasing soft errors and cell leakage in integrated circuit structures
KR100702011B1 (ko) * 2005-03-16 2007-03-30 삼성전자주식회사 다중 게이트 트랜지스터들을 채택하는 씨모스 에스램 셀들및 그 제조방법들
KR100702012B1 (ko) * 2005-03-22 2007-03-30 삼성전자주식회사 매립막 패턴들을 갖는 에스. 램들 및 그 형성방법들
KR100663360B1 (ko) * 2005-04-20 2007-01-02 삼성전자주식회사 박막 트랜지스터를 갖는 반도체 소자들 및 그 제조방법들
US20090224330A1 (en) * 2005-07-28 2009-09-10 Hong Chang Min Semiconductor Memory Device and Method for Arranging and Manufacturing the Same
US7978561B2 (en) * 2005-07-28 2011-07-12 Samsung Electronics Co., Ltd. Semiconductor memory devices having vertically-stacked transistors therein
US7512017B2 (en) * 2005-12-21 2009-03-31 Intel Corporation Integration of planar and tri-gate devices on the same substrate
KR100665853B1 (ko) * 2005-12-26 2007-01-09 삼성전자주식회사 고집적 스태이틱 랜덤 억세스 메모리에 채용하기 적합한적층 메모리 셀
US20070145367A1 (en) * 2005-12-27 2007-06-28 Taiwan Semiconductor Manufacturing Company, Ltd. Three-dimensional integrated circuit structure
KR100737920B1 (ko) * 2006-02-08 2007-07-10 삼성전자주식회사 반도체 소자 및 그 형성 방법
US20070194450A1 (en) * 2006-02-21 2007-08-23 Tyberg Christy S BEOL compatible FET structure
US7486111B2 (en) * 2006-03-08 2009-02-03 Tier Logic, Inc. Programmable logic devices comprising time multiplexed programmable interconnect
KR100756844B1 (ko) * 2006-08-31 2007-09-07 동부일렉트로닉스 주식회사 반도체 소자 및 이의 제조 방법
US7726320B2 (en) 2006-10-18 2010-06-01 R. J. Reynolds Tobacco Company Tobacco-containing smoking article
US7666723B2 (en) * 2007-02-22 2010-02-23 International Business Machines Corporation Methods of forming wiring to transistor and related transistor
US7586132B2 (en) * 2007-06-06 2009-09-08 Micrel, Inc. Power FET with low on-resistance using merged metal layers
US7838429B2 (en) * 2007-07-18 2010-11-23 Texas Instruments Incorporated Method to manufacture a thin film resistor
US7847586B2 (en) * 2007-08-20 2010-12-07 Northern Lights Semiconductor Corp. Integrate circuit chip with magnetic devices
US7875529B2 (en) * 2007-10-05 2011-01-25 Micron Technology, Inc. Semiconductor devices
US20090128189A1 (en) * 2007-11-19 2009-05-21 Raminda Udaya Madurawe Three dimensional programmable devices
US7635988B2 (en) * 2007-11-19 2009-12-22 Tier Logic, Inc. Multi-port thin-film memory devices
US7602213B2 (en) * 2007-12-26 2009-10-13 Tier Logic, Inc. Using programmable latch to implement logic
US7573294B2 (en) * 2007-12-26 2009-08-11 Tier Logic, Inc. Programmable logic based latches and shift registers
US7573293B2 (en) * 2007-12-26 2009-08-11 Tier Logic, Inc. Programmable logic based latches and shift registers
US7795913B2 (en) * 2007-12-26 2010-09-14 Tier Logic Programmable latch based multiplier
US8222097B2 (en) 2008-08-27 2012-07-17 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing semiconductor device
US8230375B2 (en) 2008-09-14 2012-07-24 Raminda Udaya Madurawe Automated metal pattern generation for integrated circuits
KR101529052B1 (ko) * 2009-01-30 2015-06-16 삼성전자주식회사 풀 씨모스 에스 램
US9577642B2 (en) 2009-04-14 2017-02-21 Monolithic 3D Inc. Method to form a 3D semiconductor device
US7964916B2 (en) * 2009-04-14 2011-06-21 Monolithic 3D Inc. Method for fabrication of a semiconductor device and structure
US8395191B2 (en) 2009-10-12 2013-03-12 Monolithic 3D Inc. Semiconductor device and structure
US8362482B2 (en) 2009-04-14 2013-01-29 Monolithic 3D Inc. Semiconductor device and structure
US8058137B1 (en) 2009-04-14 2011-11-15 Monolithic 3D Inc. Method for fabrication of a semiconductor device and structure
US9509313B2 (en) 2009-04-14 2016-11-29 Monolithic 3D Inc. 3D semiconductor device
US8669778B1 (en) 2009-04-14 2014-03-11 Monolithic 3D Inc. Method for design and manufacturing of a 3D semiconductor device
US11374118B2 (en) 2009-10-12 2022-06-28 Monolithic 3D Inc. Method to form a 3D integrated circuit
US10388863B2 (en) 2009-10-12 2019-08-20 Monolithic 3D Inc. 3D memory device and structure
US10354995B2 (en) 2009-10-12 2019-07-16 Monolithic 3D Inc. Semiconductor memory device and structure
US10910364B2 (en) 2009-10-12 2021-02-02 Monolitaic 3D Inc. 3D semiconductor device
US11018133B2 (en) 2009-10-12 2021-05-25 Monolithic 3D Inc. 3D integrated circuit
US10366970B2 (en) 2009-10-12 2019-07-30 Monolithic 3D Inc. 3D semiconductor device and structure
US9099424B1 (en) 2012-08-10 2015-08-04 Monolithic 3D Inc. Semiconductor system, device and structure with heat removal
US10043781B2 (en) 2009-10-12 2018-08-07 Monolithic 3D Inc. 3D semiconductor device and structure
US10157909B2 (en) 2009-10-12 2018-12-18 Monolithic 3D Inc. 3D semiconductor device and structure
CN105070715B (zh) * 2009-10-21 2018-10-19 株式会社半导体能源研究所 半导体装置
SG10201406869QA (en) 2009-10-29 2014-12-30 Semiconductor Energy Lab Semiconductor device
CN102668377B (zh) * 2009-12-18 2015-04-08 株式会社半导体能源研究所 非易失性锁存电路和逻辑电路以及使用它们的半导体器件
KR101842413B1 (ko) * 2009-12-28 2018-03-26 가부시키가이샤 한도오따이 에네루기 켄큐쇼 반도체 장치
CN105702631B (zh) * 2009-12-28 2019-05-28 株式会社半导体能源研究所 半导体器件
US9099526B2 (en) 2010-02-16 2015-08-04 Monolithic 3D Inc. Integrated circuit device and structure
US8026521B1 (en) 2010-10-11 2011-09-27 Monolithic 3D Inc. Semiconductor device and structure
US8492886B2 (en) 2010-02-16 2013-07-23 Monolithic 3D Inc 3D integrated circuit with logic
US8450779B2 (en) * 2010-03-08 2013-05-28 International Business Machines Corporation Graphene based three-dimensional integrated circuit device
KR101854421B1 (ko) * 2010-04-23 2018-05-03 가부시키가이샤 한도오따이 에네루기 켄큐쇼 반도체 장치의 제작 방법
US11344683B2 (en) 2010-05-15 2022-05-31 Rai Strategic Holdings, Inc. Vaporizer related systems, methods, and apparatus
US8757147B2 (en) 2010-05-15 2014-06-24 Minusa Holdings Llc Personal vaporizing inhaler with internal light source
US8901613B2 (en) 2011-03-06 2014-12-02 Monolithic 3D Inc. Semiconductor device and structure for heat removal
US9219005B2 (en) 2011-06-28 2015-12-22 Monolithic 3D Inc. Semiconductor system and device
US9953925B2 (en) 2011-06-28 2018-04-24 Monolithic 3D Inc. Semiconductor system and device
US10217667B2 (en) 2011-06-28 2019-02-26 Monolithic 3D Inc. 3D semiconductor device, fabrication method and system
JP2013009285A (ja) 2010-08-26 2013-01-10 Semiconductor Energy Lab Co Ltd 信号処理回路及びその駆動方法
US8163581B1 (en) 2010-10-13 2012-04-24 Monolith IC 3D Semiconductor and optoelectronic devices
US8273610B2 (en) 2010-11-18 2012-09-25 Monolithic 3D Inc. Method of constructing a semiconductor device and structure
US10497713B2 (en) 2010-11-18 2019-12-03 Monolithic 3D Inc. 3D semiconductor memory device and structure
US11482440B2 (en) 2010-12-16 2022-10-25 Monolithic 3D Inc. 3D semiconductor device and structure with a built-in test circuit for repairing faulty circuits
US11315980B1 (en) 2010-10-11 2022-04-26 Monolithic 3D Inc. 3D semiconductor device and structure with transistors
US11257867B1 (en) 2010-10-11 2022-02-22 Monolithic 3D Inc. 3D semiconductor device and structure with oxide bonds
US10896931B1 (en) 2010-10-11 2021-01-19 Monolithic 3D Inc. 3D semiconductor device and structure
US11227897B2 (en) 2010-10-11 2022-01-18 Monolithic 3D Inc. Method for producing a 3D semiconductor memory device and structure
US11018191B1 (en) 2010-10-11 2021-05-25 Monolithic 3D Inc. 3D semiconductor device and structure
US10290682B2 (en) 2010-10-11 2019-05-14 Monolithic 3D Inc. 3D IC semiconductor device and structure with stacked memory
US11462586B1 (en) * 2010-10-11 2022-10-04 Monolithic 3D Inc. Method to produce 3D semiconductor devices and structures with memory
US11024673B1 (en) 2010-10-11 2021-06-01 Monolithic 3D Inc. 3D semiconductor device and structure
US11600667B1 (en) 2010-10-11 2023-03-07 Monolithic 3D Inc. Method to produce 3D semiconductor devices and structures with memory
US11158674B2 (en) 2010-10-11 2021-10-26 Monolithic 3D Inc. Method to produce a 3D semiconductor device and structure
US11469271B2 (en) 2010-10-11 2022-10-11 Monolithic 3D Inc. Method to produce 3D semiconductor devices and structures with memory
US11605663B2 (en) 2010-10-13 2023-03-14 Monolithic 3D Inc. Multilevel semiconductor device and structure with image sensors and wafer bonding
US11133344B2 (en) 2010-10-13 2021-09-28 Monolithic 3D Inc. Multilevel semiconductor device and structure with image sensors
US10679977B2 (en) 2010-10-13 2020-06-09 Monolithic 3D Inc. 3D microdisplay device and structure
US11327227B2 (en) 2010-10-13 2022-05-10 Monolithic 3D Inc. Multilevel semiconductor device and structure with electromagnetic modulators
US10978501B1 (en) 2010-10-13 2021-04-13 Monolithic 3D Inc. Multilevel semiconductor device and structure with waveguides
US11929372B2 (en) 2010-10-13 2024-03-12 Monolithic 3D Inc. Multilevel semiconductor device and structure with image sensors and wafer bonding
US11437368B2 (en) 2010-10-13 2022-09-06 Monolithic 3D Inc. Multilevel semiconductor device and structure with oxide bonding
US11063071B1 (en) 2010-10-13 2021-07-13 Monolithic 3D Inc. Multilevel semiconductor device and structure with waveguides
US11855100B2 (en) 2010-10-13 2023-12-26 Monolithic 3D Inc. Multilevel semiconductor device and structure with oxide bonding
US10998374B1 (en) 2010-10-13 2021-05-04 Monolithic 3D Inc. Multilevel semiconductor device and structure
US11404466B2 (en) 2010-10-13 2022-08-02 Monolithic 3D Inc. Multilevel semiconductor device and structure with image sensors
US10943934B2 (en) 2010-10-13 2021-03-09 Monolithic 3D Inc. Multilevel semiconductor device and structure
US11869915B2 (en) 2010-10-13 2024-01-09 Monolithic 3D Inc. Multilevel semiconductor device and structure with image sensors and wafer bonding
US11855114B2 (en) 2010-10-13 2023-12-26 Monolithic 3D Inc. Multilevel semiconductor device and structure with image sensors and wafer bonding
US10833108B2 (en) 2010-10-13 2020-11-10 Monolithic 3D Inc. 3D microdisplay device and structure
US11694922B2 (en) 2010-10-13 2023-07-04 Monolithic 3D Inc. Multilevel semiconductor device and structure with oxide bonding
US11043523B1 (en) 2010-10-13 2021-06-22 Monolithic 3D Inc. Multilevel semiconductor device and structure with image sensors
US11163112B2 (en) 2010-10-13 2021-11-02 Monolithic 3D Inc. Multilevel semiconductor device and structure with electromagnetic modulators
US9197804B1 (en) 2011-10-14 2015-11-24 Monolithic 3D Inc. Semiconductor and optoelectronic devices
US11164898B2 (en) 2010-10-13 2021-11-02 Monolithic 3D Inc. Multilevel semiconductor device and structure
JP5588298B2 (ja) * 2010-10-14 2014-09-10 株式会社東芝 半導体装置
US8159265B1 (en) 2010-11-16 2012-04-17 Raminda Udaya Madurawe Memory for metal configurable integrated circuits
US8159268B1 (en) 2010-11-16 2012-04-17 Raminda Udaya Madurawe Interconnect structures for metal configurable integrated circuits
US8159266B1 (en) 2010-11-16 2012-04-17 Raminda Udaya Madurawe Metal configurable integrated circuits
US11355381B2 (en) 2010-11-18 2022-06-07 Monolithic 3D Inc. 3D semiconductor memory device and structure
US11164770B1 (en) 2010-11-18 2021-11-02 Monolithic 3D Inc. Method for producing a 3D semiconductor memory device and structure
US11521888B2 (en) 2010-11-18 2022-12-06 Monolithic 3D Inc. 3D semiconductor device and structure with high-k metal gate transistors
US11443971B2 (en) 2010-11-18 2022-09-13 Monolithic 3D Inc. 3D semiconductor device and structure with memory
US11569117B2 (en) 2010-11-18 2023-01-31 Monolithic 3D Inc. 3D semiconductor device and structure with single-crystal layers
US11508605B2 (en) 2010-11-18 2022-11-22 Monolithic 3D Inc. 3D semiconductor memory device and structure
US11355380B2 (en) 2010-11-18 2022-06-07 Monolithic 3D Inc. Methods for producing 3D semiconductor memory device and structure utilizing alignment marks
US11482439B2 (en) 2010-11-18 2022-10-25 Monolithic 3D Inc. Methods for producing a 3D semiconductor memory device comprising charge trap junction-less transistors
US11615977B2 (en) * 2010-11-18 2023-03-28 Monolithic 3D Inc. 3D semiconductor memory device and structure
US11211279B2 (en) 2010-11-18 2021-12-28 Monolithic 3D Inc. Method for processing a 3D integrated circuit and structure
US11004719B1 (en) 2010-11-18 2021-05-11 Monolithic 3D Inc. Methods for producing a 3D semiconductor memory device and structure
US11901210B2 (en) 2010-11-18 2024-02-13 Monolithic 3D Inc. 3D semiconductor device and structure with memory
US11495484B2 (en) 2010-11-18 2022-11-08 Monolithic 3D Inc. 3D semiconductor devices and structures with at least two single-crystal layers
US11784082B2 (en) 2010-11-18 2023-10-10 Monolithic 3D Inc. 3D semiconductor device and structure with bonding
US11804396B2 (en) 2010-11-18 2023-10-31 Monolithic 3D Inc. Methods for producing a 3D semiconductor device and structure with memory cells and multiple metal layers
US11031275B2 (en) 2010-11-18 2021-06-08 Monolithic 3D Inc. 3D semiconductor device and structure with memory
US11094576B1 (en) 2010-11-18 2021-08-17 Monolithic 3D Inc. Methods for producing a 3D semiconductor memory device and structure
US11482438B2 (en) 2010-11-18 2022-10-25 Monolithic 3D Inc. Methods for producing a 3D semiconductor memory device and structure
US11854857B1 (en) 2010-11-18 2023-12-26 Monolithic 3D Inc. Methods for producing a 3D semiconductor device and structure with memory cells and multiple metal layers
US11121021B2 (en) 2010-11-18 2021-09-14 Monolithic 3D Inc. 3D semiconductor device and structure
US11735462B2 (en) 2010-11-18 2023-08-22 Monolithic 3D Inc. 3D semiconductor device and structure with single-crystal layers
US11923230B1 (en) 2010-11-18 2024-03-05 Monolithic 3D Inc. 3D semiconductor device and structure with bonding
US11107721B2 (en) 2010-11-18 2021-08-31 Monolithic 3D Inc. 3D semiconductor device and structure with NAND logic
US11610802B2 (en) 2010-11-18 2023-03-21 Monolithic 3D Inc. Method for producing a 3D semiconductor device and structure with single crystal transistors and metal gate electrodes
US11862503B2 (en) 2010-11-18 2024-01-02 Monolithic 3D Inc. Method for producing a 3D semiconductor device and structure with memory cells and multiple metal layers
US11018042B1 (en) 2010-11-18 2021-05-25 Monolithic 3D Inc. 3D semiconductor memory device and structure
US8975670B2 (en) 2011-03-06 2015-03-10 Monolithic 3D Inc. Semiconductor device and structure for heat removal
US10388568B2 (en) 2011-06-28 2019-08-20 Monolithic 3D Inc. 3D semiconductor device and system
US9078473B2 (en) 2011-08-09 2015-07-14 R.J. Reynolds Tobacco Company Smoking articles and use thereof for yielding inhalation materials
US8687399B2 (en) 2011-10-02 2014-04-01 Monolithic 3D Inc. Semiconductor device and structure
US9117916B2 (en) 2011-10-13 2015-08-25 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device comprising oxide semiconductor film
CN103999015B (zh) 2011-12-21 2017-02-08 英特尔公司 在计算设备上促进电量延长服务的机制
US11410912B2 (en) 2012-04-09 2022-08-09 Monolithic 3D Inc. 3D semiconductor device with vias and isolation layers
US11476181B1 (en) 2012-04-09 2022-10-18 Monolithic 3D Inc. 3D semiconductor device and structure with metal layers
US11616004B1 (en) 2012-04-09 2023-03-28 Monolithic 3D Inc. 3D semiconductor device and structure with metal layers and a connective path
US11088050B2 (en) 2012-04-09 2021-08-10 Monolithic 3D Inc. 3D semiconductor device with isolation layers
US8557632B1 (en) 2012-04-09 2013-10-15 Monolithic 3D Inc. Method for fabrication of a semiconductor device and structure
US11694944B1 (en) 2012-04-09 2023-07-04 Monolithic 3D Inc. 3D semiconductor device and structure with metal layers and a connective path
US10600888B2 (en) 2012-04-09 2020-03-24 Monolithic 3D Inc. 3D semiconductor device
US11881443B2 (en) 2012-04-09 2024-01-23 Monolithic 3D Inc. 3D semiconductor device and structure with metal layers and a connective path
US11594473B2 (en) 2012-04-09 2023-02-28 Monolithic 3D Inc. 3D semiconductor device and structure with metal layers and a connective path
US11164811B2 (en) 2012-04-09 2021-11-02 Monolithic 3D Inc. 3D semiconductor device with isolation layers and oxide-to-oxide bonding
US11735501B1 (en) 2012-04-09 2023-08-22 Monolithic 3D Inc. 3D semiconductor device and structure with metal layers and a connective path
US8674470B1 (en) 2012-12-22 2014-03-18 Monolithic 3D Inc. Semiconductor device and structure
US11217565B2 (en) 2012-12-22 2022-01-04 Monolithic 3D Inc. Method to form a 3D semiconductor device and structure
US11018116B2 (en) 2012-12-22 2021-05-25 Monolithic 3D Inc. Method to form a 3D semiconductor device and structure
US11784169B2 (en) 2012-12-22 2023-10-10 Monolithic 3D Inc. 3D semiconductor device and structure with metal layers
US11063024B1 (en) 2012-12-22 2021-07-13 Monlithic 3D Inc. Method to form a 3D semiconductor device and structure
US11309292B2 (en) 2012-12-22 2022-04-19 Monolithic 3D Inc. 3D semiconductor device and structure with metal layers
US11916045B2 (en) 2012-12-22 2024-02-27 Monolithic 3D Inc. 3D semiconductor device and structure with metal layers
US9871034B1 (en) 2012-12-29 2018-01-16 Monolithic 3D Inc. Semiconductor device and structure
US10903089B1 (en) 2012-12-29 2021-01-26 Monolithic 3D Inc. 3D semiconductor device and structure
US11004694B1 (en) 2012-12-29 2021-05-11 Monolithic 3D Inc. 3D semiconductor device and structure
US11430667B2 (en) 2012-12-29 2022-08-30 Monolithic 3D Inc. 3D semiconductor device and structure with bonding
US10115663B2 (en) 2012-12-29 2018-10-30 Monolithic 3D Inc. 3D semiconductor device and structure
US10892169B2 (en) 2012-12-29 2021-01-12 Monolithic 3D Inc. 3D semiconductor device and structure
US9385058B1 (en) 2012-12-29 2016-07-05 Monolithic 3D Inc. Semiconductor device and structure
US11430668B2 (en) 2012-12-29 2022-08-30 Monolithic 3D Inc. 3D semiconductor device and structure with bonding
US10651054B2 (en) 2012-12-29 2020-05-12 Monolithic 3D Inc. 3D semiconductor device and structure
US11087995B1 (en) 2012-12-29 2021-08-10 Monolithic 3D Inc. 3D semiconductor device and structure
US11177140B2 (en) 2012-12-29 2021-11-16 Monolithic 3D Inc. 3D semiconductor device and structure
US10600657B2 (en) 2012-12-29 2020-03-24 Monolithic 3D Inc 3D semiconductor device and structure
US10325651B2 (en) 2013-03-11 2019-06-18 Monolithic 3D Inc. 3D semiconductor device with stacked memory
US11869965B2 (en) 2013-03-11 2024-01-09 Monolithic 3D Inc. 3D semiconductor device and structure with metal layers and memory cells
US11935949B1 (en) 2013-03-11 2024-03-19 Monolithic 3D Inc. 3D semiconductor device and structure with metal layers and memory cells
US8902663B1 (en) 2013-03-11 2014-12-02 Monolithic 3D Inc. Method of maintaining a memory state
US11398569B2 (en) 2013-03-12 2022-07-26 Monolithic 3D Inc. 3D semiconductor device and structure
US10840239B2 (en) 2014-08-26 2020-11-17 Monolithic 3D Inc. 3D semiconductor device and structure
US11923374B2 (en) 2013-03-12 2024-03-05 Monolithic 3D Inc. 3D semiconductor device and structure with metal layers
US8994404B1 (en) 2013-03-12 2015-03-31 Monolithic 3D Inc. Semiconductor device and structure
US11088130B2 (en) 2014-01-28 2021-08-10 Monolithic 3D Inc. 3D semiconductor device and structure
US9117749B1 (en) 2013-03-15 2015-08-25 Monolithic 3D Inc. Semiconductor device and structure
US10224279B2 (en) 2013-03-15 2019-03-05 Monolithic 3D Inc. Semiconductor device and structure
US11487928B2 (en) 2013-04-15 2022-11-01 Monolithic 3D Inc. Automation for monolithic 3D devices
US11574109B1 (en) 2013-04-15 2023-02-07 Monolithic 3D Inc Automation methods for 3D integrated circuits and devices
US9021414B1 (en) 2013-04-15 2015-04-28 Monolithic 3D Inc. Automation for monolithic 3D devices
US11341309B1 (en) 2013-04-15 2022-05-24 Monolithic 3D Inc. Automation for monolithic 3D devices
US11030371B2 (en) 2013-04-15 2021-06-08 Monolithic 3D Inc. Automation for monolithic 3D devices
US11270055B1 (en) 2013-04-15 2022-03-08 Monolithic 3D Inc. Automation for monolithic 3D devices
US11720736B2 (en) 2013-04-15 2023-08-08 Monolithic 3D Inc. Automation methods for 3D integrated circuits and devices
CN105264655B (zh) * 2013-06-25 2018-08-03 英特尔公司 具有局部层间互连的单片三维(3d)ic
TWI566328B (zh) 2013-07-29 2017-01-11 高效電源轉換公司 具有用於產生附加構件之多晶矽層的氮化鎵電晶體
KR102294507B1 (ko) * 2013-09-06 2021-08-30 가부시키가이샤 한도오따이 에네루기 켄큐쇼 반도체 장치
US10980273B2 (en) 2013-11-12 2021-04-20 VMR Products, LLC Vaporizer, charger and methods of use
US10039321B2 (en) 2013-11-12 2018-08-07 Vmr Products Llc Vaporizer
US9781953B2 (en) 2013-11-15 2017-10-10 Vmr Products Llc Vaporizer with cover sleeve
US11031394B1 (en) 2014-01-28 2021-06-08 Monolithic 3D Inc. 3D semiconductor device and structure
US10297586B2 (en) 2015-03-09 2019-05-21 Monolithic 3D Inc. Methods for processing a 3D semiconductor device
US11107808B1 (en) 2014-01-28 2021-08-31 Monolithic 3D Inc. 3D semiconductor device and structure
US9839238B2 (en) 2014-02-28 2017-12-12 Rai Strategic Holdings, Inc. Control body for an electronic smoking article
USD788697S1 (en) 2014-03-04 2017-06-06 VMR Products, LLC Battery portion for a vaporizer
USD763502S1 (en) 2014-03-04 2016-08-09 Vmr Products Llc Cartomizer for a vaporizer
USD752280S1 (en) 2014-03-07 2016-03-22 VMR Products, LLC Cartomizer for a vaporizer
USD752278S1 (en) 2014-03-07 2016-03-22 VMR Products, LLC Battery portion of a vaporizer
USD749505S1 (en) 2014-03-07 2016-02-16 VMR Products, LLC Charger for a vaporizer
USD804090S1 (en) 2014-04-08 2017-11-28 VMR Products, LLC Vaporizer with indicators
USD750320S1 (en) 2014-08-05 2016-02-23 VMR Products, LLC Vaporizer
US10825779B2 (en) 2015-04-19 2020-11-03 Monolithic 3D Inc. 3D semiconductor device and structure
US10381328B2 (en) 2015-04-19 2019-08-13 Monolithic 3D Inc. Semiconductor device and structure
US11056468B1 (en) 2015-04-19 2021-07-06 Monolithic 3D Inc. 3D semiconductor device and structure
US11011507B1 (en) 2015-04-19 2021-05-18 Monolithic 3D Inc. 3D semiconductor device and structure
US11956952B2 (en) 2015-08-23 2024-04-09 Monolithic 3D Inc. Semiconductor memory device and structure
US10034494B2 (en) 2015-09-15 2018-07-31 Rai Strategic Holdings, Inc. Reservoir for aerosol delivery devices
CN115942752A (zh) 2015-09-21 2023-04-07 莫诺利特斯3D有限公司 3d半导体器件和结构
US10522225B1 (en) 2015-10-02 2019-12-31 Monolithic 3D Inc. Semiconductor device with non-volatile memory
US11296115B1 (en) 2015-10-24 2022-04-05 Monolithic 3D Inc. 3D semiconductor device and structure
US10418369B2 (en) 2015-10-24 2019-09-17 Monolithic 3D Inc. Multi-level semiconductor memory device and structure
US11114464B2 (en) 2015-10-24 2021-09-07 Monolithic 3D Inc. 3D semiconductor device and structure
US10847540B2 (en) 2015-10-24 2020-11-24 Monolithic 3D Inc. 3D semiconductor memory device and structure
US11114427B2 (en) 2015-11-07 2021-09-07 Monolithic 3D Inc. 3D semiconductor processor and memory device and structure
US11937422B2 (en) 2015-11-07 2024-03-19 Monolithic 3D Inc. Semiconductor memory device and structure
US11282861B2 (en) * 2015-12-26 2022-03-22 Intel Corporation Dynamic logic built with stacked transistors sharing a common gate
US11302694B2 (en) * 2016-02-16 2022-04-12 Samsung Electronics Co., Ltd. Semiconductor device without a break region
US10062697B2 (en) * 2016-02-16 2018-08-28 Samsung Electronics Co., Ltd. Semiconductor device without a break region
KR102458660B1 (ko) 2016-08-03 2022-10-26 가부시키가이샤 한도오따이 에네루기 켄큐쇼 표시 장치 및 전자 기기
US10872820B2 (en) 2016-08-26 2020-12-22 Intel Corporation Integrated circuit structures
US10580735B2 (en) * 2016-10-07 2020-03-03 Xcelsis Corporation Stacked IC structure with system level wiring on multiple sides of the IC die
US11869591B2 (en) 2016-10-10 2024-01-09 Monolithic 3D Inc. 3D memory devices and structures with control circuits
US11251149B2 (en) 2016-10-10 2022-02-15 Monolithic 3D Inc. 3D memory device and structure
US11812620B2 (en) 2016-10-10 2023-11-07 Monolithic 3D Inc. 3D DRAM memory devices and structures with control circuits
US11711928B2 (en) 2016-10-10 2023-07-25 Monolithic 3D Inc. 3D memory devices and structures with control circuits
US11930648B1 (en) 2016-10-10 2024-03-12 Monolithic 3D Inc. 3D memory devices and structures with metal layers
US11329059B1 (en) 2016-10-10 2022-05-10 Monolithic 3D Inc. 3D memory devices and structures with thinned single crystal substrates
WO2018111247A1 (en) * 2016-12-13 2018-06-21 Intel Corporation Passivation dielectrics for oxide semiconductor thin film transistors
FR3082656B1 (fr) 2018-06-18 2022-02-04 Commissariat Energie Atomique Circuit integre comprenant des macros et son procede de fabrication
US11616057B2 (en) 2019-03-27 2023-03-28 Intel Corporation IC including back-end-of-line (BEOL) transistors with crystalline channel material
US11018156B2 (en) 2019-04-08 2021-05-25 Monolithic 3D Inc. 3D memory semiconductor devices and structures
US10892016B1 (en) 2019-04-08 2021-01-12 Monolithic 3D Inc. 3D memory semiconductor devices and structures
US11763864B2 (en) 2019-04-08 2023-09-19 Monolithic 3D Inc. 3D memory semiconductor devices and structures with bit-line pillars
US11158652B1 (en) 2019-04-08 2021-10-26 Monolithic 3D Inc. 3D memory semiconductor devices and structures
US11296106B2 (en) 2019-04-08 2022-04-05 Monolithic 3D Inc. 3D memory semiconductor devices and structures
US20210126096A1 (en) * 2019-10-24 2021-04-29 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. Integrated circuit
US11462282B2 (en) * 2020-04-01 2022-10-04 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor memory structure
CN111477623B (zh) * 2020-04-23 2023-06-16 浙江大学 三维堆叠的全透明微处理器
US11450605B2 (en) * 2021-02-11 2022-09-20 Taiwan Semiconductor Manufacturing Company, Ltd. Reducing internal node loading in combination circuits
KR20230043603A (ko) 2021-09-24 2023-03-31 한국전자통신연구원 산화물 반도체를 포함하는 sram 소자

Family Cites Families (35)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62190753A (ja) 1986-02-18 1987-08-20 Agency Of Ind Science & Technol 輪郭抽出用半導体装置
US4918510A (en) * 1988-10-31 1990-04-17 Motorola, Inc. Compact CMOS device structure
US5006913A (en) * 1988-11-05 1991-04-09 Mitsubishi Denki Kabushiki Kaisha Stacked type semiconductor device
JPH0660601B2 (ja) 1989-03-16 1994-08-10 モートン サイオコール，インコーポレイティド 複数推進薬固体ロケットエンジン
US5198379A (en) * 1990-04-27 1993-03-30 Sharp Kabushiki Kaisha Method of making a MOS thin film transistor with self-aligned asymmetrical structure
JPH0749534B2 (ja) 1990-05-10 1995-05-31 三井東圧化学株式会社 フタロシアニン化合物の製造方法
EP0469215B1 (en) 1990-07-31 1995-11-22 International Business Machines Corporation Method of forming stacked tungsten gate PFET devices and structures resulting therefrom
US5321280A (en) * 1990-09-13 1994-06-14 Nec Corporation Composite semiconductor integrated circuit device
JP3089657B2 (ja) * 1990-10-16 2000-09-18 ソニー株式会社 スタック型ｓｒａｍ
US5198683A (en) * 1991-05-03 1993-03-30 Motorola, Inc. Integrated circuit memory device and structural layout thereof
US5266511A (en) * 1991-10-02 1993-11-30 Fujitsu Limited Process for manufacturing three dimensional IC's
JP2689038B2 (ja) * 1991-12-04 1997-12-10 三菱電機株式会社 半導体装置およびその製造方法
JPH05275652A (ja) * 1992-01-30 1993-10-22 Sony Corp ポリシリコン薄膜トランジスタを備えるスタック型トランジスタ及びその製造方法
JP2742747B2 (ja) * 1992-05-29 1998-04-22 株式会社半導体エネルギー研究所 薄膜トランジスタを有する多層半導体集積回路
US5348899A (en) * 1993-05-12 1994-09-20 Micron Semiconductor, Inc. Method of fabricating a bottom and top gated thin film transistor
US5654915A (en) * 1993-08-19 1997-08-05 Cypress Semiconductor Corp. 6-bulk transistor static memory cell using split wordline architecture
US5825070A (en) * 1993-11-30 1998-10-20 Stmicroelectronics, Inc. Structure for transistor devices in an SRAM cell
JPH08167655A (ja) 1994-12-12 1996-06-25 Hitachi Ltd 半導体集積回路装置およびその製造方法
US5451534A (en) * 1994-12-14 1995-09-19 United Microelectronics Corporation Method of making single layer thin film transistor static random access memory cell
JPH0945922A (ja) 1995-07-27 1997-02-14 Showa Denko Kk 多結晶シリコン膜の形成方法
US5670812A (en) * 1995-09-29 1997-09-23 International Business Machines Corporation Field effect transistor having contact layer of transistor gate electrode material
US6005806A (en) * 1996-03-14 1999-12-21 Altera Corporation Nonvolatile configuration cells and cell arrays
KR100204419B1 (ko) * 1996-03-29 1999-06-15 김영환 반도체 소자의 제조방법
JP4103968B2 (ja) * 1996-09-18 2008-06-18 株式会社半導体エネルギー研究所 絶縁ゲイト型半導体装置
US5863818A (en) * 1996-10-08 1999-01-26 Advanced Micro Devices, Inc. Multilevel transistor fabrication method having an inverted, upper level transistor
US5770482A (en) * 1996-10-08 1998-06-23 Advanced Micro Devices, Inc. Multi-level transistor fabrication method with a patterned upper transistor substrate and interconnection thereto
KR100209750B1 (ko) * 1996-11-08 1999-07-15 구본준 씨모스 소자의 구조 및 제조방법
US6424011B1 (en) * 1997-04-14 2002-07-23 International Business Machines Corporation Mixed memory integration with NVRAM, dram and sram cell structures on same substrate
US5880991A (en) * 1997-04-14 1999-03-09 International Business Machines Corporation Structure for low cost mixed memory integration, new NVRAM structure, and process for forming the mixed memory and NVRAM structure
US5784311A (en) * 1997-06-13 1998-07-21 International Business Machines Corporation Two-device memory cell on SOI for merged logic and memory applications
US5888872A (en) * 1997-06-20 1999-03-30 Advanced Micro Devices, Inc. Method for forming source drain junction areas self-aligned between a sidewall spacer and an etched lateral sidewall
US5818069A (en) * 1997-06-20 1998-10-06 Advanced Micro Devices, Inc. Ultra high density series-connected transistors formed on separate elevational levels
US5949092A (en) * 1997-08-01 1999-09-07 Advanced Micro Devices, Inc. Ultra-high-density pass gate using dual stacked transistors having a gate structure with planarized upper surface in relation to interlayer insulator
US6271542B1 (en) 1997-12-08 2001-08-07 International Business Machines Corporation Merged logic and memory combining thin film and bulk Si transistors
US5953606A (en) * 1998-04-27 1999-09-14 Taiwan Semiconductor Manufacturing Company, Ltd. Method for manufacturing a TFT SRAM memory device with improved performance

Cited By (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100382319C (zh) * 2003-09-24 2008-04-16 株式会社东芝 静态随机存取存储器
CN100440513C (zh) * 2004-10-15 2008-12-03 中国科学院上海微系统与信息技术研究所 一种三维互补金属氧化物半导体器件结构的制备方法
US10720433B2 (en) 2009-10-29 2020-07-21 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
CN104733033A (zh) * 2009-10-29 2015-06-24 株式会社半导体能源研究所 半导体器件
CN104733033B (zh) * 2009-10-29 2018-03-02 株式会社半导体能源研究所 半导体器件
US9806079B2 (en) 2009-10-29 2017-10-31 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
CN104282691A (zh) * 2009-10-30 2015-01-14 株式会社半导体能源研究所 半导体装置
CN104716139A (zh) * 2009-12-25 2015-06-17 株式会社半导体能源研究所 半导体装置
CN103985760B (zh) * 2009-12-25 2017-07-18 株式会社半导体能源研究所 半导体装置
CN103985760A (zh) * 2009-12-25 2014-08-13 株式会社半导体能源研究所 半导体装置
CN104716139B (zh) * 2009-12-25 2018-03-30 株式会社半导体能源研究所 半导体装置
US9991265B2 (en) 2009-12-25 2018-06-05 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
US10553589B2 (en) 2009-12-25 2020-02-04 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
US11456296B2 (en) 2009-12-25 2022-09-27 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
US11825665B2 (en) 2009-12-25 2023-11-21 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
CN102487087A (zh) * 2010-12-01 2012-06-06 上海丽恒光微电子科技有限公司 应用于三维片上集成系统的薄膜晶体管及其制造方法
CN102487087B (zh) * 2010-12-01 2014-08-13 张家港丽恒光微电子科技有限公司 应用于三维片上集成系统的薄膜晶体管的制造方法
CN102486806A (zh) * 2010-12-03 2012-06-06 北京晶智意达科技有限公司 网表子电路多级交换信息的描述方法
CN111832245A (zh) * 2019-04-23 2020-10-27 三星电子株式会社 包括标准单元的集成电路及其制造方法及计算系统
CN114256245A (zh) * 2021-12-23 2022-03-29 波平方科技(杭州)有限公司 一种高密度静态随机存储器

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