CN1226776C - 具有双栅极氧化物层的半导体器件的制造方法 - Google Patents

具有双栅极氧化物层的半导体器件的制造方法 Download PDF

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CN1226776C
CN1226776C CNB021524254A CN02152425A CN1226776C CN 1226776 C CN1226776 C CN 1226776C CN B021524254 A CNB021524254 A CN B021524254A CN 02152425 A CN02152425 A CN 02152425A CN 1226776 C CN1226776 C CN 1226776C
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gate oxide
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CN1423306A (zh
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林宽容
赵兴在
朴大奎
车泰昊
吕寅硕
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SK Hynix Inc
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Abstract

本发明公开了一种具有双栅极氧化物层的半导体器件的制造方法，其包括步骤：a)在一半导体衬底上形成一栅极氧化物层；以及b)通过进行退耦等离子体处理，增加部分栅极氧化物层的厚度。因为双栅极氧化物层是用退耦等离子体形成的，所以不需要额外的热处理。此外，因为硅衬底没有损伤，所以可以确保半导体器件的沟道特性。此外，因为在没有额外的沟道离子注入的情况下单元区内的阈值电压增加，所以半导体器件的电特性可提高。

Description

具有双栅极氧化物层的半导体器件的制造方法
技术领域
本发明涉及一种制造双栅极氧化物层的方法，尤其涉及一种制造具有双栅极氧化物层的半导体器件的方法。
背景技术
通常，由热处理生长的二氧化硅SiO2层用于栅极氧化物层。半导体器件设计中一般倾向于栅极氧化物层的厚度低于25埃至30埃的范围，这是SiO2层的最大隧穿极限。
然而，由于刷新，单元中的阈值电压Vt高于周围电路中的阈值电压Vt。因此，需要向单元晶体管施加高的栅极电压，使得电性能不会劣化。
为了提高单元晶体管的性能，需要将双栅极氧化物形成方法应用于单元晶体管，以增加栅极氧化物层的厚度。
在形成双栅极氧化物层的若干技术中，广泛采用两种方法。一种是：通过在某部分上去除栅极氧化物层来形成双栅极氧化物层，然后再次氧化和形成双栅极氧化物层。另一种方法包括通过在某部分上离子注入氮以延缓栅极氧化物层的生长来形成双栅极氧化物层。
然而，第一种方法具有缺点，即，因为对半导体施行两次高温热处理以形成双栅极氧化物层，所以半导体衬底受损。第二种方法具有类似的问题，即半导体衬底因离子注入氮而受损。
尤其是当半导体衬底受损后，导致沟道迁移率的下降。
发明内容
本发明的目的是提供一种形成双栅极氧化物层的新方法。
根据一实施例，形成双栅极氧化物层的方法包括：a)在半导体衬底上形成栅极氧化物层；以及b)通过进行退耦等离子体处理来增加部分栅极氧化物层的厚度，其中，在退耦等离子体处理过程中，将100W至1000W范围内的一RF电源功率施加一在5秒到300秒的范围内的时间段，以及退耦等离子体处理以包括氮元素的气体、包括氧元素的气体和包括卤素元素的气体来进行。
根据本发明的另一实施例，制造半导体器件的方法包括步骤：a)在半导体衬底上形成栅极氧化物层，其中在该半导体衬底上定义有一单元区和一周边电路区；b)对单元区中的部分栅极氧化物层进行退耦等离子体处理，从而增加其厚度；c)在单元区和周边电路区的每个栅极氧化物层上形成栅电极；以及d)在栅电极的半导体衬底上形成源极/漏极区，其中，在RF电源功率在100W到1000W的范围内且处理持续时间在5秒到300秒的范围内的条件下，以包括氮元素的气体、包括氧元素的气体和包括卤素元素的气体来施行该退耦等离子体处理。
附图说明
通过以下结合附图对优选实施例进行的说明，所公开的方法的以上和其它特征将变得清晰，其中：
图1A和1B是说明形成双栅极氧化物层的方法的横截面视图；
图2A至2D是说明形成半导体器件的方法的横截面视图；
图3是一MOS电容器的C-V特性曲线的曲线图，该电容器经历了氧化硅层上进行的DPN处理；
图4是一MOS电容器的统计数据分布表，该电容器经历了氧化硅层上进行的DPN处理；以及
图5是一MOS电容器的栅极漏电流特性曲线的曲线图，该电容器经历了氧化硅层上进行的氮气退耦等离子体处理。
具体实施方式
以下，将参照附图详细说明制造具有双栅极氧化物层的半导体器件的新方法。
图1A和1B是说明形成双栅极氧化物层的方法的横截面视图。退耦等离子体装置用于形成双栅极氧化物层。常规等离子体蚀刻工具利用一种被称作电源功率(source power)的单一功率，晶片电接地；或者，晶片可以连接电源功率，而反应室电接地。等离子体蚀刻工具控制电源功率并影响产生多少等离子体，还控制反应物的浓度，因此控制反应物有多少落在晶片上。
在退耦等离子体源蚀刻机中，功率被分成电源功率，该电源功率是供给至反应室壁的高功率。另一功率被连接到晶片，这被称作偏置功率(biaspower)或基本功率(bottom power)。该电源功率将供给到反应室中的气体电离，并在反应室中产生反应物。晶片上的偏置功率驱动反应物以加速该反应。因此，对蚀刻工艺有更多的控制：电源功率控制化学物质的产生，并因此控制化学蚀刻部分；以及偏置功率控制蚀刻的物理部分，例如物质轰击晶片。
参照图1A，氧化硅层12形成在硅衬底11上，且氧化硅层12的一部分经受氮气退耦等离子体处理(decoupled plasma treatment with nitrogen)，以下称作DPN。此时，掩模可利用光致抗蚀剂形成在氧化硅层12上，以暴露部分氧化硅层12。
在DPN中，硅衬底11保持在以下条件下：温度在约0℃至约500℃范围内，压力在约10mtorr至约30mtorr之间，且所注入的N2气的流速在约10sccm至约500sccm范围内。在注入N2气之后，约100W至约1000W的RF电源功率得以施加一约5秒至约300秒之间的时间周期。
然而，以下气体可用于替换N2气，该气体包括：诸如NH3、N2O和NO的包含N元素的气体；诸如Cl2、BCl3、CF4、CHF3、C2F6、BF2、F2、NF3、SF6、HBr、Br2和I2的包含卤素元素的气体；诸如O2、O3和H2O的包含O元素的气体；或这些元素的组合。
如果这些元素中的氟元素系列用在DPN中，则还可以希望得到对栅极氧化物层的完整性和热载流子性能的改进。
在DPN之后，在约100℃至约900℃范围的一个温度下，在N2、Ar气氛中或在真空中，持续一段时间地加热氧化硅层12，该时期在约1分钟到约30分钟范围内。
参见图1B，经历了DPN处理的氧化硅层12的一部分的厚度比起始氧化硅层12的厚度增加了d。
厚度增加的原因在于，氮N在DPN过程中扩散到氧化硅层12中，使得氮N与具有O-Si-O键的氧化硅层12中的弱键和悬空键(dangling bond)结合。
即，弱的Si-O键被氮N打开以取代氧，因此，自由氧扩散到硅衬底11和氧化硅层12的表面中。之后，发生额外的氧化，使得氧化硅层的厚度增加。
根据图1A和1B，虽然施加了高电压，但是可以确保栅极氧化物层的足够厚度。此外，半导体衬底的损失可以减小，因为栅极氧化物层既不是通过对半导体进行热处理而形成的，也不是由离子注入氮获得的。
图2A至2D是横截面视图，示出根据另一实施例形成半导体器件的方法。
参照图2A，分隔器件的有源区和场区的场氧化层22形成在半导体衬底21上，该衬底上定义了一单元区I和一周边电路区II。为了形成场氧化层22，蚀刻半导体衬底21以形成槽。之后，在该槽中形成氧化层，以形成场氧化层22。这被称为形成场氧化层22的浅槽隔离STI方法。然而，硅LOCOS方法中的局部氧化可用于形成场氧化层22。
在半导体衬底21的有源区上生长第一薄氧化硅层SiO2 23，以形成栅极氧化物层。除了第一氧化硅层23外，还可以使用其它的层，例如氮氧化硅层SiON，高氧化物金属氧化物层(high oxide metal oxide layer)Al2O3、Ta2O5、HfO2或ZrO2，高氧化物金属氧化物层和高氧化物金属氧化物层的铪(Hf)硅酸盐或锆(Zr)硅酸盐的混合层，以及具有高氧化物金属氧化物层纳米叠层结构的高氧化物层。这样的栅极氧化物层的厚度在约5埃到约100埃的范围内变化。
在图2B中，在具有第一氧化硅层23的半导体衬底21上涂敷光致抗蚀剂。之后，形成第一光致抗蚀剂构图14以暴露单元区I。
将第一光致抗蚀剂构图14用作掩模，对单元区I中的第一氧化硅层23施行DPN。
此时，硅衬底14保持在约0℃至约500℃的范围内的一温度，在约10mtorr至约30mtorr范围内的一压力下，并且N2气以约10sccm至约500sccm范围内的一流速注入。在注入N2气后，在约100W至约1000W范围内的一RF电源功率得以施加在约5秒至约300秒的范围内的一时间段。
然而，以下气体可用于替换N2气，该气体包括：诸如NH3、N2O和NO的包括N元素的气体；诸如Cl2、BCl3、CF4、CHF3、C2F6、BF2、F2、NF3、SF6、HBr、Br2和I2的包含卤素元素的气体；诸如O2、O3和H2O的包含O元素的气体；或这些元素的组合。
如果这些元素中的氟元素系列与DPN一起使用，则还可以额外得到对栅极氧化物层的完整性和热载流子性能的改进。
在进行DPN之后，在约100℃至约900℃之间的一个温度下，在N2、Ar气氛中或在真空中，持续一时期地加热第一氧化硅层23，该时期在约1分钟到约30分钟之间。
参照图2C，第一氧化硅层23的厚度在DCP后增加，且其被称作第二氧化硅层25。
厚度增加的原因在于，氮N在DPN过程中扩散到第一氧化硅层23中，使得氮N与具有O-Si-O键的氧化硅层中的弱键和悬空键结合。即，弱键Si-O被氮N切断以取代氧，因此，自由氧扩散到硅衬底21和第一氧化硅层23的表面。之后，发生额外的氧化，使得氧化硅层厚度增加。
在形成第二氧化硅层25后，去除半导体衬底21上的第一光致抗蚀剂构图14。顺序叠放掺杂多晶硅26和低电阻金属层27以具有约50埃至约2000埃范围内的一总厚度，从而形成栅电极。
此时，其上分别顺序叠放了金属氮化物和金属氮化物/硅化物的一金属层用于低电阻金属层27。
此外，n+多晶硅用于掺杂多晶硅26，该n+多晶硅具有约4.1eV到约4.2eV范围内的功函数。对于低电阻金属层27的氮金属，使用TiN、TaN、WN、TiSiN、TiAlN、TiBN、ZrSiN、ZrAlN、MoSiN、MoAlN、RuTiN、RuTaN、IrTiN、TaSiN或TaAlN。对于硅化物元素，使用WSi、CoSi、CoSi、TiSi、MoSi、TaSi或NbSi。
然而，多晶硅和金属氮化物的厚度在约10埃至约2000埃范围内变化。其中堆叠了硅化物的叠层用于减小栅电极的电阻，且硅化物的厚度在约50埃至约2000埃的范围内变化。
接着，在低电阻金属层27上涂敷光致抗蚀剂，并形成第二光致抗蚀剂构图28。
参见图2D，通过将第二光致抗蚀剂构图28用作蚀刻掩模来蚀刻低电阻金属层27和掺杂多晶硅26，使得在单元区I和周边电路区II中形成每个晶体管的栅电极。
在去除第二光致抗蚀剂构图28后，通过间隔壁形成和杂质注入工艺形成具有LDD结构的源极/漏极。形成氧化物层以将每个晶体管绝缘，且施行金属化工艺以连接源极、漏极和栅电极到外部器件。
如果仅在单元区I中施行DPN以形成双栅极氧化物，则单元区I中的栅极氧化物层可以形成得其厚度比周边电路区II中的栅极氧化物层厚约2埃至约10埃。
因此，尽管施加了高电压，但是可获得栅极氧化物层的足够厚度。此外，单元区I中在经历了DPN处理的栅极氧化物层上形成的晶体管具有比周边电路区II中的晶体管高的阈值电压Vt，该阈值电压在约+0.4V到约+0.5V之间。该阈值电压Vt可以通过对单元施加注入工艺而调节。
图3是根据本发明该另一实施例的、经历了在氧化硅层上进行的DPN处理的MOS电容器的C-V特性曲线的曲线图。图3中，如果施加了DPN，则与形成在无DPN处理的氧化硅层上的MOS晶体管相比，该阈值电压Vt增加到约+0.4V到约+0.5V的范围。
相应地，可以通过本发明避免过度的沟道离子注入。
图4是根据本发明该另一实施例的、经历了氧化硅层上进行的DPN处理的MOS电容器的统计数据分布图。图4中，如果施行了DPN，则电厚度(electrical thickness)根据处理时间和电源等离子体功率而增加。
参见图4，与未施行DPN的情形相比，电厚度(以下称为CET)在500W-18秒的工艺情形下增加达2埃。在500W-35秒的工艺情形下，CET增加达5埃，而在700W-35秒的情形下，CET增加达10埃。
图5是根据本发明该另一实施例的、经历了在氧化硅层上进行的氮退耦等离子体处理的MOS电容器的栅极漏电流特性曲线的曲线图。图5中，虽然电厚度增加了，但是无论是否施行了DPN处理，漏电流的下降也没有发现。
以上方法不仅可用于具有层叠结构的双栅极氧化物层的CMOS器件，还可用于具有双镶嵌结构的CMOS器件。此外，以上方法可用于具有三栅极氧化物层的半导体器件。
因为双栅极氧化物层是用退耦等离子体形成的，所以不需要额外的热处理。此外，因为硅衬底没有损伤，所以可以确保半导体器件的沟道特性。此外，因为在没有额外的沟道离子注入的情况下单元区内的阈值电压增加，所以半导体器件的电特性可提高。
虽然本发明已参照具体实施例进行了说明，但是对本领域技术人员清楚的是，在不脱离本发明的如所附权利要求所确定的精髓和范围的情况下，可作各种变化和更改。

Claims (14)

1.一种形成双栅极氧化物层的方法，包括：
a)在一半导体衬底上形成一栅极氧化物层；以及
b)通过进行退耦等离子体处理，增加部分栅极氧化物层的厚度，
其中，在退耦等离子体处理过程中，将100W至1000W范围内的一RF电源功率施加一在5秒到300秒的范围内的时间段，以及
退耦等离子体处理以包括氮元素的气体、包括氧元素的气体和包括卤素元素的气体来进行。
2.如权利要求1所述的方法，其中，在退耦等离子体处理过程中，该半导体衬底保持在0℃到500℃范围内的一温度下。
3.如权利要求1所述的方法，其中，退耦等离子体处理在10mtorr至30mtorr的范围内的一压力下进行。
4.如权利要求1所述的方法，其中，在退耦等离子体处理过程中，以10sccm到500sccm范围内的一流速注入N2气体。
5.如权利要求1所述的方法，其中，包含氮元素的气体为选自NH3、N2O和NO构成的组中的一种物质。
6.如权利要求1所述的方法，其中，包含氧元素的气体是选自O2、O3和H2O构成的组中的一种物质。
7.如权利要求1所述的方法，其中，包含卤素元素的气体是选自Cl2、BCl3、CF4、CHF3、C2F6、BF2、F2、NF3、SF6、HBr、Br2和I2构成的组中的一种物质。
8.如权利要求1所述的方法，还包括在退耦等离子体处理中，将该半导体衬底加热到一温度持续一时期，该温度在100℃至900℃之间，该时期在1分钟至30分钟之间。
9.如权利要求1所述的方法，在进一步利用氮气施行退耦等离子体处理之前，该栅极氧化物层堆叠至5埃到100埃范围内的一厚度。
10.如权利要求1所述的方法，其中，栅极氧化物层是选自氧化硅层、Al2O3、Ta2O5、HfO2、ZrO2、Hf-硅酸盐、Zr-硅酸盐和具有高氧化物金属氧化物层纳米叠层结构的高氧化物层构成的组中的一种物质。
11.一种制备半导体器件的方法，包括：
a)在包括单元区和周边电路的半导体衬底上形成栅极氧化物层；
b)对栅极氧化物层在单元区中的部分施行退耦等离子体处理，从而增加其厚度；
c)在单元区的栅极氧化物层上形成栅电极，并在周边电路区的栅极氧化物层上形成栅电极；以及
d)在半导体衬底上形成源极/漏极区，
其中，在RF电源功率在100W到1000W的范围内且处理持续时间在5秒到300秒的范围内的条件下，以包括氮元素的气体、包括氧元素的气体和包括卤素元素的气体来施行该退耦等离子体处理。
12.如权利要求11所述的方法，其中，施行退耦等离子体处理的步骤包括：
a)在栅极氧化物层上形成光致抗蚀剂；
b)通过构图光致抗蚀剂形成掩模图案，以暴露单元区中的栅极氧化物层；以及
c)将掩模图案用作氧化掩模来进行退耦等离子体处理。
13.如权利要求12所述的方法，其中，在以下条件下在半导体衬底上进行退耦等离子体处理，该条件为：温度在0℃到500℃的范围内，压力在10mtorr到30mtorr的范围内。
14.如权利要求11所述的方法，其中，包含卤素元素的气体是选自Cl2、BCl3、CF4、CHF3、C2F6、BF2、F2、NF3、SF6、HBr、Br2和I2构成的组中的一种物质。
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