CN1232291A - 铜互连结构及其制作方法 - Google Patents

铜互连结构及其制作方法 Download PDF

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CN1232291A
CN1232291A CN99104925A CN99104925A CN1232291A CN 1232291 A CN1232291 A CN 1232291A CN 99104925 A CN99104925 A CN 99104925A CN 99104925 A CN99104925 A CN 99104925A CN 1232291 A CN1232291 A CN 1232291A
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拉比尔·伊斯拉姆
阿乌格里诺斯·V·格拉特斯
克文·卢卡斯
斯坦利·M·费里皮克
拉纳思·温卡特拉曼
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Abstract

在一个实施例中,用在半导体衬底(10)上淀积介电层(28)的方法制作铜互连结构。然后对此介电层(28)进行图形化以形成互连窗口(29)。再在互连窗口(29)中制作铜层(34)。然后清除一部分铜层(34)以便在互连窗口(29)中形成铜互连(39)。再在铜互连(39)上制作铜势垒层(40)。借助于将铜互连(39)的暴露表面暴露于只用氨作为源气体而产生的等离子体,改善了铜势垒层(40)与铜互连(39)之间的粘附性。

Description

铜互连结构及其制作方法
本发明一般涉及到半导体器件，更具体地说是涉及到半导体器件中的铜互连结构及其制作方法。
在半导体工业中，通常是用铝制作导电互连。但为了满足新型半导体器件对速度的要求，需要电阻比铝更低的导电互连。由于铜的电阻比较低，最近已提出用铜来代替传统的铝互连。铜不象铝，在目前用来制造半导体器件的很多材料中，铜是非常容易迁移的。因此，在半导体器件中使用铜互连时，要求使用铜的势垒层以防止半导体器件中不希望有的铜扩散。然而，势垒层对铜互连的粘附性是成问题的，常常引起半导体器件失效。因此，需要有一种合金化工艺能够使半导体器件更可靠地用铜互连加以制造。
图1-7剖面图示出了根据本发明实施例的工艺步骤。
图1所示是根据本发明实施例的半导体器件结构部分5。此半导体器件结构包含半导体衬底10、场隔离区12、晶体管14、导电塞24、介电层22、腐蚀停止层26和介电层28。晶体管14包含源/漏区16、栅介电层18和栅电极20。在一个实施例中，半导体衬底10是单晶硅衬底。作为变通，半导体衬底10可以是绝缘体上硅衬底、蓝宝石上硅衬底之类。
在一个实施例中，场隔离区12是用常规腐蚀和化学机械抛光技术制作的沟槽隔离区，作为变通，场隔离区12可以是用诸如硅的局部氧化(LOCOS)、多晶缓冲LOCOS(PBL)、多晶硅包封局部氧化(PELOX)之类的常规技术制作的场氧化区。
在一个实施例中，栅介电层18是用对半导体衬底10的一部分进行热氧化而制作的热氧化硅层。作为变通，栅介电层18可以是氮化硅层、氮氧化硅层、化学汽相淀积的二氧化硅层、氮化氧化物层、或它们的组合。
在一个实施例中，栅电极20是多晶硅层。作为变通，栅电极20可以是钨或钼之类的金属层、氮化钛或氮化钨之类的金属氮化物层、或它们的组合。此外，栅电极20可以是多晶硅层上的多硅化物(polycide)层，包含诸如硅化钨、硅化钛或硅化钴之类的金属硅化物层。
在一个实施例中，介电层22是用TEOS作为源气体制作的等离子体淀积的氧化物层。作为变通，介电层22可以是氮化硅层、PSG层、BPSG层、SOG层、氮氧化硅层、聚酰亚胺层、或它们的组合。
在一个实施例中，用钛/氮化钛势垒层和钨接触填充来制作导电塞24。在淀积钨部分之后，用常规腐蚀或化学机械抛光技术清除下方的钛/氮化钛势垒层以形成导电塞24。作为变通，可以用多晶硅作为接触填充材料来制作导电塞24。
在一个实施例中，腐蚀停止层26是用常规等离子体淀积技术制作的氮氧化硅层。作为变通，腐蚀停止层26可以是等离子体淀积的氮化硅层、氮化硼层等。
在一个实施例中，介电层28是用TEOS作为源气体制作的等离子体淀积的氧化物层。作为变通，介电层28可以是氮化硅层、PSG层、BPSG层、SOG层、氮氧化硅层、聚酰亚胺层等等。此外，上述各个介电材料的组合也可以用来制作介电层28。
在图2中，清除了部分介电层28和部分腐蚀停止层26，以便暴露部分导电塞24并制作互连窗口29。然后在互连窗口29中制作导电势垒层30。在一个实施例中，导电势垒层30是氮化钽层。作为变通，导电势垒层30可以是氮化钛层、氮化钨层、氮化钽硅层、钽层、钛钨层(TiW)等等。可以用常规溅射或化学汽相淀积技术来淀积导电势垒层30。
然后在导电势垒层30上制作第一铜层32。如图2所示，第一铜层32的厚度不足以填充互连窗口29。在一个实施例中，用溅射淀积工艺来淀积第一铜层32。作为变通，可以用化学汽相淀积工艺来制作第一铜层32。
然后，用电镀工艺在第一铜层32上制作第二铜层34。如图2所示，第二铜层的厚度足以填充互连窗口29。在一个实施例中，用含有铜(Cu)、硫酸铜(Cu2SO4)、硫酸(H2SO4)、和诸如来自盐酸(HCl)的氯离子的电解液来淀积第二铜层34。在此特定的实施例中，如授予本申请受让人的美国专利申请08/856459所述，为了改善铜电镀的均匀性，在铜电镀过程中，对半导体衬底边沿附近的电流密度进行了修正。此处将美国专利申请08/856459的主要内容列为参考。作为变通，可以用其他电镀技术和其他电镀溶液来制作第二铜层34。此外，可以用诸如化学汽相淀积之类的其他技术来制作第二铜层34。
在图3中，为了在互连窗口29中制作铜互连39，清除了部分第二铜层34、第一铜层32和导电势垒层30，其中铜互连39包含导电势垒层30的剩余部分36、第一铜层32的剩余部分37和第二铜层34的剩余部分38。在导电势垒层30包含钛、钨或钽的特定实施例中，可以如授予本申请受让人的美国专利申请08/954190所述，用使用含有过氧化氢、柠檬酸铵、氧化铝、1,2,4-三唑和去离子水的抛光胶的化学机械抛光工艺来制作铜互连39。此处将美国专利申请08/954190的主要内容列为参考。作为变通，可以用诸如离子束研磨、反应离子束刻蚀和等离子体腐蚀之类的常规技术，或用腐蚀与抛光技术的组合来制作铜互连39。
然后在铜互连39上制作含有硅和氮的铜势垒层40。铜势垒层40被用来防止铜互连39中的铜原子扩散进入随后淀积在铜互连39上的介电层中。在一个实施例中，铜势垒层40对365nm或更短的光刻胶曝光波长的吸收系数(k)在大约0.0-0.15的范围内。更具体地说，铜势垒层40在365nm和248nm的光刻胶曝光波长下的吸收系数(k)在大约0.0-0.15的范围内。
为了改善铜互连39与铜势垒层40之间的粘附性，铜互连39被暴露于含氢的无硅的等离子体中。用馈送到等离子体室的一种或多种无硅源气体来产生含氢的无硅等离子体。例如，在一个实施例中，只用氨(NH3)作为产生主要由氢和氮组成的等离子体的源气体来产生含氢的无硅等离子体。在此特定的实施例中，主要由氢和氮组成的等离子体在下列条件下产生：淀积压力约为8.0乇；氨的流速约为400sccm；射频功率约为200W；间距约为650密尔；而淀积温度约为400℃。作为变通，可以只用氢(H2)作为源气体，或用氢与诸如氮(N2)、氦(He)或氩(Ar)之类的惰性源气体的组合来产生含氢的无硅等离子体。据信，等离子体工艺从铜互连39的暴露表面清除了能够使铜势垒层40与铜互连39之间的粘附性变差的氧化铜。具体地说，据信等离子体中的氢与铜互连表面上的氧化铜反应，形成挥发性水而被抽走，而等离子体中的氮借助于撞击铜表面而有助于氧化铜的还原。此外，借助于在与随后淀积铜势垒层相同的工作室中执行清洗工序，清洗过的铜表面在淀积之前不再暴露于空气因而不再被氧化。必须指出的是，上述的等离子体工序改善了粘附性而不使铜互连的电阻变差，也不使相邻铜互连之间的漏电流变大。
在一个实施例中，铜势垒层40是氮氧化硅(SixOyNz)层。在此特定的实施例中，在安装有DXZ工作室的Applied Materials Centure等离子体淀积系统中，采用下列淀积条件来制作铜势垒层40：淀积压力约为5.0乇；硅烷流速约为73sccm；笑气流速约为92sccm；氮气流速约为3900sccm；射频功率约为500W；间距约为475密尔；淀积温度约为400℃。在约为365nm的光刻胶曝光波长下，上述氮氧化硅层的折射率约为1.66而吸收系数约为0.0。
在一个变通实施例中，铜势垒层40是等离子体淀积的氮化硅(SixNy)。在此特定的实施例中，在安装有DXZ工作室的AppliedMaterials Centure等离子体淀积系统中，采用下列淀积条件来制作铜势垒层40：淀积压力约为5.0乇；硅烷流速约为100sccm；氨流速约为140sccm；氮气流速约为4000sccm；射频功率约为450W；间距约为610密尔；淀积温度约为400℃。在约为365nm的光刻胶曝光波长下，上述氮化硅层的折射率约为2.05而吸收系数约为0.0。
必须指出的是，由于粘附于铜互连39，且由于对铜互连39的电阻或相邻的镶嵌铜互连之间的漏电流没有不利的影响，故铜势垒层40可以与镶嵌的铜金属化可靠地集成。具体地说，已经发现，在相距约为2400埃的镶嵌铜互连之间的漏电流，在被铜势垒层40覆盖时，小于1毫微安。这样，本发明也使得能够用铜互连来制造漏电流小的半导体器件。
在一个实施例中，在临近铜势垒层40处制作含硅和氮的抗反射层41。抗反射层的厚度范围为大约5nm到大约100nm。抗反射层41对365nm或更短的光刻胶曝光波长的吸收系数(k)在大约0.2-1.0的范围内。具体地说，抗反射层41在365nm和248nm的光刻胶曝光波长下的吸收系数(k)在大约0.2-1.0的范围内。于是，对于相同的光刻胶曝光波长，铜势垒层40的吸收系数就小于抗反射层41的吸收系数。
在一个实施例中，抗反射层41是氮氧化硅(SixOyNz)层。在此特定的实施例中，在安装有DXZ工作室的Applied Materials Centure等离子体淀积系统中，采用下列淀积条件来制作抗反射层41：淀积压力约为5.0乇；硅烷流速约为300sccm；笑气流速约为92sccm；氮气流速约为3900sccm；射频功率约为520W；间距约为475密尔；淀积温度约为400℃。在约为365nm的光刻胶曝光波长下，上述氮氧化硅层的折射率约为2.8而吸收系数约为0.3。
应该理解的是，借助于调整各自的淀积工艺，可以分别剪裁铜势垒层40和抗反射层41的光学性能。例如，若将上面讨论的用来淀积抗反射层41的硅烷的流速改变成约为330sccm，则在约为365nm的光刻胶曝光波长下，氮氧化硅层的吸收系数约为0.40。由于较高的硅烷流速提高了氮氧化硅层中的硅浓度，故抗反射层41的吸收系数增大。同样，降低硅烷流速会降低氮氧化硅层中的硅浓度，从而降低吸收系数。因此，能够独立地剪裁抗反射层41和铜势垒层40的光学性能。例如，能够将铜势垒层40制成其硅浓度低于抗反射层41的硅浓度，从而对于相同的光刻胶曝光波长，铜势垒层40可以具有比抗反射层41更小的吸收系数。此外，应该指出的是，硅、氧和氮之外的组分可以包括在用来制作铜势垒层40和抗反射层41的氮氧化硅层中。而且，硅和氮之外的组分可以包括在用来制作铜势垒层40的氮化硅层中。例如，在这些氮化物层中可以有氢。
在抗反射层41上制作层间介电层48。在一个实施例中，如图4所示，层间介电层48包含介电层42、腐蚀停止层44和介电层46。
介电层42可以是用TEOS作为源气体淀积的等离子体淀积氧化物层。作为变通，介电层42可以是PSG层、BPSG层、SOG层、聚酰亚胺层、低介电常数绝缘体等等。
腐蚀停止层44可以是等离子体淀积的氮氧化硅层。作为变通，腐蚀停止层44可以是等离子体淀积的氮化硅层、氮化硼层等等。
介电层46可以是用TEOS作为源气体制作的等离子体淀积的氧化物层。作为变通，介电层46可以是PSG层、BPSG层、SOG层、聚酰亚胺层、低介电常数绝缘体等等。应该理解的是，层间介电层48不必用不同的介电材料来制作。例如，可以用诸如等离子体淀积的氧化物、PSG、BPSG、SOG、聚酰亚胺、低介电常数绝缘体之类的单一介电材料来制作层间介电层48。
然后在介电层48上制作光刻胶掩模51。用具有选定的光刻胶曝光波长，例如365nm或248nm的电磁辐照来制作光刻胶掩模51。需要指出的是，抗反射层41降低了光刻胶掩模51中在高反射性铜互连39上的光刻胶被光刻曝光时能够出现的反射切口。然后如图5所示，用光刻胶掩模51来使部分下方介电层48图形化。更具体地说，部分介电层46和腐蚀停止层44被清除，以便在介电层48中形成互连窗口52。在形成互连窗口52之后，清除光刻胶掩模51。
在图6中，在介电层48上制作光刻胶掩模53。用具有选定的光刻胶曝光波长(例如365nm或248nm)的电磁辐照来制作光刻胶掩模53。需要指出的是，抗反射层41降低了光刻胶掩模53中在高反射性铜互连39上的光刻胶被光刻曝光时能够出现的反射切口。然后如图6所示，用光刻胶掩模53来使部分下方介电层48图形化。更具体地说，部分介电层42、抗反射层41和铜势垒层40被清除，以便形成暴露部分铜互连39的通道窗口54。这也导致在介电层48中形成双重镶嵌窗口50，其中双重镶嵌窗口50包含互连部分52和通道部分54。在介电层48中制作双重镶嵌窗口50之后，清除光刻胶掩模53。
然后，在图7中，在双重镶嵌窗口50中制作第二导电势垒层。在一个实施例中，第二导电势垒层是氮化钽层。作为变通，第二导电势垒层可以是氮化钛层、氮化钨层、氮化钽硅层、钽层、钛钨层(TiW)等等。可以用常规溅射或化学汽相淀积技术来淀积第二导电势垒层。
然后，在第二导电势垒层上制作第三铜层。如图7所示，第三铜层的厚度不足以填充双重镶嵌窗口50。在一个实施例中，用溅射淀积工艺来制作第三铜层。作为变通，可以用化学汽相淀积工艺来制作第三铜层。
然后用电镀工艺来制作第三铜层上的第四铜层。第四铜层的厚度足以填充双重镶嵌窗口50。在一个实施例中，用含有铜(Cu)、硫酸铜(Cu2SO4)、硫酸(H2SO4)、和诸如来自盐酸(HCl)的氯离子的电解液来淀积第四铜层。在此特定的实施例中，如授予本申请受让人的美国专利申请08/856459所述，为了改善铜电镀的均匀性，在铜电镀过程中，对半导体衬底边沿附近的电流密度进行了修正。此处将美国专利申请08/856459的主要内容列为参考。作为变通，可以用其他电镀技术和其他电镀溶液来制作第四铜层。此外，可以用诸如化学汽相淀积之类的其他技术来制作第四铜层。
为了在双重镶嵌窗口50中制作铜互连62，清除部分第四铜层、第三铜层和第二导电势垒层，其中铜互连62包含第二导电势垒层的剩余部分57、第三铜层的剩余部分59和第四铜层的剩余部分60。在第二导电势垒层包含钛、钨或钽的特定实施例中，可以如授予本申请受让人的美国专利申请08/954190所述，用使用含有过氧化氢、柠檬酸铵、氧化铝、l,2,4-三唑和去离子水的抛光胶的化学机械抛光工艺来制作铜互连62。此处将美国专利申请08/954190的主要内容列为参考。作为变通，可以用诸如离子束研磨、反应离子束刻蚀和等离子体腐蚀之类的常规技术，或用腐蚀与抛光技术的组合来制作铜互连62。
然后，如前面图3所述，在铜互连62上制作含有硅和氮的铜势垒层64。若不需要更多的互连层，则铜势垒层64用作器件的最后钝化层，并且通过它随后制作键合焊点窗口(未示出)。作为变通，若需要更多的互连层，则重复图3到图7所述的步骤。
于是，根据本发明，显然已经提供了一种能够用铜互连可靠地制造半导体器件的合金化工艺。虽然参照具体的实施例已经描述了本发明，但不意味着本发明局限于这些实施例。本技术领域熟练人员知道，可以作出各种修正和改变而不超越本发明的构思与范围。因此，本发明包含所附权利要求范围内的所有改变和修正。

Claims (5)

1．一种在半导体器件中制作铜互连结构的方法，其特征是下列步骤：
提供半导体衬底；
在半导体衬底上制作介电层；
对介电层进行图形化，以便在介电层中制作窗口；
在半导体衬底上制作铜层，此铜层位于窗口中；
对铜层进行抛光，以便在窗口中制作铜互连，此铜互连具有上表面；
将铜互连暴露于以氢为特征的等离子体，以便从铜互连的上表面清除氧化铜并形成清洁的铜表面；以及
在清洁的铜表面上制作铜势垒层，其中在制作铜势垒层之前，清洁的铜表面不再被氧化。
2．一种在半导体器件中制作铜互连结构的方法，其特征是下列步骤：
提供半导体衬底；
在半导体衬底上制作介电层；
对介电层进行图形化，以便在介电层中制作窗口；
在半导体衬底上制作铜层，此铜层位于窗口中；
对铜层进行抛光，以便在窗口中制作铜互连，此铜互连具有上表面；
从铜互连的上表面清除氧化铜以形成清洁的铜表面；以及
在清洁的铜表面上制作铜势垒层。
3．一种在半导体器件中制作铜互连结构的方法，其特征是下列步骤：
提供半导体衬底；
在半导体衬底上制作介电层；
对介电层进行图形化，以便在介电层中制作窗口；
在半导体衬底上制作铜层，此铜层位于窗口中；
对铜层进行抛光，以便在窗口中制作铜互连，此铜互连具有上表面；
将铜互连暴露于以氢和氮为特征的等离子体，以便从铜互连的上表面清除氧化铜并形成清洁的铜表面；以及
在清洁的铜表面上制作铜势垒层，其中在制作铜势垒层之前，清洁的铜表面不再被氧化。
4．一种在半导体器件中制作铜互连结构的方法，其特征是下列步骤：
提供半导体衬底；
在半导体衬底上制作介电层；
对介电层进行图形化，以便在介电层中制作窗口；
在半导体衬底上制作铜层，此铜层位于窗口中；
对铜层进行抛光，以便在窗口中制作铜互连，此铜互连具有上表面；
将铜互连暴露于以氢为特征的无硅等离子体，以便从铜互连的上表面清除氧化铜并形成清洁的铜表面；以及
在清洁的铜表面上制作铜势垒层，其中暴露铜互连的步骤和制作铜势垒层的步骤在同一个工作室中进行。
5．一种在半导体器件中制作铜互连结构的方法，其特征是下列步骤：
提供半导体衬底；
在半导体衬底上制作介电层；
对介电层进行图形化，以便在介电层中制作窗口；
在半导体衬底上制作铜层，此铜层位于窗口中；
对铜层进行抛光，以便在窗口中制作铜互连，此铜互连具有上表面；
将铜互连暴露于以氢和氮为特征的等离子体，以便从铜互连的上表面清除氧化铜并形成清洁的铜表面；以及
在清洁的铜表面上制作以硅和氮为特征的铜势垒层，其中暴露铜互连的步骤和制作铜势垒层的步骤在同一个工作室中进行。
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