CN1235452C - 一种集成电路载体的制作方法 - Google Patents

一种集成电路载体的制作方法 Download PDF

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CN1235452C
CN1235452C CNB018177603A CN01817760A CN1235452C CN 1235452 C CN1235452 C CN 1235452C CN B018177603 A CNB018177603 A CN B018177603A CN 01817760 A CN01817760 A CN 01817760A CN 1235452 C CN1235452 C CN 1235452C
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CN1471802A (zh
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卡·西尔弗布鲁克
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Abstract

一种制作集成电路载体的方法，该方法包括提供一个基板。划分至少一个容纳区，用以容纳基板上的集成电路。在至少一个容纳区周围设置多个岛屿界定部分。通过从基板去除材料在相邻的岛屿界定部分之间设置刚性降低装置。

Description

一种集成电路载体的制作方法
技术领域
本发明与集成电路封装有关。特别地，本发明与用于集成电路封装的集成电路载体有关。
技术背景
由于集成电路连接(引脚数目)的数目不断增加，采用球栅阵列封装将集成电路连接到印刷电路板的技术正在不断增加。这样使得集成电路倒装芯片凸点阵列由非常微小的问距重新分布到更大问距的球栅阵列，以附着到印刷电路板(PCB)。
该载体通常是指一个内插件(interposer)并且可以利用不同的材料例如陶瓷，或者塑性材料，例如双马来酰亚胺三嗪(BT)进行制造。
通过热传导而去除集成电路的热能，集成电路载体也可以起到热沉的作用。因此集成电路载体容易受到热应变的影响。
另外，包括集成电路、载体和PCB的电子封装组件具有多种采用不同机械性能的不同材料。在工作中由于温度分布不均、几何形状、材料结构和热膨胀不匹配而在封装内部产生复杂的热应变。
通常情况下，当前的集成电路是通过金或焊接凸点的球栅阵列电连接到该载体。同样，该载体进一步通过更大的焊球的球栅阵列与PCB电连接。通常在PCB和载体之间的焊球接口处的热机械应变是非常严重的。这会导致焊球连接的剪切(shearing)。该问题被由PCB和载体之间热应变差的增加而引起的载体边缘长度的增加而扩大。通常载体边缘长度的增加与集成电路连接和焊球数目的增加有关联。
目前球栅阵列设计受到集成电路引脚数目的可靠性的限制。
通常焊球的最大弹性剪切应变值大约为0.08％。申请人采用厚度为500微米固态硅载体，间距为1毫米、直径为500微米的焊球，厚度为700微米的PCB和边长16毫米的硅芯片进行实验计算，结果显示在封装最外面球的最大剪切应变为1.476％，该数值远大于焊球的塑流值(plastic yield value)。
该结果被认为是在封装的最外面边缘的焊球产生最大的平移剪切应变。
正如1999年版(附本附后)the Assembly and Packaging Sectionof the International Technology Road Map for Semiconductors的出版中第217页表59a所述，高性能集成电路引脚数目可达到1800个引脚的水平，该版本是提出本申请时的最新版本。在近期内，也就是说直到2005年，对于高性能集成电路，将要求引脚的数目超过3,000，如表所示，至今还没有解决方案。同样，如该出版物第219页表59b所述，在更长期的时间内，直到大约2014年，高性能集成电路封装引脚数目将达到9,000个的级。同样，如表中所述，没有公知的针对该类型封装的解决方案。
以上几个方面的问题是本发明关注的焦点。
发明内容
本发明提供一种制作集成电路载体的方法，该方法包括以下步骤：
提供一个基板；
在所述基板上为集成电路界定出至少一个容纳区，在上述至少一个容纳区周围设置多个岛限定部分；以及
通过从基板去除材料在相邻的岛限定部分之间设置刚性降低装置。
该方法包括在上述至少一个容纳区中形成电接触，以及每个岛限定部分中形成一个电端子，每个电端子通过电路层的走线轨迹电连接到一个电接触。
因此，该方法包括通过在基板上沉积金属层从而在基板表面形成电路层。然后，该方法可以包括对金属层进行蚀刻从而形成走线轨迹。
该方法可以包括通过在基板表面应用掩膜而界定出所述至少一个容纳区和岛限定部分。
该方法可以随后包括通过在将承载所述掩模的基板曝光之后蚀刻贯通基板去除基板材料，以产生刚性降低装置。
优选地，该方法包括通过重入式蚀刻(re-entrant etch)形成刚性降低装置以提高载体的热沉能力。
该方法可以包括在与上述至少一个容纳区相邻的每个岛限定部分与所述至少一个容纳区之间产生第二刚性降低装置。同样，该方法可以通过在基板上进行贯通蚀刻的方法产生第二刚性降低装置。
该方法可以包括从具有绝缘层的未掺杂的硅晶片形成基板。该绝缘层可以作为蚀刻用的硬掩模。
该方法可以包括通过在基板内形成凹槽来界定所述至少一个容纳区。该凹槽可以通过对基板蚀刻的方法而界定。
另外，该方法可以包括通过形成穿过所述基板的通道来界定至少一个容纳区，围绕所述通道的基板区域承载所述电接触。同样，该通道可以通过蚀刻基板而形成。
附图说明
下面结合附图和实例对本发明给予说明；
图1所示为概念性集成电路载体的部分平面示意图；
图2所示为本发明的集成电路载体的部分平面图；
图3所示为集成电路载体的一个实施例的局部透视截面图；
图4所示为集成电路载体第二实施例的局部透视截面图；
图5所示为集成电路载体第三实施例的局部透视截面图；
图6所示为集成电路载体第四实施例的局部透视截面图；
图7所示为使用中的集成电路载体的一个实施例的截面侧视图；
图8所示为使用中的集成电路载体的另一个实施例的截面侧视图；
图9所示为图8中圆圈A部分的放大示意图；
图10所示为集成电路载体以更大比例放大的截面侧视图；
图11所示为集成电路载体的另一个实施例的侧视图；
图12所示为集成电路载体的再一个实施例的截面侧视图；
图13所示为基于集成电路载体的多芯片模块；
图14所示为基于集成电路载体的多芯片模块的截面侧视图。
具体实施方式
参考附图，本发明的集成电路载体通常用参考数字10来表示。附图的图2对集成电路载体给予更加具体的说明。
集成电路载体10具有一个容纳区12，用以容纳一个集成电路或者芯片14(图7)。
多个岛限定部分或者岛16围绕着容纳区12。每个岛16其上具有一个电端子18，焊球20附着或者回流(reflow)到该电端子18。
每个岛16通过一个蛇形件22形式的刚性降低装置连接到与其相邻的一个岛或者多个岛16。图1对此给予了详细的概念性说明。如图1所示，每个蛇形件22起到类似弹簧的作用，这样每个岛16相对于其相邻的岛16都具有一定的移动自由度。因此，印刷电路板24(图7至图9)和载体10之间的膨胀差通过相关蛇形件22的伸或缩而得到补偿。由此，岛16上焊球20的剪切应变被显著降低，同时对焊球20产生的疲乏失效(fatigue failure)也相应下降。
下面结合图3到附图6对载体10的各种具体实施例给予具体说明。如图3所示，载体10具有通过具有单个曲线臂26的蛇形件22被连接到其相邻的岛16的每个岛26。
在如图4所示的本发明的具体实施例中，每个蛇形件22通过由垂直桥接部分30而相互连接的一对并行臂28，将一个岛16连接到其相邻的岛16。
在图5所示的具体实施例中，每个蛇形件22通过具有三个彼此并行延伸的臂34的装置，将一个岛16连接到其相邻的岛16，相邻臂34通过垂直桥接部分32连接在一起。
在图6所显示的具体实施例中，每个将一个岛16连接到其相邻的岛16的蛇形件22具有五个并行臂36，其中，相邻的并行臂36通过一个垂直桥接部分38而连接。
为便于说明，在附图的图3到图6中所示的具体实施例可以在以下内容中分别称为：一臂26蛇形件22、两臂28蛇形件22、三臂34蛇形件22以及五臂36蛇形件22。
如附图的图7到图9更清楚显示的，围绕容纳区12的岛16由之字形元件40形式的第二刚性降低装置而连接到接收区，该之字形元件40可进一步降低作用在焊球20上的应变。
同样，如图7到图9所示，集成电路14通过焊接凸点44电连接到容纳区12内的电接触42(图2)。
载体10由与集成电路14相同的材料形成。因此，载体10是由具有一层二氧化硅绝缘层的硅而形成的。该绝缘层也可以作为蚀刻蛇形件22的硬掩膜，这一点将在以下内容给予更加细致的讨论。
在集成电路载体10的制作过程当中，首先提供一个硅晶片46。该晶片46可以为单晶硅或者多晶硅。
需要指明的是，在附图的图10所示的载体10的版本中，接收区12与图7中所示的垫18位于载体10的同一侧。如图8所示，当容纳区12位于与载体10的相对表面上时，电路层可应用在晶片46的两侧。这一点在图9中以较小比例进行了显示。在该具体实施例内，每条轨道52都通过延伸通过晶片46的电镀通孔58而电连接到其关联垫18上。
现在参照图11和12，对载体10的另外两个具体实施例给予说明。参照前面的附图，除非特别指定，相同部件采用相同的数字编号标注。
在图示的实例当中，容纳区12不是被在载体10的表面上划界，而是一个通过载体10限定的通道60。集成电路14附着在金属盖形式的安装装置或者保持装置上，该装置接合到载体10的一个表面上。集成电路14的相反表面上具有将集成电路电连接到载体10上的接合垫。需要注意的是，在本实施例中，在围绕通道60的载体10部分设置以电接触。在如图11所述的具体实施例中，相互连接是引线接合64。也可采用球或者楔接合的形式。在图12所示的具体实施例中，相互连接是通过采取是卷带自动接合(TAB)薄层66或者其他诸如梁式引线等平面连接形式。
结合图13，在以下内容对集成电路载体的进展给予了说明，并且采用参考数字70表示。参照前面的附图，除非特别指定，相同部件采用相同的参考数字。
在本发明的本实施例中，载体70是一个多芯片模块的基板70，承载有多个集成电路或者芯片，例如图13所示的72，74和760芯片72，74和76或者安装在载体70的表面，或者如上面参照图10和图11的描述，该芯片被嵌入载体70，如图14所示。
如上面的指示，蛇形件22具有不同的结构，例如，单臂26结构，两臂28结构，三臂34结构或者五臂36结构。使用有限元分析也可以采用例如四臂、六臂或者更多臂结构的其他结构，因此用于具有不同形式的蛇形件22和不同球阵列的不同载体装置的结果矩阵被产生。下面所列举的矩阵包括用于具有一到二十四个球的行，固态硅，固态Al2O3，固态BT的载体，单臂26蛇形件22，两臂28蛇形件22，三臂34蛇形件22和五臂36蛇形件的球栅阵列的结果。
 每排焊球数   1   4   8   16   24   100
 固态硅内插件   1.08％   1.48％   1.61％   1.01％
 固态Al2O3内插件   0.667％   0.953％   1.077％   0.72％
 固态BT内插件   0.126％   0.149％   0.150％   0.097％
 单臂蛇形件   0.103％   0.0903％   0.085％
 二臂蛇形件   0.47％   0.15％   0.147％   0.136％   0.128％   0.088％
 三臂蛇形件   0.22％   0.082％   0.079％   0.058％   0.056％
  五臂蛇形件   0.025％   0.025％   0.013％
如上所示，焊料弹性应变限度大约为0.08％。一排焊球被限定为从容纳区12的边缘到载体10的边缘。
以上结果显示，由于PCB24和载体10之间的热-机械应变的累积效应，固态载体的焊球应变峰值随焊球20数目增加达到某一点时而增加。对于上百的球实施焊球应变实际下降了，这可能是由于固态硅载体发生变形而造成的。虽然由于载体和PCB之间的差别膨胀被最小化而被降低，但是在最外面的球中仍然出现最大应变。而且，除了BT载体，固态载体的最大应变值仍然远远超过焊料的弹性应变极限。
蛇形件22实施表明随着焊球数目的增加最大焊球应变降低。这是由于热应变不匹配分布到了大量焊球20，从而导致较轻程度的形变。球栅阵列越小，即每行的焊球越少，就会显示出越严重的形变，从而在焊球20的最内面或最外面都会造成集中负荷现象。
因此，本发明的一个具体优点在于，由于应变的峰值随焊球20数目的增加而减少，所以对于集成电路针脚连接的数目不存在热-机械的限制。在容纳区12的所有的侧上一行100个球相当于一个大于40,000个球的球栅阵列，远远超过到2014年9000个球的预期要求。对于具有三个或更多臂的蛇形件，具有8行或者更多行球的载体，有限元计算表明最大焊球应变低于焊料的弹性限度。由于容纳区为硅，并且因此与硅集成电路具有相同的热膨胀系数，则从集成电路14至载体10的凸点连接上的应变被最小化。这一点指示这里所述的带有蚀刻顺从区域的硅BGA能够对热循环的失败问题提供肯定的解决方案，其限制了使用球栅阵列能够在芯片和PCB之间制作的连接数量。同样，如上所述，通过提供蛇形件22，可以提供更大的表面积并且该表面积通过重入式蚀刻50进一步增加从而增强了载体10的热沉能力。这也有助于增加能够构成阵列的焊球20的数目。
本领域的技术人员应该明确：在不违背本发明所广泛说明的精神和范围的情况下，可以对本发明进行各种变化和/或改进。因此，应当将本发明的实施例作为说明而不是限制。

Claims (11)

1.一种制作集成电路载体的方法，该方法包括步骤如下：
提供一个基板；
在基板上为集成电路界定至少一个容纳区，以及多个岛限定部分被设置于上述至少一个容纳区周围；以及
通过从基板去除材料在相邻的岛限定部分之间产生刚性降低装置。
2.如权利要求1所述的方法，其特征在于，该方法包括在上述至少一个容纳区中形成电接触，以及在每个岛限定部分中形成一个电端子，每个电端子通过电路层的走线轨迹电连接到电接触之一。
3.如权利要求2所述的方法，其特征在于，该方法包括通过在基板上沉积金属层从而在基板表面形成电路层。
4.如权利要求1所述的方法，其特征在于，该方法包括通过对基板表面应用的掩膜而界定所述至少一个容纳区和所述岛限定部分。
5.如权利要求4所述的方法，其特征在于，该方法包括通过在将承载所述掩模的基板曝光之后蚀刻贯通该基板来去除基板材料，以产生刚性降低装置。
6.如权利要求1所述的方法，其特征在于，该方法还包括该步骤即通过蚀刻贯通基板在所述至少一个容纳区以及与所述至少一个容纳区相邻的岛限定部分之间产生第二刚性降低装置。
7.如权利要求1所述的方法，其特征在于，该方法包括从具有绝缘层的未掺杂的硅晶片形成基板。
8.如权利要求1所述的方法，其特征在于包括通过在基板中形成凹槽来界定所述至少一个容纳区。
9.如权利要求8所述的方法，其特征在于包括通过蚀刻该基板形成该凹槽。
10.如权利要求2所述的方法，其特征在于，该方法包括通过形成穿过所述基板的通道来界定所述至少一个容纳区，围绕所述通道的基板区承载所述电接触。
11.如权利要求10所述的方法，其特征在于，该方法包括通过蚀刻基板而形成所述通道。
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US7247941B2 (en) 2007-07-24
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