CN1244716C - 通过使用三(二甲基氨基)硅烷的原子层沉积形成含硅薄膜的方法 - Google Patents

通过使用三(二甲基氨基)硅烷的原子层沉积形成含硅薄膜的方法 Download PDF

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CN1244716C
CN1244716C CNB011399651A CN01139965A CN1244716C CN 1244716 C CN1244716 C CN 1244716C CN B011399651 A CNB011399651 A CN B011399651A CN 01139965 A CN01139965 A CN 01139965A CN 1244716 C CN1244716 C CN 1244716C
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reactant
substrate
silicon
forms
containing solid
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CN1392288A (zh
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金营宽
朴泳旭
李承换
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Samsung Electronics Co Ltd
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Abstract

本发明提供一种形成含硅固体薄膜层的原子层沉积方法。将基底置入腔体，此后，将含Si和氨基硅烷的第一反应物注入腔体。该第一反应物的第一部分化学吸附于基底上，第一反应物的第二部分物理吸附于基底上。一个优选方案中，通过吹洗和冲洗腔体，将第一反应物的物理吸附的第二部分从基体上清除。然后将第二反应物注入腔体，这里第二反应物的第一部分与第一反应物的化学吸附的第一部分化学反应，在基底上形成含硅固体。然后从腔体中清除第二反应物的未化学反应部分。一个优选方案中，在基底上形成的含硅固体为薄膜层，如氮化硅层。另一个优选方案中，第一反应物至少为选自Si[N(CH3)2]4，SiH[N(CH3)2]3，SiH2[N(CH3)2]2和SiH3[N(CH3)2]中的一种。第二反应物优选为活性NH3。腔体的压强优选维持在1.33-13300Pa(0.01-100乇)的范围内，且在优选实施方案中可在整个工艺中保持恒定，或可在四个步骤中的至少一个中改变。上述步骤中的一步或多步可重复进行，以在基底上获得较厚的固体。

Description

通过使用三(二甲基氨基)硅烷 的原子层沉积形成含硅薄膜的方法
技术领域
本发明是关于形成Si3N4和SiO2薄膜的方法，采用的是原子层沉积法，该方法使用三(二甲基氨基)硅烷(trisdimethylaminosilane){HSi[N(CH3)2]3}(以下称“TDMAS”)作为反应物。
背景技术
通常，在半导体元件上形成Si3N4和SiO2薄膜是采用沉积方法如化学气相沉积(CVD)、低压化学气相沉积(LPCVD)、等离子体增强化学气相沉积(PECVD)。
以CVD为基础的方法常常具有缺陷，限制了其在制造因具有Si3N4薄膜而受益的半导体元件上的应用。典型的CVD法中，Si3N4薄膜在相对较高的温度下沉积，由于可能对元件产生有害的热效应，所以一般没有低温工艺好。用CVD法沉积的Si3N4层也易受几何形状干扰导致整个元件表面的厚度不均。表面上具有紧密堆积的形貌周围形成的薄膜的厚度要小于较不紧密堆积的形貌周围形成的膜的厚度。该问题公知为构型充填效应。
LPCVD也有缺点。LPCVD法制备的薄膜的氢含量通常较高，表面的间距覆盖率不好。由于采用LPCVD法时膜的生长速率较低，因此形成合适厚度的膜所需的工艺时间相对较长。长的处理时间使得基底在相当高的温度下长时间暴露，造成与LPCVD工艺伴生的高的热存积。
已有推荐采用原子层沉积(ALD)作为形成Si3N4和SiO2薄膜的以CVD为基础的沉积法的替代方法。ALD是实施于表面动力学区域的表面控制工艺，可导致表面上的二维层叠沉积。Goto等描述了一种使用二氯甲硅烷(dichlorosilane)(DCS)和NH3等离子体形成Si3N4膜的ALD沉积法。(Appl.Surf.Sci.，112，75-81(1997)；Appl.Phys.Lett.68(23)，3257-9(1996))。但是用Goto描述的方法制备的薄膜的性能并不理想。Cl含量(0.5％)和O含量太高。这些再加上测出的Si∶N比率为41∶37，表明该方法不能形成Si3N4的近化学计量的膜。此外，每300秒为周期的0.09nm(0.91埃)的生长速率对于商业应用来说不够高。
Klaus等描述了一种用SiCl4和NH3反应形成Si3N4膜的ALD方法。见美国专利6,090,442，和Surf.Sci.，418，L14-L19(1998)。该方法制备的薄膜的特性优于Goto等的所得。比率Si∶N＝1∶1.39，并且Cl、H和O的低含量令人满意。但是，10分钟形成0.245nm(2.45埃)膜的周期太长，使其商业应用不切实际。
也有建议使用Si2Cl6(HCD)和N2H4用ALD法沉积薄Si3N4膜。(Appl.Surf.Sci.，112，198-203(1997))。尽管化学计量法上，该膜的Cl和H含量合适，其氧的含量太高，使得这样的膜不适合上述用途。
ALD也被提议为沉积SiO2薄膜的一种方法。例如，已被提议用于使用SiCl4和H2O的沉积工艺。Appl.Phys.Lett.70(9)，1092(1997)。然而，该推荐工艺的周期对于商业应用来说太长了。美国专利6,090,442公开了一种催化工艺，该工艺采用SiCl4和H2O沉积SiO2膜，使用C5H5N或NH3作为催化剂。因为沉积温度低，该工艺获得的SiO2膜的质量不好。一种使用Si(NCO)4和TEA的工艺已被披露(Appl.Surf. Sci.Vol.130-132，pp.202-207(1998))，但也因工艺温度低以致膜的质量低。使用Si(NCO)x和H2O的推荐工艺也是如此(J.Non-crystalline Solids，Vol.187，66-69(1995))。
因此，尽管有长期以来公认的广泛应用的潜力，仍然存在着形成满足下列条件的Si3N4和SiO2薄膜的新方法的需求，这些条件为：低热存积工艺；优异的间距覆盖率；无构型充填效应；比率Si∶N同Si3N4；优异的厚度控制及均匀度；颗粒夹杂量最少；杂质含量低；以及使得商业应用切实可行的膜生长速率。
为达到上述目标，本发明采用原子层沉积法(ALD)，使用TDMAS作为反应物制备Si3N4和SiO2薄膜。
发明内容
本发明具体表现为在置于腔体中的基底上形成含硅固体薄膜层的一种原子层沉积方法。将含Si的第一反应物和氨基硅烷(aminosilane)注入腔体，在这里第一反应物的第一部分化学吸附于基底上，且第一反应物的第二部分物理吸附于基底上。一个优选方案中，通过吹洗和冲洗腔体，将第一反应物的物理吸附的第二部分从基底上清除。然后将第二反应物注入腔体，该第二反应物的第一部分与第一反应物的化学吸附的第一部分化学反应，在基底上形成含硅固体。然后将第二反应物的未化学反应部分从腔体中清除。一个优选方案中，基底上形成的含硅固体为薄膜层，如氮化硅层。另一个优选方案中，第一反应物为至少选自Si[N(CH3)2]4、SiH[N(CH3)2]3、SiH2[N(CH3)2]2和SiH3[N(CH3)2]中的一种。第二反应物优选为活性NH3。腔体压力优选维持在0.01-100乇的范围内，并且在优选方案中的整个工艺过程中腔体压力可维持恒定，或者在四个步骤的至少一个中可改变。上述步骤中的一步或多步可重复进行，以在基体上获得较厚些的固体。
不同实施方案中，用本发明方法形成的含硅固体，在用作活性掩模氮化物时对于半导体元件的Si，在用作栅掩模氮化物时对于半导体元件的WSix和掺杂的多晶硅，在用作位线掩模氮化物时对于半导体元件的W和Ti/TiN具有干法刻蚀选择性。基底上形成的含硅固层也能用作化学机械抛光(CMP)隔离件，或用作对于半导体元件(隔板)的SiO2具有于法刻蚀选择性绝缘层。其它实施方案中，基底上形成的含硅固体为绝缘层，作为隔湿件，对半导体元件的SiO2具有HF湿法刻蚀选择性。
基底上形成的含硅固体可用作半导体元件的栅极绝缘件，在半导体元件的Ta2O5层和电容器存储节点之间形成的覆层，用作半导体元件的电容器的绝缘层，或用作半导体元件的浅沟槽隔离(STI)内衬。
在其它实施方案中，基底上形成的含硅固体为氧化硅，并且在这些实施方案的一个或多个中，第二反应物选自H2O，H2O2，O2等离子体和O3等离子体。
另外还有一个实施方案中，第一和第二含硅固体中至少有一个为金属硅酸盐，其中的金属选自Al、Hf、Zr、Ti和Ta。
现在参照附图来阐述本发明的这些和其它特征。
附图说明
参照附图，通过详细描述本发明的优选方案，本发明的上述目的和优点将更明显：
图1至5描述了根据本发明的优选实施方案，采用原子层沉积法形成Si3N4薄膜的工艺步骤。
图6为根据本发明的薄膜制备方法使用的薄膜制备装置的示意图。
图7为根据本发明的薄膜制备方法的流程图。
图8为表示根据本发明的一个优选实施方案采用的制备方法，每周期形成的Si3N4膜厚度的图表。
图9为根据本发明的一个优选实施方案的方法，随着TDMAS注入时间的变化，Si3N4膜厚度和膜均匀度改变的曲线图。
图10为根据本发明的一个优选实施方案的方法，随着NH3等离子体发生器能量的变化，Si3N4膜厚度和膜均匀度改变的曲线图。
具体实施方式
从解释方法的工艺步骤开始进行优选实施方案的下列描述，接着描述本发明的优选实施方案的具体实例。
参见图1-6，基底1如硅(100)置于腔体3(见图6)中，然后抽真空至压强为约266Pa(2乇)。加热基底1至约550℃。然后向腔体中注入15秒钟500sccm的Ar载体气体中的TDMAS流束2。停止注入流束2，保持腔体不受干扰15至165秒钟。
在此期间，TDMAS的第一部分在基底1的表面上化学吸附并形成覆层4。TDMAS分子的第二部分物理附着(物理吸附)并松散地附着于TDMAS化学吸附层上。然后用N2吹洗腔体35秒钟，并真空驱气5秒钟。在吹洗步骤中，TDMAS的未化学吸附部分被清除出腔体，在基底1上留下完整的TDMAS化学吸附层4(图2)。现在参见图3，向腔体3中注入30秒钟的含活性NH3的2000sccm的Ar流束6，同时维持降低的腔体压强66.5Pa(0.5乇)，基底温度550℃。活性NH3的一部分与基底上的化学吸附TDMAS反应，形成Si3N4层8(图4)。一个实施方案中，活性NH3为等离子体发生器在约400瓦特时产生的等离子体，但是该功率可改变，并且本发明并不限于一个特定的等离子体腔体功率水平。在含NH3的流束注入容器30秒钟之后，用N2吹洗5秒钟腔体3，并真空驱气5秒钟。向腔体3中注入TDMAS，吹洗，向容器中注入NH3，再冲洗的步骤可重复进行，以获得所需厚度的Si3N4层8。现在Si3N4层8已完成了。
图6为根据本发明的薄膜制备方法使用的薄膜制备装置的示意图。图7为根据本发明的薄膜制备方法的流程图。现在参照图6-10来描述上述的实施方案。将基底1，如(100)硅基底，置入腔体3中后，将腔体的压强调至约266Pa(2乇)，使用加热器5(步骤100)将腔体加热至约550℃的温度。将含TDMAS的第一反应物流束注入腔体3中达30秒钟，此时基底维持在550℃，压强约为266Pa(2乇)(步骤105)。通过从气源19注入500sccm的Ar载体气体进入第一起泡器12，该起泡器在约25℃下容纳液态TDMAS，TDMAS汽化形成第一反应物流束6。如上所述，将TDMAS和Ar相结合的气体流束通过第一气体管线13和淋喷头15注入腔体3中约30秒钟。然后，用纯Ar吹洗腔体3达5秒钟，用泵7进行真空驱气5秒钟。本发明并不限于该特定的吹洗方案，而是包括不同的能从TDMAS的化学吸附表面层上清除物理吸附TDMAS的吹洗工序。
然后将Ar载体气体中的活性NH3的第二反应物气体流束通过气体管线16和淋喷头15注入腔体3中约30秒，速率约为2000sccm。在该步骤中，基底1维持在550℃，腔体压强维持在约66.5Pa(0.5乇)(图7中步骤115)。一个实施方案中，将Ar从气体源19经第二起泡器17中约25℃的液态NH314通过，使第二反应物气体流束中的NH3汽化。于是NH3和Ar流束流经远程等离子体发生器(未标示)，通过气体管线16和淋喷头15以约2000sccm的速率注入腔体3中约30秒。
如图3和4所示，第二反应物流束中的一部分NH3与化学吸附在基底1上的TDMAS反应形成Si3N4层。当Si3N4层在基底上形成时，第二反应物流束中的第二部分NH3物理吸附在Si3N4层上。用Ar流束吹洗腔体3达5秒钟，接着用泵7真空驱气(步骤120)。但是，没有最初的惰性气体吹洗，物理吸附的第二反应物也能通过对腔体进行真空泵驱气而清除。
在从腔体3吹洗去未反应的NH3之后，测量Si3N4层的厚度(步骤125)。如果需要增加层厚，重复步骤105至125，直到获得理想的层厚。获得了理想的层厚，将腔体的温度和压强调回正常值，制备工艺完成(步骤130)。
如图8所示，在形成Si3N4层的上述方法中，沉积速率为0.135nm(1.35)/周期，并且层厚对于周期数表现出线性关系。在波长632.8nm时测量沉积材料的折射率为2.0，证明该沉积层为化学计量Si3N4。在5×105米/厘米2(5E10达因/厘米2)下测量膜的拉应力。氢含量和碳含量都很低，约为1at％或更低，没有检测到氧。在具有深宽比(aspect ratio)为8∶1的接点型结构上可达到95％或更高的间距覆盖率。与200∶1的HF水溶液的湿法刻蚀速率很低，约为1nm(10)/min，提供了理想的湿法刻蚀选择性，是Si3N4薄膜的一个有益特征。
参见图9，当考虑到相对于TDMAS照射量(此为典型的ALD沉积特性)的生长速率的变化时，已证实在上述条件下暴露60秒钟(吹15秒钟并停留45秒钟)，未检测到生长速率的变化。这看来意味着60秒钟的照射导致了基底表面的饱和。此外，当吹入TDMAS达30秒钟时，可获得与吹入时间15秒钟且停留时间45秒钟或更多时相同的生长速率。
现在参见图10，测定了等离子体发生器中的RF能量水平的影响。由上述的方法可知，在基底暴露于TDMAS，且容器被吹洗后，活性NH3被注入容器。如图10所示，活性NH3的使用是权利要求的方法的一个重要的方面。当能量发生器中的RF能量为0，且因此没有活性NH3注入腔体中时，根本没有Si3N4膜沉积，表明未活化的NH3和基底上的TDMAS之间没有反应。在0和0.4kW之间，膜的沉积速率如所示的以线性关系递增。从0.4kW往上，生长速率几乎不增长，表现出典型的ALD的沉积速率关系。
使用TDMAS形成SiO2层的ALD工艺
为了改善这些问题，可使用TDMAS和H2O、H2O2、活性O2(如O3、O2远程等离子体等)实施ALD工艺。
使用TDMAS的硅酸盐ALD工艺
当应用ALD工艺形成硅酸盐时，该硅酸盐为绝缘物质，且与SiO2相比具有较大的介电常数，应在金属氧化物的处理窗口(processwindow)中施行SiO2处理以形成硅酸盐。适当的SiO2处理可由使用TDMAS而实现。
上述优选方案为说明性的而非限定性的。本领域的技术人员会认识到，在没有脱离下列权利要求的范围的情况下，可对上述发明予以修改与变换。

Claims (27)

1.一种形成含硅固体薄膜层的原子层沉积方法，包括下列步骤：
a)将基底放置入腔体；
b)将第一反应物注入腔体，所述的第一反应物包括至少选自Si[N(CH3)2]4、SiH[N(CH3)2]3、SiH2[N(CH3)2]2和SiH3[N(CH3)2]中的一种；
c)第一反应物化学吸附以及物理吸附于基底上；
d)从基底上清除第一反应物的物理吸附部分；
e)将第二反应物注入腔体；
f)第二反应物与第一反应物的化学吸附部分化学反应，在基底上形成含硅固体；
g)从腔体中清除第二反应物的未化学反应部分。
2.权利要求1所述的方法，其中在基底上形成的含硅固体为薄膜层。
3.权利要求1所述的方法，其中重复所述步骤b)-g)中的一步或多步。
4.权利要求2所述的方法，其中所述的薄膜为氮化硅膜。
5.权利要求4所述的方法，其中所述的第二反应物为活性NH3。
6.权利要求5所述的方法，其中所述的活性NH3由远程等离子体发生器产生。
7.权利要求1所述的方法，其中所述的第二反应物为活性NH3，并且所述的活性NH3由使用贵金属的催化方法产生。
8.权利要求1所述的方法，其中所述膜的成分比N/Si为1-1.6。
9.权利要求1所述的方法，其中腔体的压强在1.33-13300Pa的范围内。
10.权利要求9所述的方法，其中在每个步骤实施期间，腔体的压强是相同的。
11.权利要求9所述的方法，其中在所述步骤b)-g)中的至少一个实施期间，所述腔体的压强不同于其余的步骤。
12.如权利要求1所述的方法，其中在基底上形成的含硅固体为活性掩模氮化物，其对于半导体元件的Si具有干法刻蚀选择性。
13.如权利要求1所述的方法，其中在基底上形成的含硅固体为栅掩模氮化物，其对于半导体元件的WSi2和掺杂的多晶Si具有干法刻蚀选择性。
14.如权利要求1所述的方法，其中在基底上形成的含硅固体为位线掩模氮化物，其对于半导体元件的W和Ti/TiN具有干法刻蚀选择性。
15.如权利要求1所述的方法，其中在基底上形成的含硅固体为化学机械抛光隔离件。
16.如权利要求1所述的方法，其中在基底上形成的含硅固体为对于半导体元件的SiO2具有干法刻蚀选择性的绝缘层或隔板。
17.如权利要求1所述的方法，其中在基底上形成的含硅固体为对于半导体元件的SiO2具有HF湿法刻蚀选择性的绝缘层或隔湿件。
18.如权利要求1所述的方法，其中在基底上形成的含硅固体包括一个半导体元件的栅极绝缘件。
19.如权利要求1所述的方法，其中在基底上形成的含硅固体是在半导体元件的Ta2O5层和电容器存储节点之间形成的覆层。
20.如权利要求1所述的方法，其中在基底上形成的含硅固体是半导体元件的电容器的绝缘层。
21.如权利要求1所述的方法，其中在基底上形成的含硅固体是半导体元件的浅构槽隔离内衬。
22.如权利要求1所述的方法，其中在基底上形成的含硅固体是氧化硅。
23.权利要求22所述的方法，其中的第二反应物选自H2O、H2O2、O2等离子体和O3等离子体。
24.权利要求22所述的方法，其中所形成薄膜的折射率在1.43-1.5范围内。
25.制备含硅固体薄膜的方法，包括下列步骤：
a)将基底置入腔体；
b)将含Si和H(CH3)2的第一气体反应物注入腔体，所述的第一气体反应物包括至少选自Si[N(CH3)2]4、SiH[N(CH3)2]3、SiH2[N(CH3)2]2和SiH3[N(CH3)2]中的一种；
c)第一反应物进行反应，在基底上形成第一含硅固体，第一反应物的未反应部分物理吸附于基底上；
d)从基底上清除第一反应物的物理吸附部分；
e)将第二反应物注入腔体；
f)第二反应物进行化学反应，在基底上形成第二含硅固体，第二反应物的未反应部分物理吸附于基底上；以及
g)从腔体中清除第二反应物的物理吸附部分。
26.权利要求25所述的方法，其中第一和第二含硅固体中至少有一个为金属硅酸盐。
27.权利要求26所述的方法，其中所述金属硅酸盐为选自Al、Hf、Zr、Ti和Ta的金属的硅酸盐。
CNB011399651A 2001-06-20 2001-11-21 通过使用三(二甲基氨基)硅烷的原子层沉积形成含硅薄膜的方法 Expired - Lifetime CN1244716C (zh)

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