CN1264160A - 用浅沟隔离工艺在绝缘体上硅晶片上集成衬底接触的方法 - Google Patents
用浅沟隔离工艺在绝缘体上硅晶片上集成衬底接触的方法 Download PDFInfo
- Publication number
- CN1264160A CN1264160A CN99126769A CN99126769A CN1264160A CN 1264160 A CN1264160 A CN 1264160A CN 99126769 A CN99126769 A CN 99126769A CN 99126769 A CN99126769 A CN 99126769A CN 1264160 A CN1264160 A CN 1264160A
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- Prior art keywords
- substrate
- silicon
- contact trench
- contact
- semiconductor device
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- Granted
Links
- 239000000758 substrate Substances 0.000 title claims abstract description 111
- 238000000034 method Methods 0.000 title claims abstract description 45
- 239000012212 insulator Substances 0.000 title claims abstract description 43
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title claims abstract description 33
- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 28
- 239000010703 silicon Substances 0.000 title claims abstract description 28
- 238000009413 insulation Methods 0.000 title 1
- 239000000463 material Substances 0.000 claims abstract description 15
- 238000002955 isolation Methods 0.000 claims abstract description 14
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 13
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 27
- 229920005591 polysilicon Polymers 0.000 claims description 27
- 239000004065 semiconductor Substances 0.000 claims description 24
- 239000011810 insulating material Substances 0.000 claims description 14
- 239000002019 doping agent Substances 0.000 claims description 12
- 238000005260 corrosion Methods 0.000 claims description 7
- 230000007797 corrosion Effects 0.000 claims description 7
- 238000001020 plasma etching Methods 0.000 claims description 7
- 239000004020 conductor Substances 0.000 claims description 6
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 claims description 5
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 4
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 4
- 229910052785 arsenic Inorganic materials 0.000 claims description 4
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 claims description 4
- 229910052796 boron Inorganic materials 0.000 claims description 4
- 229910052738 indium Inorganic materials 0.000 claims description 4
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 claims description 4
- 229910052698 phosphorus Inorganic materials 0.000 claims description 4
- 239000011574 phosphorus Substances 0.000 claims description 4
- 238000009792 diffusion process Methods 0.000 claims description 3
- 229910052751 metal Inorganic materials 0.000 claims description 3
- 239000002184 metal Substances 0.000 claims description 3
- 230000005611 electricity Effects 0.000 claims 2
- 229910052787 antimony Inorganic materials 0.000 claims 1
- WATWJIUSRGPENY-UHFFFAOYSA-N antimony atom Chemical compound [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 claims 1
- 150000004767 nitrides Chemical class 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 3
- 230000003068 static effect Effects 0.000 description 3
- 238000012937 correction Methods 0.000 description 2
- 239000000945 filler Substances 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 230000003628 erosive effect Effects 0.000 description 1
- 230000014509 gene expression Effects 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 239000000615 nonconductor Substances 0.000 description 1
- 238000012856 packing Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 230000003014 reinforcing effect Effects 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/585—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries comprising conductive layers or plates or strips or rods or rings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/74—Making of localized buried regions, e.g. buried collector layers, internal connections substrate contacts
- H01L21/743—Making of internal connections, substrate contacts
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78603—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the insulating substrate or support
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
- H01L21/76286—Lateral isolation by refilling of trenches with polycristalline material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Abstract
Description
Claims (32)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/239,327 | 1999-01-28 | ||
US09/239,327 US6521947B1 (en) | 1999-01-28 | 1999-01-28 | Method of integrating substrate contact on SOI wafers with STI process |
Publications (2)
Publication Number | Publication Date |
---|---|
CN1264160A true CN1264160A (zh) | 2000-08-23 |
CN1156891C CN1156891C (zh) | 2004-07-07 |
Family
ID=22901680
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CNB991267699A Expired - Lifetime CN1156891C (zh) | 1999-01-28 | 1999-12-16 | 用浅沟隔离工艺在绝缘体上硅晶片上集成衬底接触的方法 |
Country Status (7)
Country | Link |
---|---|
US (1) | US6521947B1 (zh) |
JP (1) | JP2000223684A (zh) |
KR (1) | KR100358629B1 (zh) |
CN (1) | CN1156891C (zh) |
GB (1) | GB2346260B (zh) |
SG (1) | SG85156A1 (zh) |
TW (1) | TW463290B (zh) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102593125A (zh) * | 2012-03-09 | 2012-07-18 | 上海宏力半导体制造有限公司 | 沟槽式mos静电释放结构以及集成电路 |
Families Citing this family (38)
Publication number | Priority date | Publication date | Assignee | Title |
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US6355511B1 (en) * | 2000-06-16 | 2002-03-12 | Advanced Micro Devices, Inc. | Method of providing a frontside contact to substrate of SOI device |
JP2002110990A (ja) * | 2000-09-27 | 2002-04-12 | Toshiba Corp | 半導体装置およびその製造方法 |
US6603166B2 (en) * | 2001-03-14 | 2003-08-05 | Honeywell International Inc. | Frontside contact on silicon-on-insulator substrate |
KR100456526B1 (ko) * | 2001-05-22 | 2004-11-09 | 삼성전자주식회사 | 식각저지막을 갖는 에스오아이 기판, 그 제조방법, 그위에 제작된 에스오아이 집적회로 및 그것을 사용하여에스오아이 집적회로를 제조하는 방법 |
US6800530B2 (en) * | 2003-01-14 | 2004-10-05 | International Business Machines Corporation | Triple layer hard mask for gate patterning to fabricate scaled CMOS transistors |
DE10303643B3 (de) * | 2003-01-30 | 2004-09-09 | X-Fab Semiconductor Foundries Ag | Verfahren zur Herstellung von Substratkontakten bei SOI-Schaltungsstrukturen |
US6753239B1 (en) | 2003-04-04 | 2004-06-22 | Xilinx, Inc. | Bond and back side etchback transistor fabrication process |
US6864156B1 (en) | 2003-04-04 | 2005-03-08 | Xilinx, Inc. | Semiconductor wafer with well contacts on back side |
DE10324433B4 (de) * | 2003-05-28 | 2007-02-08 | Advanced Micro Devices, Inc., Sunnyvale | Verfahren zur Herstellung eines Substratkontakts für ein SOI-Halbleiterbauteil |
JP4282388B2 (ja) * | 2003-06-30 | 2009-06-17 | 株式会社東芝 | 半導体記憶装置 |
US7851860B2 (en) * | 2004-03-26 | 2010-12-14 | Honeywell International Inc. | Techniques to reduce substrate cross talk on mixed signal and RF circuit design |
US7053453B2 (en) * | 2004-04-27 | 2006-05-30 | Taiwan Semiconductor Manufacturing Company, Ltd. | Substrate contact and method of forming the same |
US7230270B2 (en) * | 2004-11-24 | 2007-06-12 | Taiwan Semiconductor Manfacturing Company, Ltd. | Self-aligned double gate device and method for forming same |
DE102005010944B4 (de) * | 2005-03-10 | 2009-09-10 | X-Fab Semiconductor Foundries Ag | Verfahren zur Herstellung eines Trägerscheibenkontaktes in integrierten Schaltungen mit Hochspannungsbauelementen auf der Basis der SOI-Technologie und integrierte Schaltungen mit entsprechenden Grabenstrukturen |
US20060261436A1 (en) * | 2005-05-19 | 2006-11-23 | Freescale Semiconductor, Inc. | Electronic device including a trench field isolation region and a process for forming the same |
DE102005046624B3 (de) * | 2005-09-29 | 2007-03-22 | Atmel Germany Gmbh | Verfahren zur Herstellung einer Halbleiteranordnung |
US7408206B2 (en) * | 2005-11-21 | 2008-08-05 | International Business Machines Corporation | Method and structure for charge dissipation in integrated circuits |
KR100724199B1 (ko) * | 2005-12-28 | 2007-05-31 | 동부일렉트로닉스 주식회사 | 에스오아이 소자의 섀로우 트렌치 분리막 형성 방법 |
US7491622B2 (en) * | 2006-04-24 | 2009-02-17 | Freescale Semiconductor, Inc. | Process of forming an electronic device including a layer formed using an inductively coupled plasma |
US20070249127A1 (en) * | 2006-04-24 | 2007-10-25 | Freescale Semiconductor, Inc. | Electronic device including a semiconductor layer and a sidewall spacer and a process of forming the same |
US7670895B2 (en) | 2006-04-24 | 2010-03-02 | Freescale Semiconductor, Inc | Process of forming an electronic device including a semiconductor layer and another layer adjacent to an opening within the semiconductor layer |
US7528078B2 (en) | 2006-05-12 | 2009-05-05 | Freescale Semiconductor, Inc. | Process of forming electronic device including a densified nitride layer adjacent to an opening within a semiconductor layer |
US7550795B2 (en) * | 2006-06-30 | 2009-06-23 | Taiwan Semiconductor Manufacturing | SOI devices and methods for fabricating the same |
US7414289B2 (en) | 2006-07-17 | 2008-08-19 | Advanced Micro Devices, Inc. | SOI Device with charging protection and methods of making same |
US7638376B2 (en) * | 2007-01-12 | 2009-12-29 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method for forming SOI device |
DE102007029756A1 (de) * | 2007-06-27 | 2009-01-02 | X-Fab Semiconductor Foundries Ag | Halbleiterstruktur zur Herstellung eines Trägerwaferkontaktes in grabenisolierten SOI-Scheiben |
US7718514B2 (en) * | 2007-06-28 | 2010-05-18 | International Business Machines Corporation | Method of forming a guard ring or contact to an SOI substrate |
US7675121B2 (en) * | 2007-10-08 | 2010-03-09 | International Business Machines Corporation | SOI substrate contact with extended silicide area |
US7723178B2 (en) * | 2008-07-18 | 2010-05-25 | International Business Machines Corporation | Shallow and deep trench isolation structures in semiconductor integrated circuits |
US8026131B2 (en) * | 2008-12-23 | 2011-09-27 | International Business Machines Corporation | SOI radio frequency switch for reducing high frequency harmonics |
US7772083B2 (en) * | 2008-12-29 | 2010-08-10 | International Business Machines Corporation | Trench forming method and structure |
US8624349B1 (en) * | 2010-10-11 | 2014-01-07 | Maxim Integrated Products, Inc. | Simultaneous isolation trench and handle wafer contact formation |
CN104517889B (zh) * | 2013-09-30 | 2018-07-10 | 中芯国际集成电路制造(上海)有限公司 | 隔离结构的形成方法 |
US9087906B2 (en) | 2013-10-04 | 2015-07-21 | Globalfoundries Singapore Pte. Ltd. | Grounding of silicon-on-insulator structure |
US9431531B2 (en) | 2013-11-26 | 2016-08-30 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device having drain side contact through buried oxide |
US9847246B1 (en) | 2016-09-30 | 2017-12-19 | International Business Machines Corporation | Multiple finFET formation with epitaxy separation |
JP6936027B2 (ja) * | 2017-03-09 | 2021-09-15 | ルネサスエレクトロニクス株式会社 | 半導体装置およびその製造方法 |
US10943814B1 (en) | 2019-08-21 | 2021-03-09 | Globalfoundries U.S. Inc. | Etch stop member in buried insulator of SOI substrate to reduce contact edge punch through |
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JP2888878B2 (ja) * | 1989-10-02 | 1999-05-10 | 株式会社東芝 | 半導体装置 |
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JP3321899B2 (ja) | 1992-12-04 | 2002-09-09 | 株式会社デンソー | 半導体装置 |
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JPH07283414A (ja) * | 1994-04-05 | 1995-10-27 | Toshiba Corp | Mos型半導体装置 |
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JP3401918B2 (ja) | 1994-07-04 | 2003-04-28 | 株式会社デンソー | 半導体装置 |
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JP3462301B2 (ja) * | 1995-06-16 | 2003-11-05 | 三菱電機株式会社 | 半導体装置及びその製造方法 |
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US5643823A (en) | 1995-09-21 | 1997-07-01 | Siemens Aktiengesellschaft | Application of thin crystalline Si3 N4 liners in shallow trench isolation (STI) structures |
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JP3717227B2 (ja) | 1996-03-29 | 2005-11-16 | 株式会社ルネサステクノロジ | 入力/出力保護回路 |
JPH09283751A (ja) | 1996-04-11 | 1997-10-31 | Toshiba Corp | 半導体装置およびその製造方法 |
KR100253699B1 (ko) * | 1996-06-29 | 2000-05-01 | 김영환 | Soi소자 및 그 제조방법 |
US5702957A (en) | 1996-09-20 | 1997-12-30 | Lsi Logic Corporation | Method of making buried metallization structure |
US5889293A (en) | 1997-04-04 | 1999-03-30 | International Business Machines Corporation | Electrical contact to buried SOI structures |
US6300666B1 (en) * | 1998-09-30 | 2001-10-09 | Honeywell Inc. | Method for forming a frontside contact to the silicon substrate of a SOI wafer in the presence of planarized contact dielectrics |
-
1999
- 1999-01-28 US US09/239,327 patent/US6521947B1/en not_active Expired - Lifetime
- 1999-12-10 SG SG9906334A patent/SG85156A1/en unknown
- 1999-12-16 CN CNB991267699A patent/CN1156891C/zh not_active Expired - Lifetime
- 1999-12-23 TW TW088122753A patent/TW463290B/zh not_active IP Right Cessation
-
2000
- 2000-01-21 KR KR1020000002795A patent/KR100358629B1/ko not_active IP Right Cessation
- 2000-01-24 GB GB0001370A patent/GB2346260B/en not_active Expired - Fee Related
- 2000-01-26 JP JP2000017676A patent/JP2000223684A/ja active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102593125A (zh) * | 2012-03-09 | 2012-07-18 | 上海宏力半导体制造有限公司 | 沟槽式mos静电释放结构以及集成电路 |
Also Published As
Publication number | Publication date |
---|---|
GB2346260A (en) | 2000-08-02 |
KR100358629B1 (ko) | 2002-10-25 |
SG85156A1 (en) | 2001-12-19 |
GB2346260B (en) | 2004-01-28 |
CN1156891C (zh) | 2004-07-07 |
US6521947B1 (en) | 2003-02-18 |
TW463290B (en) | 2001-11-11 |
JP2000223684A (ja) | 2000-08-11 |
KR20000053556A (ko) | 2000-08-25 |
GB0001370D0 (en) | 2000-03-08 |
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