CN1267397A - 具有预定的α碳化硅区的半导体结构及此半导体结构的应用 - Google Patents
具有预定的α碳化硅区的半导体结构及此半导体结构的应用 Download PDFInfo
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Abstract
本发明涉及一种半导体结构(HS),它包括至少一个α碳化硅区(3、10、11)和一个例如为氧化层的电绝缘区(13a)以及一个在它们之间的界面(20)。通过为至少一个邻近界面的区选择一种能带宽度比6H碳化硅多型的能带宽度小的α碳化硅多型,提高了在此区内载流子的迁移率。
Description
本发明涉及一种半导体结构，它包括一个在预定的α碳化硅多型区与电绝缘区之间的界面，其中在碳化硅区的电导率在界面上可通过感应电荷加以改变。例如由“IEEE电子器件文摘”(“IEEE Electron Device Letters”Vol.18，No.3，1997年3月，93至95页)公知了此类半导体结构。此外，本发明还涉及上述半导体结构的应用。
单晶形式的碳化硅是一种具有优异物理特性的半导体材料，尤其由于其高的击穿场强及良好的导热性，这种半导体材料特别适用于大功率电子器件和在千伏范围内使用。因为市场上提供的6H和4H碳化硅多型单晶晶片越来越多，因而以碳化硅为基的大功率半导体器件(例如碳化硅肖特基二极管)也日益增多。然而迄今已公知的单极性碳化硅功率MOSFET中还存在着重要的性能问题，如导通电阻问题。
下面经常提到碳化硅多型的能带宽度。这里应指出，比较能带宽度值应在相同的制备、测试以及环境条件前提下来确定。在下文中引用的与之相关的值均适用于室温。在《碳化硅性能》(“Properties of Silicon Carbide”，G.L.Harris编辑，INSPEC出版社，英国伦敦，1995，74-80页)中提供了不同的碳化硅多型在温度为4K时的能带宽度。
在“IEEE电子器件文摘”(“IEEE Electron Device Letters”，Vol.18，No.3，1997年3月，93至95页)中例如介绍了一种单极性的MOSFET，它以6H碳化硅晶片为基础通过双重离子植入制成(所谓的D-MOSFET)。在此类D-MOSFET中，在碳化硅半导体区内电流是靠横向电流控制的，此半导体区即所谓的通道区，是在碳化硅区内碳化硅半导体区与电绝缘区(例如SiO2)之间的界面旁边。此后电流垂直通过此元件流入第二碳化硅半导体区，即所谓的漂移区。
采用所介绍的D-MOSFET与现有技术相比已经能达到改善导通电阻的目的。进一步专门地改善导通电阻(导通电阻主要取决于通道区和漂移区的电导率)的方法见“IEEE电子器件文摘”(“IEEE Electron Device Letters”，Vol.18，No.3，1997年3月，93至95页)，文中提出了可将6H碳化硅多型转换为4H碳化硅多型的前景。这种设想是建立在只考虑漂移区内的(体积)电导率这一认识基础上的。当电流沿晶体学的C轴垂直流动时，决定体积电导率的自由载流子迁移率约为800cm2V-1S-1的4H碳化硅多型明显地优于迁移率只有约100cm2V-1S-1的6H碳化硅。但是这里没有考虑到多型选择对第二个对导通电阻有决定意义的参数的影响，亦即对在通道区内的电导率的影响，该电导率除几何参数外主要取决于碳化硅半导体区与电绝缘区之间界面的特性。
本发明的目的是设计具有本文前言所述特征的半导体结构，使之与现有技术相比有更好的性能，尤其改善导通电阻。
本发明的目的是通过权利要求1的特征部分达到的。对于碳化硅区采用与4H和6H碳化硅多型不同的α碳化硅多型，它的能带宽度最多等于6H碳化硅多型的能带宽度。
本发明以下列认识为基础，即，在半导体区与电绝缘区之间界面上的有效电空穴(陷阱)的分布决定了在界面旁半导体的电导率，因而基本上决定了整个半导体结构的导通电阻。对碳化硅的研究证明，可与多型无关地构成高空穴密度的能带，它与价带有固定的能量间隙。此能带有一个在能量上比较清晰的极限下边缘，它位于价带边缘上方约2.9eV处。因为在碳化硅中价带的能位与多型无关，所以按本发明选择的多型保证空穴带在能量上位于导带内部，因而对电导率的影响明显地小于通常采用的具有较大能带宽度的多型材料时的情况。
按本发明选择α碳化硅多型时，有利地使半导体结构具有在前序部分所述的特征，从而有比现有技术更优的性能。尤其是导通电阻可有利地例如降低20倍。
从属权利要求给出了本发明的半导体结构的有利设计。在下面所论及的实施形式可看作是本发明的特别有利设计。
在半导体结构中，α碳化硅半导体区有一个至少比6H碳化硅多型小5meV的能带宽度。特别有利的是菱形α碳化硅多型(R型)，尤其是15R型或21R型。15R型碳化硅在室温下的能带宽度为2.79eV，因此它低于6H碳化硅的本发明的对照值(2.91eV)。由于4H或6H碳化硅多型的能带宽度为3.15eV(4H碳化硅)和2.91eV(6H碳化硅)，所以不是合适的多型材料，被本发明排除在外，尽管它们迄今在碳化硅大功率电子器件领域内由于市场有供应而实际上是唯一被使用的。因此在本发明的半导体结构界面区(通道区)内，载流子垂直于晶体学C轴的有利的迁移率在15R碳化硅多型中为≥40cm2V-1S-1，反之，在4H碳化硅中相应的值(≤1cm2V-1S-1)和6H碳化硅相应的值(＞20cm2V-1S-1)明显地较低。迄今一直认为，在邻接着漂移区内平行于晶体学的C轴通过基片体积的载流子迁移率对于导通电阻是决定性的，与在15R碳化硅中为330cm2V-1S-1相比，在4H碳化硅中更有利为800cm2V-1S-1。但是尽管如此，由于已说明的界面对通道区内载流子迁移率的影响，4H碳化硅的导通电阻比15R碳化硅高20倍。
另一种有利的实施形式充分利用了这一特征，为了在界面处获得有利的电导率，只须在直接与电绝缘区相邻的一个狭窄的半导体区内采用所需的α碳化硅多型构成。因此，与狭窄区连接的半导体区可用相同的或至少部分采用另一种碳化硅多型构成，或采用不同于碳化硅的另一种半导体材料或采用至少一种不同于碳化硅的另一种半导体材料的复合结构组成。
在另一种有利的实施形式中，本发明的半导体结构可设计为MOSFET结构，尤其设计为D-MOSFET结构或U-MOSFET结构，或设计为IGBT结构。这类结构经常应用于大功率电子器件中。
此外特别有利的是，本发明的半导体结构可应用于构成半导体元件或复合半导体电路。
下面借助附图说明本发明的实施例，唯一的附图示意示出了一种D-MOSFET。
D-MOSFET元件，如图所示并用HS表示的半导体结构，是重要的单极性大功率元件。在这种元件中，一方面电流是靠横向电流IL控制的，另一方面在由碳化硅半导体区3与碳化硅基片2组成的漂移区内电流是由通过该元件的垂直电流IV导引的。
在这里，垂直的电流指的是沿垂直于碳化硅半导体区3的界面20的方向的电流。与此相对应，横向指的是平行于在界面20内的方向的方向。
决定D-MOSFET元件导通电阻大小的一个参数是在横向电流IL区域内，即在所谓通道内的电导率。这些通道在接通状态由于感应电荷构成一些与界面20相邻的、有较大基区11的区域。决定性的界面20在此图中用粗线标明。半导体结构准确地位于D-MOSFET元件的这些区域内。基区11的至少与界面邻近的区域由比6H碳化硅的能带宽度小的α碳化硅多型构成，此区域与由第一氧化层13a构成的电绝缘区邻接，例如采用15R碳化硅多型是适合的。由此可以保证获得所期望的有利的高通道电导率，其结果是使结构具有较低的导通电阻。在基区11上面所设的电绝缘区，如附图实施例所示，可仅由单层构成。不过按照其他有利的实施形式，这一区也可以构造成优选由不同材料制成的多层。在图中表示的所谓栅极氧化物的第一氧化层13a有利地用SiO2材料，尤其热SiO2材料构成。但这一层在其他实施形式中也可以用非氧化的电绝缘材料，尤其用Si3N4构成。
下面详细说明图1所示D-MOSFET元件的工作原理。图中源区用10表示，其余为基区11、基接触区12、第一氧化层13a、第二氧化层13b、栅电极14、源电极15和漏极电极16。第二氧化层13b(绝缘氧化物)用于在栅电极14与源电极15之间的绝缘，并由采用LPCVD法沉积的SiO2构成。每个为15R碳化硅半导体区的基区11植入在碳化硅基片2上取向生长的碳化硅层3中，并相对于碳化硅层3相反掺杂。在基区11和碳化硅层3之间分别构成的p-n结17在D-MOSFET元件的截止状态下主要承受截止电压。在每个基区11内至少植入一个源区10，它相对于基区11相反掺杂，因而与相关的基区11分别构成p-n结18。每个源区10与相关的基区11通过源电极电短路。基区11优选用硼掺杂，因而是p型的。除此之外，它们也可以为了更高的闭锁强度在源区10的下面和基接触区12内在源电极15处通过附加植入铝而更加强烈地掺杂，因而是p+型的。源区10和碳化硅层3优选用氮掺杂，因而是n型的。漏极电极16设在碳化硅基片2的背对碳化硅层3的那一侧。尤其是可以在碳化硅基片2内再设一个植入的高度掺杂的漏极区。因此，此D-MOSFET有一种垂直结构。
若在所表示的实施形式中，碳化硅基片2与生长的碳化硅层3是相同的导通型，则产生一种MOSFET结构。反之，若此碳化硅基片2与碳化硅层3的导通型相反，则在层3与基片2之间形成了一个附加的源电极15与漏极电极16之间的p-n结。于是构成一种IGBT结构。
显然，所有提及的半导体区的导通型可以分别互换。
Claims (13)
1.一种半导体结构，它包含一个在预定的α碳化硅多型区与电绝缘区之间的界面，其中，在碳化硅区内界面处的电导率可通过感应电荷而加以改变，其特征在于：碳化硅区(3、10、11)采用与4H和6H碳化硅多型不同的α碳化硅多型，它的能带宽度最多等于6H碳化硅多型的能带宽度。
2.根据权利要求1所述的半导体结构，其特征在于：对于α碳化硅区选择一种多型，它的能带宽度比6H碳化硅多型的小，优选至少小5meV。
3.根据权利要求1所述的半导体结构，其特征在于：α碳化硅多型是一种R型。
4.根据权利要求3所述的半导体结构，其特征在于：此R型是15R型或21R型。
5.根据上述任一项权利要求所述的半导体结构，其特征在于：电绝缘区优选由不同材料制成的多层构成。
6.根据上述任一项权利要求所述的半导体结构，其特征在于：电绝缘区(13a)采用氧化材料。
7.根据权利要求6所述的半导体结构，其特征在于：采用SiO2作为氧化材料。
8.根据权利要求7所述的半导体结构，其特征在于：采用一种热SiO2作为SiO2材料。
9.根据上述任一项权利要求所述的半导体结构，其特征在于一种具有相同α碳化硅多型的结构。
10.根据权利要求1至8中任一项所述的半导体结构，其特征在于一种具有至少一个α碳化硅多型的结构。
11.根据上述任一项权利要求所述的半导体结构，其特征在于设计为MOSFET结构或IGBT结构。
12.根据权利要求11所述的半导体结构，其特征在于：MOSFET结构设计为D-或U-MOSFET结构。
13.一种根据上述任一项权利要求的半导体结构的应用，用于构造半导体器件或半导体电路。
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DE19736211.7 | 1997-08-20 | ||
| DE19736211 | 1997-08-20 |
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| Publication Number | Publication Date |
|---|---|
| CN1267397A true CN1267397A (zh) | 2000-09-20 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN98808324A Pending CN1267397A (zh) | 1997-08-20 | 1998-04-01 | 具有预定的α碳化硅区的半导体结构及此半导体结构的应用 |
Country Status (4)
| Country | Link |
|---|---|
| US (1) | US6316791B1 (zh) |
| EP (1) | EP1010204A1 (zh) |
| CN (1) | CN1267397A (zh) |
| WO (1) | WO1999009598A1 (zh) |
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-
1998
- 1998-04-01 CN CN98808324A patent/CN1267397A/zh active Pending
- 1998-04-01 WO PCT/DE1998/000931 patent/WO1999009598A1/de not_active Application Discontinuation
- 1998-04-01 EP EP98928113A patent/EP1010204A1/de not_active Withdrawn
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2000
- 2000-02-22 US US09/523,158 patent/US6316791B1/en not_active Expired - Fee Related
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1311534C (zh) * | 2000-10-03 | 2007-04-18 | 克里公司 | 利用n2o在碳化硅层上制造氧化物层的方法 |
| US9559172B2 (en) | 2013-03-22 | 2017-01-31 | Kabushiki Kaisha Toshiba | Semiconductor device and method of manufacturing the same |
Also Published As
| Publication number | Publication date |
|---|---|
| EP1010204A1 (de) | 2000-06-21 |
| US6316791B1 (en) | 2001-11-13 |
| WO1999009598A1 (de) | 1999-02-25 |
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