CN1306596C - Self-alignment process for flash memory - Google Patents

Self-alignment process for flash memory Download PDF

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Publication number
CN1306596C
CN1306596C CNB031464645A CN03146464A CN1306596C CN 1306596 C CN1306596 C CN 1306596C CN B031464645 A CNB031464645 A CN B031464645A CN 03146464 A CN03146464 A CN 03146464A CN 1306596 C CN1306596 C CN 1306596C
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China
Prior art keywords
silicide layer
sidewall
grid
annealing
layer
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CNB031464645A
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CN1571144A (en
Inventor
郑培仁
杨令武
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Macronix International Co Ltd
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Macronix International Co Ltd
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Abstract

The present invention relates to a self-alignment manufacturing process used for a quick-flashing memory body, the aim of which is to provide a memory body manufacturing method which guarantees the side wall of a gate electrode to be smooth, increases the pressurization of the gate electrode and prolongs the service life of the quick-flashing memory body. The present invention comprises a gate electrode forming step, the gate electrode which comprises a metallic silicium layer is formed on a penetrating oxide layer; a source electrode and a draw electrode forming step, the gate electrode is used as a shading cover; a metallic silicium side wall etching step; an oxidizing annealing processing step; a side wall edge lining forming step on the side of the gate electrode.

Description

The autoregistration processing procedure that is used for fast flash memory bank
Technical field
The invention belongs to method for manufacturing memory, particularly a kind of autoregistration processing procedure that is used for fast flash memory bank.
Background technology
On the complicated integrated circuit, dwindling of component size used to such an extent that design is difficult more, therefore, uses and uses autoregistration processing procedure or other technologies usually, to reach required design.
As shown in Figure 1, the grid structure 10a of typical fast flash memory bank comprise substrate 12a, be deposited on tunnel oxide (tunnel oxidel layer) 14a on the substrate 12a, be deposited on tunnel oxide (tunneloxidel layer) the last floating grid of 14a polysilicon layer 16a, be deposited on the ONO (oxide-nitride thing-oxide on the polysilicon layer 16a; Oxide-nitride-oxide) layer 18a, be deposited on ONO layer 18a go up the control grid polysilicon layer 20a, be deposited on polysilicon layer 20a go up the control grid tungsten silicide layer 22a, be deposited on mask 24a on the tungsten silicide layer 22a, be deposited on side walls limit lining 26a, 28a, be located at source electrode 30a and drain electrode 32a in the substrate 12a.
In the process of making grid structure, need in substrate 12a, to adopt deposition and etched processing procedure to finish gate stack, and use the autoregistration processing procedure to form source electrode 30a and drain electrode 32a, after forming side edge lining 26a, 28a, use the autoregistration processing procedure, as United States Patent (USP) the 5th, 907, No. 781 and 6, (process for fabricating an Integrated circuit with a self-alignedcontact) the autoregistration processing procedure that proposes in 444, No. 530 forms source electrode 30a and drain electrode 32a contact.
Owing in the grid structure of known fast flash memory bank, comprise tungsten silicide layer 22a, at follow-up hot processing procedure, during for example heating anneal is handled, the crystal structure of tungsten silicide becomes the hexagonal cubic crystal by four jiaos of cubic crystals, makes tungsten silicide be subjected to the influence of thermal stress and expand to cause critical dimension (Critical Dimension; The distance of increase CD) and shortening and contact hole, the latter further causes low breakdown voltage.Moreover, because the growth again of tungsten silicide crystal block (grain), extruding makes the sidewall of grid structure become coarse and uneven each other, increased internal field (local electrical filed) effect, cause point discharge to cause the damage of grid easily, make that the useful life of fast flash memory bank is of short duration.
Summary of the invention
The purpose of this invention is to provide and a kind ofly guarantee that gate lateral wall is level and smooth, increase gate withstand voltage, prolong the fast flash memory bank autoregistration processing procedure that is used for fast flash memory bank in useful life.
Present invention resides on the tunnel oxide that deposition first polysilicon layer, ONO layer, second polysilicon layer, tungsten silicide layer and mask form the formation grid step of the grid that contains metal silicide layer, with the grid are that shade forms source electrode and drain electrode step, etching metal silicon thing sidewall step, cleans the sidewall step, oxidizing annealing treatment step and form side edge lining step in the next door of grid; Cleaning the sidewall step is the sidewall that cleans tungsten silicide layer with the high solution of etching selectivity, forms pothole with etching on the sidewall of tungsten silicide layer; Form in the side edge lining step and between tungsten silicide layer and side edge lining, form the gap; The annealing in process step is that the Fast Heating under oxygen radical atmosphere is handled.
Wherein:
A kind of autoregistration processing procedure that is used for fast flash memory bank, it comprise in regular turn deposit the formation grid step of first polysilicon layer, ONO layer, second polysilicon layer, tungsten silicide layer and mask at tunnel oxide, with the grid be that shade forms source electrode and drain electrode step, cleans the sidewall step, annealing in process step and form side edge lining step in the next door of grid; Clean the sidewall of sidewall step system, form pothole with etching on the sidewall of tungsten silicide layer with the high solution cleaning tungsten silicide layer of etching selectivity; Form in the side edge lining step and between tungsten silicide layer and side edge lining, form the gap; The annealing in process step is that oxidizing annealing is handled; Use sidewall in the etching metal silicon thing sidewall step, form pothole with etching on the sidewall of metal silicide to the high solution etching metal silicide layer of metal silicide layer etching selectivity; The annealing in process step is that Fast Heating is handled; Fast Heating is treated to Fast Heating processing under oxygen radical atmosphere; Form in the sidewall lining step, between the sidewall of metal silicide layer and side edge lining, form the gap, with the minimizing thermal expansion stress.
Fast Heating is treated to and feeds hydrogen and oxygen in reative cell.
Air pressure in the reative cell is 5at to 50at.
Because present invention resides on the tunnel oxide formation grid step that forms the grid that contains metal silicide layer, with the grid be shade form source electrode and drain electrode step, etching on the sidewall of tungsten silicide layer form pothole cleaning sidewall step, serve as a contrast step at the Fast Heating treatment step under the oxygen radical atmosphere and in the formation side edge that forms the gap between the tungsten silicide layer on the next door of grid and the side edge lining.The sidewall of etching metal silicide layer, make that etching forms pothole on the sidewall of metal silicide layer, with in annealing in process, make and form the gap between metal silicide layer and the side edge lining, thereby the distance between increase metal silicide layer and the side edge lining, when metal silicide layer is subjected to the influence of thermal stress and expands, no longer produce and push and destroy grid, therefore, it is level and smooth that the surface of metal silicide layer keeps, and the distance between unlikely shortening and the contact hole, thereby do not produce the adverse consequences that internal field rises and breakdown voltage reduces.Guarantee that not only gate lateral wall is level and smooth, increase gate withstand voltage, and prolong fast flash memory bank useful life, thereby reach purpose of the present invention.
Description of drawings
Fig. 1, be typical flash memory body structural representation cutaway view.
Fig. 2, form grid, source electrode and drain electrode step schematic diagram for the present invention.
Fig. 3, form side edge lining step schematic diagram for the present invention.
Fig. 4, for make grid distortion schematic diagram with prior art method.
Fig. 5, for make the micrograph of traditional grid with conventional method.
Fig. 6, be the micrograph of the grid made with the present invention.
Embodiment
The present invention includes following steps:
Step 1
Form grid 10
As shown in Figure 2, deposit tunnel oxides (tunnel oxidel layer) 14, be deposited as first polysilicon layer 16 of floating grid, on first polysilicon layer 16, deposit ONO (oxide-nitride thing-oxide in substrate 12 at tunnel oxide (tunnel oxidel layer) 14; Oxide-nitride-oxide) layer 18, second polysilicon layer 20 that is deposited as the control grid on the ONO layer 18, on second polysilicon layer 20 deposit tungsten suicide layers 22, on tungsten silicide layer 22 deposition mask 24, to form grid 10.Also can be and on tunnel oxide (tunnel oxidel layer) 14, form the gate stack that contains metal silicide layer.
Step 2
Form source electrode 30 and drain 32
With grid 10 is that shade forms source electrode 30 and drains 32 in substrate 12.
Step 3
Clean sidewall
Clean the sidewall of tungsten silicide layer 22 or metal silicide layer with the high solution of etching selectivity, preferable system uses SC-1 to clean tungsten silicide layer 22 or metal silicide layer, with the sidewall of etching tungsten silicide layer 22 or metal silicide layer, the critical dimension of control tungsten silicide layer 22 or metal silicide layer; SC-1 is the alkaline peroxide mixed liquor that five parts of deionized waters add the ammoniacal liquor composition of a 30% hydrogen peroxide, portion 29%.When using the high solution of etching selectivity to clean, the etch-rate of tungsten silicide layer 22 or metal silicide layer each layer than other is fast, and therefore, as shown in Figure 3, etching forms pothole on the sidewall of tungsten silicide layer 22 or metal silicide layer.
Step 4
Annealing in process
In containing the environment of oxygen radical, carry out oxidation rapid thermal treatment (RTP), make grid 10, source electrode 30 and 32 activation and form oxide layer and prevent electric leakage of draining in first polysilicon layer, 16 outer rims of floating grid.Heat treated ties up to Fast Heating processing (Rapid Thermal Processing under the oxygen radical atmosphere; RTP), the thermal oxidation under this atmosphere is because be that surface reaction is main mechanism, and can make tungsten silicide layer 22 or metal silicide laminar surface keep smooth and be not easy to make tungsten silicide layer 22 or metal silicide layer expands.When use is quickened heat treated under oxygen radical atmosphere, hydrogen and oxygen are being passed through in the reative cell to the low pressure of 50at (Bristol) about 5at (Bristol) greatly.Make the crystal structure of tungsten silicide layer 22 or metal silicide layer become the hexagonal cubic crystal in the annealing in process by four jiaos of cubic crystals.
Step 5
Form side edge lining 26,28
Make the crystal structure of tungsten silicide layer 22 or metal silicide layer become the hexagonal cubic crystal in the annealing in process by four jiaos of cubic crystals.As shown in Figure 3, after tungsten silicide layer 22 or metal silicide layer become the hexagonal cubic crystal, carry out the deposition of silicon nitride or silicon dioxide layer and etching and form side edge lining 26,28 in grid 10 sidewalls.Etching formed pothole on the sidewall of tungsten silicide layer 22 metal silicide layers owing to before used high solution cleaning tungsten silicide layer 22 of etching selectivity or etching metal silicide layer, make tungsten silicide layer 22 or metal silicide layer and side edge serve as a contrast 26, form gap 34 between 28,36, thereby increase tungsten silicide layer 22 or metal silicide layer and side edge lining 26, distance between 28, when tungsten silicide layer 22 or metal silicide layer are subjected to the influence of thermal stress and expand, no longer produce and push and destroy grid 10, therefore, it is level and smooth that the surface of tungsten silicide layer 22 or metal silicide layer keeps, and the distance between unlikely shortening and the contact hole, thereby do not produce the adverse consequences that internal field rises and breakdown voltage reduces.
As shown in Figure 4, in traditional brake structure made from traditional autoregistration processing procedure, its tungsten silicide layer is subjected to the influence of thermal stress and expands, owing to having unnecessary space, tungsten silicide layer do not accept the volume that the thermal stress influence is expanded, the crystal block mutual extrusion that causes tungsten silicide layer inside makes the critical dimension of tungsten silicide increase and reduces breakdown voltage between grid and the contact hole.
The present invention ties up to the gap 34,36 that forms between tungsten silicide layer 22 and the side edge lining 26,28 as the buffer area, when tungsten silicide layer 22 is subjected to thermal stress influence and when expanding, the expansion of 34,36 buffering tungsten silicide layers 22 by the gap and do not influence the structure of tungsten silicide layer 22 inside.
As shown in Figure 5, in the micrograph of the grid structure that conventional process is made, the surface that can see is squeezed after tungsten silicide layer is because of the thermal stress expansion makes sidewall is very coarse.
As shown in Figure 6, in the micrograph of the grid structure that the present invention makes, can see that its sidewall surfaces is very level and smooth because of tungsten silicide layer is not squeezed because of thermal stress expands.Therefore the present invention obviously improves the easy shortcoming of damaging of grid structure that known techniques is made.

Claims (4)

1, a kind of autoregistration processing procedure that is used for fast flash memory bank, it comprise in regular turn deposit the formation grid step of first polysilicon layer, ONO layer, second polysilicon layer, tungsten silicide layer and mask at tunnel oxide, be that shade forms source electrode and drain electrode step, annealing in process step and forms side edge lining step in the next door of grid with the grid; It is characterized in that comprising cleaning sidewall step before the described annealing in process step, it is the sidewall that cleans tungsten silicide layer with the high solution of etching selectivity, forms pothole with etching on the sidewall of tungsten silicide layer; Form in the side edge lining step and between tungsten silicide layer and side edge lining, form the gap; The annealing in process step is that the Fast Heating under oxygen radical atmosphere is handled.
2, a kind of autoregistration processing procedure that is used for fast flash memory bank, it is included on the tunnel oxide formation grid step that forms the grid that contains metal silicide layer, be that shade forms source electrode and drain electrode step, annealing in process step and forms side edge lining step in the next door of grid with the grid; It is characterized in that comprising etching metal silicon thing sidewall step before the described annealing in process step; The annealing in process step is that oxidizing annealing is handled; Use sidewall in the etching metal silicon thing sidewall step, form pothole with etching on the sidewall of metal silicide to the high solution etching metal silicide layer of metal silicide layer etching selectivity; The annealing in process step is that Fast Heating is handled; Fast Heating is treated to Fast Heating processing under oxygen radical atmosphere; Form in the sidewall lining step, between the sidewall of metal silicide layer and side edge lining, form the gap, with the minimizing thermal expansion stress.
3, the autoregistration processing procedure that is used for fast flash memory bank according to claim 2 is characterized in that described Fast Heating is treated to feeding hydrogen and oxygen in reative cell.
4, the autoregistration processing procedure that is used for fast flash memory bank according to claim 3 is characterized in that the air pressure in the described reative cell is 5at to 50at.
CNB031464645A 2003-07-15 2003-07-15 Self-alignment process for flash memory Expired - Fee Related CN1306596C (en)

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CN103730344B (en) * 2012-10-12 2016-10-26 上海华虹宏力半导体制造有限公司 The method forming the monox lateral wall of metallic silicon tangsten silicide grid

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6143611A (en) * 1998-07-30 2000-11-07 Micron Technology, Inc. Semiconductor processing methods, methods of forming electronic components, and transistors
US6180454B1 (en) * 1999-10-29 2001-01-30 Advanced Micro Devices, Inc. Method for forming flash memory devices
CN1402334A (en) * 2001-08-09 2003-03-12 旺宏电子股份有限公司 Method for mfg. semiconductor internal storage module with gate stacked dielectric layer
US6573139B2 (en) * 2000-10-27 2003-06-03 Samsung Electronics Co., Ltd. Method of fabricating cell of flash memory device

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6143611A (en) * 1998-07-30 2000-11-07 Micron Technology, Inc. Semiconductor processing methods, methods of forming electronic components, and transistors
US6180454B1 (en) * 1999-10-29 2001-01-30 Advanced Micro Devices, Inc. Method for forming flash memory devices
US6573139B2 (en) * 2000-10-27 2003-06-03 Samsung Electronics Co., Ltd. Method of fabricating cell of flash memory device
CN1402334A (en) * 2001-08-09 2003-03-12 旺宏电子股份有限公司 Method for mfg. semiconductor internal storage module with gate stacked dielectric layer

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