CN1306598C - Method for manufacturing high ultraviolet-critical potential EEPROM - Google Patents
Method for manufacturing high ultraviolet-critical potential EEPROM Download PDFInfo
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- CN1306598C CN1306598C CNB2003101216325A CN200310121632A CN1306598C CN 1306598 C CN1306598 C CN 1306598C CN B2003101216325 A CNB2003101216325 A CN B2003101216325A CN 200310121632 A CN200310121632 A CN 200310121632A CN 1306598 C CN1306598 C CN 1306598C
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- making
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- electrically erasable
- erasable read
- threshold voltage
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- 238000000034 method Methods 0.000 title claims abstract description 32
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 8
- 230000015654 memory Effects 0.000 claims abstract description 37
- 238000007667 floating Methods 0.000 claims abstract description 23
- 239000000758 substrate Substances 0.000 claims abstract description 13
- 229910052796 boron Inorganic materials 0.000 claims abstract description 8
- 239000000463 material Substances 0.000 claims abstract description 7
- 238000005468 ion implantation Methods 0.000 claims abstract description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 17
- 229920005591 polysilicon Polymers 0.000 claims description 15
- 230000004888 barrier function Effects 0.000 claims description 9
- 238000002513 implantation Methods 0.000 claims description 8
- 229940090044 injection Drugs 0.000 claims description 7
- 238000002347 injection Methods 0.000 claims description 7
- 239000007924 injection Substances 0.000 claims description 7
- 239000007943 implant Substances 0.000 claims description 5
- 230000002093 peripheral effect Effects 0.000 claims description 5
- 238000005530 etching Methods 0.000 claims description 4
- 230000003647 oxidation Effects 0.000 claims description 4
- 238000007254 oxidation reaction Methods 0.000 claims description 4
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 3
- 229910052760 oxygen Inorganic materials 0.000 claims description 3
- 239000001301 oxygen Substances 0.000 claims description 3
- 238000009413 insulation Methods 0.000 claims description 2
- 239000002184 metal Substances 0.000 claims description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims 2
- 239000013078 crystal Substances 0.000 abstract description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract 4
- 150000001875 compounds Chemical class 0.000 abstract 4
- 229910052710 silicon Inorganic materials 0.000 abstract 4
- 239000010703 silicon Substances 0.000 abstract 4
- 230000005641 tunneling Effects 0.000 abstract 2
- -1 boron ions Chemical class 0.000 abstract 1
- 150000002500 ions Chemical class 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- RTZKZFJDLAIYFH-UHFFFAOYSA-N Diethyl ether Chemical compound CCOCC RTZKZFJDLAIYFH-UHFFFAOYSA-N 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 2
- 238000000137 annealing Methods 0.000 description 1
- 239000000428 dust Substances 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 230000005055 memory storage Effects 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 238000007639 printing Methods 0.000 description 1
- 230000001737 promoting effect Effects 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- 238000005496 tempering Methods 0.000 description 1
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Abstract
The present invention relates to a method for producing high ultraviolet-critical potential electrical erasable and programmable read-only memories, which comprises the following steps: a tunneling oxide layer is formed on a substrate, and then a first compound crystal silicon layer is formed on the tunneling oxide layer, wherein the first compound crystal silicon layer is produced by an ion-implantation method through implanting boron ions; the first compound crystal silicon layer is etched later to form floating gate structure, a drain electrode area and a source electrode area are formed in the substrate at the side of the floating gate structure, an insulating layer is formed on floating gate electrodes later and used as a dielectric layer between gate electrodes, and materials of the dielectric layer between the gate electrodes contain ONO or NO; an oxide layer with high critical potential is produced in an area with high critical potential, and a second compound crystal silicon layer is formed and used as a control gate electrode of an assembly with low critical potential and a gate electrode of an HV assembly with high critical potential simultaneously; the control gate electrode of the LV assembly with low critical potential and gate electrode patterns of the HV assembly are produced by a lithography program, and ions are implanted into an HV assembly area through an oblique angle for producing a light-doped drain electrode area LDD.
Description
Technical field
The present invention relates to a kind of semiconductor subassembly, and the high ultraviolet of particularly a kind of making (Ultra Violet, UV)-threshold voltage (Threshold Voltage, VT) method of Electrically Erasable Read Only Memory (EEPROM).
Background technology
The trend of manufacture of semiconductor constantly develops towards promoting chip packaging density, so the design of assembly is just constantly towards the idea evolution of saving the space.For assembly is dwindled, the size of assembly has been contracted to time micron or the scope of meter level how.Along with semi-conductive evolution, size of components is also dwindled in the manufacturing of non-volatile along with trend, non-volatile comprises the assembly of different types, read-only memory for example able to programme (PROM), erasable programmable read-only memory (EPROM), fast flash memory (flash), Electrically Erasable Read Only Memory (EEPROM) etc.Fast flash memory (flash) or the non-volatile memory element of EEPROM comprise one can store charge floating grid (floating gate) and control grid (control gate), generally can be divided into folded grid formula (stackedgate) and divide grid formulas (split gate) two kinds of forms.In a single day data deposits after the disk, just no longer needs any power source to be used for keeping data.But even be the data of retain stored more than at least ten years still after turning off with present technology power supply.Be not digital camera, mobile computer, the palm type electronic memo pad, electronic products such as mobile phone, to the demand of non-volatile memory element, inseparable especially.Portable computer and telecommunications industry have become the main drive of semiconductor integrated circuit designing technique.For example, fast flash memory (flash) or electricallyerasable ROM (EEROM) EEPROM can be applied in the ROM-BIOS (BIOS) in the computer, and the range of application of high density non-volatile then comprises the adapter of big capacity memory storage, digital solid-state camera and personal computer in the Portable terminal equipment etc.
Present low-voltage fast flash memory carries out the charge or discharge action to suspended grid usually under 3 to 5 volts operating voltage.For in the electricallyerasable ROM (EEROM) EEPROM processing procedure now, for reaching low programmed threshold voltage (low programming VT) to obtain high read current, UV-VT can not the ether height.Usually, high ultraviolet (UltraViolet, UV)-(ThresholdVoltage, VT) down this storage element is the low threshold voltage unit to threshold voltage.
Summary of the invention
Purpose of the present invention is for proposing a kind of method of making high ultraviolet-threshold voltage Electrically Erasable Read Only Memory.
The invention provides a kind of method of making high ultraviolet-threshold voltage Electrically Erasable Read Only Memory, its feature comprises the formation tunnel oxide on a substrate; Form first polysilicon layer on above-mentioned tunnel oxide, the making of wherein above-mentioned first polysilicon layer comprises to be adopted ion implantation that boron (boron) ion is injected to form, and energy that wherein above-mentioned ion injects and implantation dosage are respectively about 5 to 50KeV and 1E14 to 5E15 atom/square centimeter; Etching first polysilicon layer forms the floating grid structure.Form drain electrode and source region in the substrate of floating grid structure side, form an insulating barrier on floating grid (floating gate) as intergate dielectric layer, wherein the material of above-mentioned intergate dielectric layer comprises ONO or NO; Make high critical potential oxide layer (HVOX) in high threshold voltage (HV) zone, form second polysilicon layer simultaneously as low threshold voltage (LOW Voltage, LV) grid of control grid of assembly (control gate) and HV assembly; Utilize lithographic procedures to make the gate pattern of this LV assembly control grid and HV assembly and utilize the oblique angle to inject ion and enter the HV device region to make light dope drain region (lightIv doped drain region; LDD).The energy that the ion of wherein above-mentioned making light dope drain region injects is about 20 to 200KeV.Implantation dosage is about 1E12 to 1E15 atom/square centimeter.The implant angle of wherein above-mentioned making light dope drain region is about the 0-60 degree.
Description of drawings
Preferred embodiment of the present invention will be aided with following figure and do more detailed elaboration in comment backward:
Fig. 1 is the schematic diagram of formation floating grid of the present invention.
Fig. 2 forms the schematic diagram of intergate dielectric layer for the present invention.
Fig. 3 forms the schematic diagram of HV assembly LDD for the present invention.
Fig. 4 forms the schematic diagram of insulating barrier and conductive plug for the present invention.
Embodiment
The brand-new method that the invention provides is in order to make high ultraviolet-threshold voltage Electrically Erasable Read Only Memory.Embodiments of the invention cooperate icon to be described in detail as follows.
At first consult Fig. 1, semi-conductive substrate (substrate) 2 is provided, in preferred embodiment, substrate 2 is that crystal plane is to＜100〉or＜111 monocrystalline silicon (single crystal silicon).Other semiconductor material can also be used.General each inter-module on substrate 2 all can form several isolated areas (not icon), and the formation of this isolated area can stope oxidation isolation method or trench isolation method.Then form on substrate 2 by the tunnel oxide (tuning oxide) 4 that silica constituted, this tunnel oxide 4 generally can grow up to thermal oxidation method in the oxygen environment below about 700 to 1100 degree of Celsius temperature.In addition, also can adopt other method to form this tunnel oxide 4.In the present embodiment, the thickness of tunnel oxide 4 is about the 60-150 dust.Then, doped polycrystalline silicon layer 6 is deposited on the tunnel oxide 4.The making of this polysilicon layer 6 can be adopted with ion implantation the injection of boron (boron) ion is formed.Energy that this ion injects and implantation dosage are respectively about 5 to 50KeV and 1E14 to 5E15 atom/square centimeter.After the boron ion injected and reaches boiler tube tempering subsequently or the annealing that is rapidly heated (RTA anneal), printing definition floating grid (Floating Gate) was made floating grid (Floating Gate) by etch process, as shown in Figure 1 then.(After?B?implant?and?the?following?furnace?orRTA?anneal，a?Litho?step?is?used?to?define?the?Floating-Gate，then?followed?bya?etching?process?to?pattern?the?Floating?Gate.)
As shown in Figure 1, carry out ion with grid and photoresistance 10 as mask subsequently and inject (ionimplantation) to form drain electrode and source region 8.Remove photoresistance 10 afterwards; Subsequently, form an insulating barrier 12 on floating grid (floating gate), as intergate dielectric layer, material can adopt ONO or NO.Afterwards, (LITHOGRAPHY) defines its pattern with lithographic process, consults Fig. 2; Then (High Voltage, HV) zone makes high threshold voltage oxide layer (HVOX) 14 in high threshold voltage.
Subsequent steps is for making the grid that second polysilicon layer 16 is selected grid (select-gate) and peripheral (periphery) assembly as control grid (control gate) and the Electrically Erasable Read Only Memory photoelectric subassembly high threshold voltage (EEPROM Cell HV) of Electrically Erasable Read Only Memory photoelectric subassembly (EEPROM Cell) simultaneously.Utilize lithographic procedures to produce the gate pattern of control grid and HV assembly subsequently, as shown in Figure 3.Afterwards, utilize the oblique angle to inject ion and enter the HV device region to make light dope drain region (lightly doped drain region; LDD) 18.Energy that this ion injects and implantation dosage are respectively about 20 to 200KeV and 1E12 to 1E15 atom/square centimeter.This implant angle is about the 0-60 degree.At last, cover an insulating barrier 20 with as insulation applications, and make metal plug (conductive plug) 22 among insulating barrier 20, as shown in Figure 4 with known technology in two device region.
Claims (16)
1. method of making high ultraviolet-threshold voltage Electrically Erasable Read Only Memory, its feature comprises:
Form tunnel oxide on a substrate;
Form first polysilicon layer on above-mentioned tunnel oxide, described polysilicon layer is the boron doped polycrystalline silicon;
This first polysilicon layer of etching forms the floating grid structure;
Form drain electrode and source region in the substrate of this floating grid structure side;
Form an insulating barrier on this floating grid, as intergate dielectric layer;
Make high critical potential oxide layer in high critical potential zone;
Form second polysilicon layer simultaneously as the control grid of Electrically Erasable Read Only Memory assembly, select the grid of grid and peripheral assembly;
Utilize lithographic procedures to make the control grid of this Electrically Erasable Read Only Memory assembly, select grid and peripheral assembly gate pattern;
Utilize the oblique angle to inject ion and enter this high critical potential device region to make the light dope drain region.
2. the method for the high ultraviolet of making as claimed in claim 1-threshold voltage Electrically Erasable Read Only Memory is characterized in that, described tunnel oxide forms with thermal oxidation method in the oxygen environment below Celsius temperature 700 to 1100 degree.
3. the method for the high ultraviolet of making as claimed in claim 1-threshold voltage Electrically Erasable Read Only Memory is characterized in that, the making of described boron doped polysilicon layer comprises adopts ion implantation that the injection of boron ion is formed.
4. the method for the high ultraviolet of making as claimed in claim 3-threshold voltage Electrically Erasable Read Only Memory is characterized in that, energy that described boron ion injects and implantation dosage are respectively 5 to 50KeV and 1E14 to 5E15 atom/square centimeter.
5. the method for the high ultraviolet of making as claimed in claim 1-threshold voltage Electrically Erasable Read Only Memory is characterized in that the material of described intergate dielectric layer comprises ONO.
6. the method for the high ultraviolet of making as claimed in claim 1-threshold voltage Electrically Erasable Read Only Memory is characterized in that the material of described intergate dielectric layer comprises NO.
7. the method for the high ultraviolet of making as claimed in claim 1-threshold voltage Electrically Erasable Read Only Memory is characterized in that, the energy that the ion of described making light dope drain region injects is 20 to 200KeV.
8. the method for the high ultraviolet of making as claimed in claim 1-threshold voltage Electrically Erasable Read Only Memory is characterized in that, the implantation dosage that the ion of described making light dope drain region injects is 1E12 to 1E15 atom/square centimeter.
9. the method for the high ultraviolet of making as claimed in claim 1-threshold voltage Electrically Erasable Read Only Memory is characterized in that, the implant angle of described making light dope drain region is the 0-60 degree.
10. the method for the high ultraviolet of making as claimed in claim 1-threshold voltage Electrically Erasable Read Only Memory is characterized in that, finishes after the above-mentioned making light dope drain region, more comprises:
Cover an insulating barrier with as insulation applications:
Make metal plug among this insulating barrier.
11. a method of making high ultraviolet-threshold voltage Electrically Erasable Read Only Memory, its feature comprises:
Form tunnel oxide on a substrate;
Form first polysilicon layer on above-mentioned tunnel oxide, the making of wherein above-mentioned first polysilicon layer comprises adopts ion implantation that the injection of boron ion is formed;
This first polysilicon layer of etching forms the floating grid structure;
Form drain electrode and source region in the substrate of this floating grid structure side;
Form an insulating barrier on this floating grid, as intergate dielectric layer, wherein the material of above-mentioned intergate dielectric layer comprises ONO or NO:
Make high critical potential oxide layer in high critical potential zone:
Form second polysilicon layer simultaneously as the control grid of Electrically Erasable Read Only Memory assembly, select the grid of grid and peripheral assembly;
Utilize lithographic procedures to make the control grid of this Electrically Erasable Read Only Memory assembly, select the gate pattern of grid and peripheral assembly; And
Utilize the oblique angle to inject ion and enter this high critical potential device region to make the light dope drain region.
12. the method for the high ultraviolet of making as claimed in claim 11-threshold voltage Electrically Erasable Read Only Memory is characterized in that, described tunnel oxide forms with thermal oxidation method in the oxygen environment below Celsius temperature 700 to 1100 degree.
13. the method for the high ultraviolet of making as claimed in claim 11-threshold voltage Electrically Erasable Read Only Memory is characterized in that, energy that described boron ion injects and implantation dosage are respectively 5 to 50KeV and 1E14 to 5E15 atom/square centimeter.
14. the method for the high ultraviolet of making as claimed in claim 11-threshold voltage Electrically Erasable Read Only Memory is characterized in that, the energy that the ion of described making light dope drain region injects is 20 to 200KeV.
15. the method for the high ultraviolet of making as claimed in claim 11-threshold voltage Electrically Erasable Read Only Memory is characterized in that, the implantation dosage that the ion of described making light dope drain region injects is 1E12 to 1E15 atom/square centimeter.
16. the method for the high ultraviolet of making as claimed in claim 11-threshold voltage Electrically Erasable Read Only Memory is characterized in that, the implant angle of described making light dope drain region is the 0-60 degree.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2003101216325A CN1306598C (en) | 2003-12-31 | 2003-12-31 | Method for manufacturing high ultraviolet-critical potential EEPROM |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2003101216325A CN1306598C (en) | 2003-12-31 | 2003-12-31 | Method for manufacturing high ultraviolet-critical potential EEPROM |
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| CN1635631A CN1635631A (en) | 2005-07-06 |
| CN1306598C true CN1306598C (en) | 2007-03-21 |
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| CNB2003101216325A Expired - Lifetime CN1306598C (en) | 2003-12-31 | 2003-12-31 | Method for manufacturing high ultraviolet-critical potential EEPROM |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101330057B (en) * | 2007-06-21 | 2010-10-06 | 中芯国际集成电路制造(上海)有限公司 | Electric programmable device with embedded EEPROM and preparation method thereof |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5101250A (en) * | 1988-06-28 | 1992-03-31 | Mitsubishi Denki Kabushiki Kaisha | Electrically programmable non-volatile memory device and manufacturing method thereof |
| US5216268A (en) * | 1991-09-23 | 1993-06-01 | Integrated Silicon Solution, Inc. | Full-featured EEPROM |
| CN1124409A (en) * | 1994-07-18 | 1996-06-12 | 现代电子产业株式会社 | Eeprom and method for fabricating the same |
| US6274411B1 (en) * | 1998-12-22 | 2001-08-14 | Stmicroelectronics S.R.L. | Method for manufacturing electronic devices, comprising non-salicided non-volatile memory cells, non-salicided HV transistors, and LV transistors with salicided junctions with few masks |
-
2003
- 2003-12-31 CN CNB2003101216325A patent/CN1306598C/en not_active Expired - Lifetime
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5101250A (en) * | 1988-06-28 | 1992-03-31 | Mitsubishi Denki Kabushiki Kaisha | Electrically programmable non-volatile memory device and manufacturing method thereof |
| US5216268A (en) * | 1991-09-23 | 1993-06-01 | Integrated Silicon Solution, Inc. | Full-featured EEPROM |
| CN1124409A (en) * | 1994-07-18 | 1996-06-12 | 现代电子产业株式会社 | Eeprom and method for fabricating the same |
| US6274411B1 (en) * | 1998-12-22 | 2001-08-14 | Stmicroelectronics S.R.L. | Method for manufacturing electronic devices, comprising non-salicided non-volatile memory cells, non-salicided HV transistors, and LV transistors with salicided junctions with few masks |
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| CN1635631A (en) | 2005-07-06 |
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Effective date of registration: 20111123 Address after: 201203 No. 18 Zhangjiang Road, Shanghai Co-patentee after: Semiconductor Manufacturing International (Beijing) Corp. Patentee after: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) Corp. Address before: 201203 Shanghai Zhangjiang Road, Zhangjiang High Tech Park of Pudong New Area No. 18 Patentee before: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) Corp. |
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