CN1307427C - Beam synthesizer and synthetic method based on linear interpolation - Google Patents
Beam synthesizer and synthetic method based on linear interpolation Download PDFInfo
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- CN1307427C CN1307427C CNB021346321A CN02134632A CN1307427C CN 1307427 C CN1307427 C CN 1307427C CN B021346321 A CNB021346321 A CN B021346321A CN 02134632 A CN02134632 A CN 02134632A CN 1307427 C CN1307427 C CN 1307427C
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Abstract
The present invention discloses a beam synthesizer and a synthetic method based on linear interpolation, and the aim is to provide an interpolation beam synthetic method with low cost and without transient output and a device of thereof. Two measures are used in the present invention: one measure is characterized in that a time delay memory adopts FIFO structure, receives time delay and dynamically adjusts with the thin time delay precision as a unit based on the starting time delay; the other measure is characterized in that apodization weighted coefficients are respectively merged two coefficients a and b of linear interpolation, and the interpolation and the apodization are completed together. The method is characterized in that the FIFO time delay memory stops working for a beat and the linear interpolation latch also stops for a beat whenever the cycle is up to the transient state DO in the process that a processor synthesizes and treats digitized echo signals. The method of the present invention is suitable for the digital beam synthesis in the receiving process of a medical ultrasonic diagnostic system.
Description
Technical field
Relate to and the present invention relates to the synthetic method and apparatus of digital beam in the medical ultrasonic diagnostic system, the wave beam that relates in particular in the receiving process is synthetic.Wave beam is synthetic to be the technology of most critical in the medical ultrasonic diagnostic system, and the quality of synthetic wave beam has a significant impact the accuracy and the resolution of ultrasonography.
Background technology
Beam synthesizer has the branch of simulation and numeral, the digital beam compositor is being better than traditional analog beam compositor aspect accuracy, stability and the dirigibility, along with the raising of digital device performance and the minimizing of cost, the synthetic analog beam that replaces just gradually of digital beam is synthesized, and what the present invention relates to is the digital beam compositor.
The synthetic gordian technique of digital beam is a digital delay, and digital delay is generally realized by dual port RAM.Each passage echoed signal writes the dual port RAM of each passage by same address after the A/D conversion, and when reading dual port RAM, each passage uses the different addresses of reading to obtain the synthetic required time-delay of wave beam.Delay precision depends on the A/D sampling rate, and this sampling rate is than big several times of Nyquist sampling rate, and general requirement is higher than 100MHz.
At Proceeding of the IEEE Vol.67, No.6, pp.904-919, in the June 1979 disclosed articles, Pridham and Mucci have proposed to reduce the requirement that the A/D conversion is taken a sample at a high speed by interpolation.The A/D sampling rate only need satisfy the Nyquist requirement, and delay memory provides a thick time-delay in the synthetic process of wave beam, and the synthetic required accurate delay of wave beam is then realized with the method for interpolation.After this, the synthetic research of interpolation type wave beam concentrates on the aspect that how to reduce cost.United States Patent (USP) 5345426 has proposed to realize with integral coefficient FIR wave filter the lower cost solution of interpolation; United States Patent (USP) 5544128 has proposed that interpolation filter is placed on wave beam and has formed lower cost solution afterwards.These interpolation type wave beam synthetic schemes in dynamic focusing with during dynamically the change mark is used, can't be avoided the transient state output of interpolation filter, thereby the synthetic quality of wave beam is affected.
Summary of the invention
The interpolation type beam synthesizing method and the device thereof that the objective of the invention is to overcome the deficiency of prior art existence and a kind of low-cost non-transient output is provided.
For achieving the above object, the present invention for example brings up to the above Nyquist sampling rate of twice by suitably improving the A/D sampling rate, interpolation filter is simplified to its minimum form---linear interpolation device.The linear interpolation device is placed on after the delay memory of each receiving cable, for the interpolation type beam synthesizer of realizing low-cost non-transient output provides possibility.Be to eliminate the transient state output of interpolator, the present invention has taked two measures: first delay memory has adopted fifo structure, and receiving time-delay is that unit dynamically adjusts with thin delay precision on the basis of initial time-delay; It two is to be dissolved into two coefficient a of linear interpolation respectively becoming the mark weighting coefficient, among the b, interpolation with become mark and finish in the lump.Concrete beam synthesizing method is as follows:
I. the echo from target is received by each array element of popping one's head in, and signal that each probe array element connects separately receives treatment channel;
Ii. receive in treatment channel at each signal, be exaggerated from the signal of probe array element, then with unified speed digitizing;
Iii. the echoed signal after the digitizing is admitted to each signal and receives treatment channel processor and handle;
Echoed signal after utilizing processor to digitizing is synthesized in the process of handling,
Iv. thick time-delay and the thin time-delay that provides signal to receive treatment channel respectively by delay memory with fifo structure and linear interpolation device, thick delay precision equals the radio frequency sampling interval T, and thin delay precision equals T divided by interpolation number of phases M;
V. all to have data sample to write fashionable for the time-delay reservoir that receives treatment channel when all signals, dynamic focusing open each signal receive the treatment channel delay memory read enable, and export the thin time-delay code S1S2S3S4 of five kinds of states, they are: a transient state D0=0000, four stable state D1=1000, D2=0100, D3=0010 and D4=0001; Each state each corresponding one group of linear interpolation coefficient a and b of thin time-delay code S1S2S3S4;
Vi. in the dynamic adjustment process of collectiong focusing time-delay, the code S1S2S3S4 that carefully delays time changes by the circulation law of D4 → D3 → D2 → D1 → D0 → D4, so that initial time-delay is dynamically adjusted, reaches the purpose of dynamic focusing;
Vii. when being circulated to transient state D0, FIFO time-delay reservoir stops reading a bat, the bat of also stopping work of the latch of linear interpolation device;
Viii. thin time-delay code is mapped as two interpolation coefficients, and two interpolation coefficients are multiplied each other with trace-changing coefficient respectively obtains becoming the mark interpolation coefficient, finish the merging of interpolation coefficient and channel weighting coefficient at last;
Ix. the output signal that merges of each passage is after device detects after testing, by the display screen video data.
According to above-mentioned beam synthesizing method, can design beam synthesizer based on linear interpolation, this beam synthesizer comprises:
Be used for the array element of respectively popping one's head in to tested body emission ultrasound wave and receiving target echo;
Be used to amplify each channel amplifier of echo that array element is exported of respectively popping one's head in;
Be used for the output of the simulating signal of each channel amplifier is converted to each passage A/D transducer of digital signal;
Be used for each passage A/D digital signal that transducer is exported is focused on each channel processor that time-delay, weighting and serial summation are handled;
The above-mentioned array element of respectively popping one's head in, each channel amplifier, each passage A/D transducer and each channel processor be unidirectional in order connect and compose a plurality of mutually independently signal receive treatment channel; Also comprise:
Be used to store data-carrier store and Read Controller and the scanning monitor that each passage focuses on delay data and becomes the mark data, all signals receive the output signal of treatment channel and synthesize after detecting device send display to show at last; It is characterized in that described each processor array element comprises:
Time-delay reservoir with fifo structure is used to provide signal to receive the thick time-delay of treatment channel;
The linear interpolation device is used to provide signal to receive the thin time-delay of treatment channel;
Dynamic focusing is used for providing to the time-delay reservoir and reads to enable control, and provides thin Delay-Code;
Initial time-delay is used to control writing of reservoir of time-delay and enables, and reaches the purpose of the initial time-delay of control;
Interpolation trace-changing coefficient generator is used for thin Delay-Code is mapped as interpolation coefficient, and calculates change mark interpolation coefficient;
The signal input port of linear interpolation device connects time-delay reservoir, dynamic focusing and interpolation trace-changing coefficient generator respectively, and its signal output part is through the first adder connection detector.
Compared with prior art, the beam synthesizer and the synthetic method thereof that the present invention is based on linear interpolation have following advantage: under the prerequisite that guarantees the quality that wave beam is synthetic, realize that the interpolation type wave beam of low-cost non-transient output is synthetic.
Description of drawings
The description of drawings of digital visual language repeater of the present invention is as follows:
Fig. 1 is the formation block scheme of a ultrasonic imaging apparatus;
Fig. 2 is the functional-block diagram according to each receiving cable processor of principle of the invention structure;
Fig. 3 is the functional-block diagram of initial time-delay logic;
Fig. 4 is the functional-block diagram of dynamic focusing logical block;
Fig. 5 is the functional-block diagram that the interpolation trace-changing coefficient produces logic;
Fig. 6 is the functional-block diagram of data-carrier store and Read Controller thereof.
Embodiment
For complete understanding the present invention better, be described in detail below in conjunction with a preferred embodiment of the present invention and accompanying drawing.
Fig. 1 is the formation block scheme of a ultrasonic imaging apparatus, and this ultrasonic imaging apparatus uses many array element probes, so beam synthesizer comprises a plurality of signal processing channels.Echo from target is received by each array element of popping one's head in, and each array element is connected to different receiving cables.In each receiving cable, from the probe array element signal be exaggerated, then with unified speed digitizing.In order to simplify description, the array element of supposing to pop one's head in has only four, but it also can be bigger.Four transmitters 10 to 13 produce conventional driving pulse, and incentive probe array element is to the body tissue emission ultrasound wave of tested person, and afterwards, these array elements receive the ultrasound wave that reflects again from the body tissue of tested person.At parallel receive channel 2 to 5, the echo that each array element receives is amplified by amplifier 14 to 17 respectively, carries out digitizing by A/D transducer 20 to 23 with unified speed respectively then.Echoed signal after the digitizing enters the processor of each passage, here finishes to focus on time-delay, weighting and serial summation.The output of processor 27 is wave beam composite signals, and this signal is detected by detecting device 6.For video data on display 9, must echo data be converted to vision signal with digital scan convertor 7.The all control of system is all carried out by the control signal that controller 8 produces.
Crucial part of the present invention is according to goal of the invention, and the structure of processor is improved.Fig. 2 is the functional-block diagram according to each receiving cable processor of principle of the invention structure; Described processor array element comprises:
Time-delay reservoir 30 with fifo structure is used to provide signal to receive the thick time-delay of treatment channel;
Dynamic focusing 32 is used for providing to time-delay reservoir 30 and reads to enable control, and provides thin Delay-Code;
Initial time-delay 31 is used to control writing of reservoir 30 of time-delay and enables, and reaches the purpose of the initial time-delay of control;
Interpolation trace-changing coefficient generator 33 is used for thin Delay-Code is mapped as interpolation coefficient, and calculates change mark interpolation coefficient;
The signal input port of linear interpolation device 39 connects time-delay reservoir 30, dynamic focusing 32 and interpolation trace-changing coefficient generator 33 respectively, and its signal output part is through first adder 38 connection detectors 6.
Described linear interpolation device 39 comprises first multiplier 35, second adder 37 and first latch 34 and second multiplier 36 that is linked in sequence, the input end of first latch 34 connects dynamic focusing 32, the output terminal that the input end of first multiplier 35 and second multiplier 36 is connected interpolation trace-changing coefficient generator 33, the second multipliers 36 is connected with second adder 37.Delay memory 30 adopts fifo structure, and its degree of depth is by required maximum delay amount decision, and read-write clock CKO is the radio frequency sampling clock.Delay memory 30 provides the thick time-delay of receiving cable to delay time with thin respectively with linear interpolation device 39, thick delay precision equals the radio frequency sampling interval T, thin delay precision equals T/M, and M is by required delay precision decision, and the span of T is generally between 40ns～25ns.M equals 4 in this example.Writing of delay memory enables to be provided by initial time-delay 31, and initial time-delay 31 enables according to required initial thick the writing of delay memory 30 of time-delay control of each receiving cable, and the required initial thin time-delay of each receiving cable is then provided by dynamic focusing 32.When the delay memory of all receiving cables all has data sample to write, dynamic focusing 32 open each communication channel delay storer 30 read enable, the clock of also opening simultaneously first latch 34 enables.The thin time-delay code s1s2s3s4 of dynamic focusing 32 output have five kinds may state: D0=0000, D1=1000, D2=0100, D3=0010, D4=0001, with the relation of linear interpolation coefficient a and b be: s1s2s3s4=1000 is a=1 then, b=0; S1s2s3s4=0100 is a=3/4 then, b=1/4; S1s2s3s4=0010 is a=2/4 then, b=2/4; S1s2s3s4=0001 is a=1/4 then, b=3/4; S1s2s3s4=0000 is a=1/4 then, b=3/4.In the dynamic adjustment process of collectiong focusing time-delay, five kinds of the code of carefully delaying time may change by a kind of circulation law by state: D4 change D3, D3 change D2, D2 change D1, D1 become D0, D0 and become D4.Suppose that current thin time-delay code status is D2=0100, when the collectiong focusing time-delay needed to adjust, D2 became D1, and interpolation coefficient becomes a=1, b=0 by a=3/4, b=1/4, and the output time-delay of linear interpolation device increases a thin timer T/M; When the collectiong focusing time-delay needed to adjust again, D1 became D0, but the D0 state only continues a radio frequency sampling cycle, becomes D4 then and settles out, and adjusted the collectiong focusing time-delay up to next time.So title D0 is a transient state, and claim that D1 to D4 is a stable state.The D0 state is the same with the interpolation coefficient of D4 state, but at the D0 state, and time-delay FIFO stops reading a bat, the bat of also stopping work of first latch 34.The effect of interpolation trace-changing coefficient generation unit 33 is that thin time-delay code is mapped as interpolation coefficient, and finishes the merging of interpolation coefficient and channel weighting coefficient.First adder 38 is links on the interchannel serial summation chain.
Described initial time-delay 31 comprises initial delay counter 40, second latch 41, first or door 42 and first and 43; The input/output terminal of second latch 41 connects data-carrier store and Read Controller 28 and initial delay counter 40, the first thereof respectively and is connected controller 8, initial delay counter 40 and time-delay reservoir 30 (Fig. 3) respectively with the input/output terminal of door 43; Initial delay counter 40 is to load counter, and it loads initial thick delay data before the take over period begins, and begins the back with radio frequency sampling rate counting in the take over period, opens writing of reservoir 30 of time-delay when meter is full and enables.A recurrence interval is divided into several periods, at first is the preset parameter phase, secondly is the pulse emission phase, is the echo take over period then, is the displacement period of output of time-delay FIFO at last.In the preset parameter phase, second latch 41 latchs the initial thick delay data of this passage; In the pulse emission phase, initial thick delay data loads counter 40; At the echo receiver, counter 40 begins counting, opens writing of FIFO of time-delay when meter is full and enables, and the counting of closing counter 40 simultaneously enables.
But described dynamic focusing 32 comprises loader cycle shift register 50, the 3rd latch 51, quad latch 52, the 5th latch 53, the tenth latch the 55, the 11 latch 58 and the 12 latch 59, second or door 54, the 3rd or door 56 and second and 57; The data input end of register 50 connects data-carrier store and Read Controller 28 thereof through the 3rd latch 51, its en input end through second or door the 54, the 5th latch 53, quad latch 52 connect data-carrier store and Read Controllers 28 thereof, its load input end directly connects controller 8 (Fig. 4); It loads initial thin delay data before the take over period begins, by ring shift left initial time-delay is adjusted dynamically in receiving process, to reach the purpose of dynamic focusing.The core of dynamic focusing 32 is circulating registers 50 of one 5.In the preset parameter phase, the 3rd latch 51 latchs the initial thin time-delay code of this passage, and initial thin time-delay code is in four stable states; On pulse emission phase, four on the right side of initial thin time-delay code loaded cycle shift register.Four outputs in the right side of circulating register are the code s1s2s3s4 that carefully delay time, they or output the displacement period of output of time-delay FIFO be used for controlling time-delay FIFO read enable.At the displacement period of output of time-delay FIFO, quad latch 52 latchs and focuses on the time-delay dynamic adjusting data, and focusing on the time-delay dynamic adjusting data is the data stream of 1bit.When quad latch 52 is latched into a high level, the 5th latch 53 becomes a phase shift pulse to this high level, the phase shift pulse is that width is the positive pulse in radio frequency sampling cycle, and the phase shift pulse is quad latch 52 zero clearings, also makes circulating register move to left one.When 1 in the circulating register moves on to Far Left, can be right after once displacement, make the D0 state of thin time-delay code only continue a radio frequency sampling cycle.
Described interpolation trace-changing coefficient generator 33 comprises combinational logic 60, the 6th latch 61, the 7th latch 62, the 8th latch 65 and the 9th latch 66, the 3rd multiplier 63 and the 4th multiplier 64; Combinational logic 60 is mapped as thin time-delay codes two the coefficient a and the b of linear interpolation device, the 6th latch 61 and the 7th latch 62 constitute two-stage trace-changing coefficient latch, the trace-changing coefficient timesharing is latched in the trace-changing coefficient latch of each passage first order in receiving process, upgrade the content of second level latch then at synchronization, trace-changing coefficient multiplies each other with interpolation coefficient a and b respectively in the 3rd multiplier 63 and the 4th multiplier 64, export change mark interpolation coefficient A and B respectively by the 8th latch 65 and the 9th latch 66 at last, with the purpose (Fig. 5) that reaches dynamic change mark.
Described data-carrier store and Read Controller 28 thereof comprise delay data storer 70 and become mark data-carrier store 71 and two data Read Controllers; Delay data storer 70 is stored the focusing delay data of different receiving cables respectively and is dynamically become the mark data with change mark data-carrier store 71.Comprise initial delay data and dynamic adjusting data in delay data storer 70, delay data storer 70 and change mark data-carrier store 71 respectively have the Read Controller of oneself.Delay data Read Controller 72 offers delay data storer 70 and reads the address, and change mark data Read Controller 73 offers change mark data-carrier store 71 and reads the address, and provides the latch pulse (Fig. 6) that each passage becomes the mark data.Delay data storer 70, change mark data-carrier store 71 are stored the focusing delay data of four receiving cables respectively and are dynamically become the mark data.In the delay data storer, comprise initial delay data and dynamic adjusting data.Delay data storer 70, change mark data-carrier store 71 respectively have the Read Controller of oneself.The delay data Read Controller offers delay data storer 70 and reads the address, provide dynamic adjusting data latch pulse CK1, give 8 initial delay data latch pulses, 4 initial thick delay datas that are used for latching four receiving cables wherein, 4 initial thin delay datas that then are used for latching four receiving cables in addition.Change mark data Read Controller offers change mark data-carrier store 71 and reads the address, and provides the latch pulse that four-way becomes the mark data.
Claims (10)
1, a kind of beam synthesizing method based on linear interpolation, this method comprises the steps:
I. the echo from target is received by each array element of popping one's head in, and signal that each probe array element connects separately receives treatment channel;
Ii. receive in treatment channel at each signal, be exaggerated from the signal of probe array element, then with unified speed digitizing;
Iii. the echoed signal after the digitizing is admitted to the processor that each signal receives treatment channel and handles;
It is characterized in that: the echoed signal after utilizing processor to digitizing is synthesized in the process of handling,
Iv. thick time-delay and the thin time-delay that provides signal to receive treatment channel respectively by delay memory with fifo structure and linear interpolation device, thick delay precision equals the radio frequency sampling interval T, and thin delay precision equals T divided by interpolation number of phases M;
V. all to have data sample to write fashionable for the time-delay reservoir that receives treatment channel when all signals, dynamic focusing open each signal receive the treatment channel delay memory read enable, and export the thin time-delay code S1S2S3S4 of five kinds of states, they are: a transient state D0=0000, four stable state D1=1000, D2=0100, D3=0010 and D4=0001; Each state each corresponding one group of linear interpolation coefficient a and b of thin time-delay code S1S2S3S4;
Vi. in the dynamic adjustment process of collectiong focusing time-delay, the code S1S2S3S4 that carefully delays time changes by the circulation law of D4 → D3 → D2 → D1 → D0 → D4, so that initial time-delay is dynamically adjusted, reaches the purpose of dynamic focusing;
Vii. when being circulated to transient state D0, FIFO time-delay reservoir stops reading a bat, the bat of also stopping work of the latch of linear interpolation device;
Viii. thin time-delay code is mapped as two interpolation coefficients, and interpolation coefficient and channel weighting coefficient are merged into change mark interpolation coefficient;
Ix. the output signal that merges of each passage is after device detects after testing, by the display screen video data.
2, the beam synthesizing method based on linear interpolation according to claim 1 is characterized in that: in described step e., the pass with linear interpolation coefficient a and b of the code S1S2S3S4 that carefully delays time is: S1S2S3S4=1000, then a=1, b=0; S1S2S3S4=0100, then a=3/4, b=1/4; S1S2S3S4=0010, then a=2/4, b=2/4; S1S2S3S4=0001, then a=1/4, b=3/4; S1S2S3S4=0000, then a=1/4, b=3/4.
3, the beam synthesizing method based on linear interpolation according to claim 1 is characterized in that: the span of described radio frequency sampling interval T is between 40ns～25ns, and interpolation number of phases M is generally 4.
4, a kind of beam synthesizer based on linear interpolation comprises:
Be used for the array element of respectively popping one's head in to tested body emission ultrasound wave and receiving target echo;
Be used to amplify each channel amplifier of echo that array element is exported of respectively popping one's head in;
Be used for the analog signal conversion of each channel amplifier is become each passage A/D transducer of digital signal;
Be used for each passage A/D digital signal that transducer is exported is focused on each channel processor that time-delay, weighting and serial summation are handled;
The above-mentioned array element of respectively popping one's head in, each channel amplifier, each passage A/D transducer and each channel processor be unidirectional in order connect and compose a plurality of mutually independently signal receive treatment channel; Also comprise:
Be used to store data-carrier store and Read Controller (28) and the controller (8) that each passage focuses on delay data and becomes the mark data, all signals receive the output signal of treatment channel and synthesize after detecting device (6) send display (9) to show at last; It is characterized in that described each channel processor comprises:
Time-delay reservoir (30) with fifo structure is used to provide signal to receive the thick time-delay of treatment channel;
Linear interpolation device (39) is used to provide signal to receive the thin time-delay of treatment channel;
Dynamic focusing (32) is used for providing to time-delay reservoir (30) and reads to enable control, and provides thin Delay-Code;
Initial time-delay (31) is used for writing of control time-delay reservoir (30) and enables, and reaches the purpose of the initial time-delay of control;
Interpolation trace-changing coefficient generator (33) is used for thin Delay-Code is mapped as interpolation coefficient, and calculates change mark interpolation coefficient;
The signal input port of linear interpolation device (39) connects time-delay reservoir (30), dynamic focusing (32) and interpolation trace-changing coefficient generator (33) respectively, and its signal output part is through first adder (38) connection detector (6).
5, the beam synthesizer based on linear interpolation according to claim 4, it is characterized in that: described linear interpolation device (39) comprises first multiplier (35), second adder (37) and first latch (34) and second multiplier (36) that is linked in sequence, the clock Enable Pin of first latch (34) connects dynamic focusing (32), the input end of first multiplier (35) and second multiplier (36) is connected interpolation trace-changing coefficient generator (33), and the output terminal of second multiplier (36) is connected with second adder (37).
6, the beam synthesizer based on linear interpolation according to claim 4 is characterized in that: described initial time-delay (31) comprises initial delay counter (40), second latch (41), first or door (42) and first and (43); The input/output terminal of second latch (41) connects data-carrier store and Read Controller (28) and initial delay counter (40) respectively, and first is connected controller (8), initial delay counter (40) respectively and the reservoir (30) of delaying time with the input/output terminal of door (43); Initial delay counter (40) is to load counter, and it loads initial thick delay data before the take over period begins, and begins the back with radio frequency sampling rate counting in the take over period, opens writing of time-delay reservoir (30) when meter is full and enables.
7, the beam synthesizer based on linear interpolation according to claim 4 is characterized in that: described dynamic focusing (32) but comprise loader cycle shift register (50), the 3rd latch (51), quad latch (52), the 5th latch (53), the tenth latch (55), the 11 latch (58) and the 12 latch (59), second or door (54), the 3rd or door (56) and second and (57); The data input end of register (50) connects data-carrier store and Read Controller (28) thereof through the 3rd latch (51), its en input end through second or door (54), the 5th latch (53), quad latch (52) connect data-carrier store and Read Controller (28) thereof, its load input end directly connects controller (8); It loads initial thin delay data before the take over period begins, by ring shift left initial time-delay is adjusted dynamically in receiving process, to reach the purpose of dynamic focusing.
8, the beam synthesizer based on linear interpolation according to claim 4 is characterized in that: described interpolation trace-changing coefficient generator (33) comprises combinational logic (60), the 6th latch (61), the 7th latch (62), the 8th latch (65) and the 9th latch (66), the 3rd multiplier (63) and the 4th multiplier (64); Combinational logic (60) is mapped as thin time-delay code two the coefficient a and the b of linear interpolation device, the 6th latch (61) and the 7th latch (62) constitute two-stage trace-changing coefficient latch, the trace-changing coefficient timesharing is latched in the trace-changing coefficient latch of each passage first order in receiving process, upgrade the content of second level latch then at synchronization, trace-changing coefficient multiplies each other with interpolation coefficient a and b respectively in the 3rd multiplier (63) and the 4th multiplier (64), export change mark interpolation coefficient A and B respectively by the 8th latch (65) and the 9th latch (66) at last, to reach the purpose of dynamic change mark.
9, the beam synthesizer based on linear interpolation according to claim 4 is characterized in that: described data-carrier store and Read Controller thereof (28) comprise delay data storer (70) and become mark data-carrier store (71) and two data Read Controllers; Delay data storer (70) is stored the focusing delay data of different receiving cables respectively and is dynamically become the mark data with change mark data-carrier store (71); Comprise initial delay data and dynamic adjusting data in delay data storer (70), delay data storer (70) and change mark data-carrier store (71) respectively have the Read Controller of oneself; Delay data Read Controller (72) offers delay data storer (70) and reads the address, and change mark data Read Controllers (73) offer change mark data-carrier store (71) and read the address, and provides the latch pulse that each passage becomes the mark data.
10, the beam synthesizer based on linear interpolation according to claim 5, it is characterized in that: first latch (34) of described linear interpolation device (39) has a clock and enables control end, the sample that is used for the last output of temporary time-delay reservoir (30), and its clock enables control end and time-delay reservoir (30) dress reads to enable a shared signal.
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| CN101373181B (en) * | 2007-08-24 | 2012-03-21 | 深圳迈瑞生物医疗电子股份有限公司 | Method and apparatus for calculating point-to-point trace-changing coefficient in real time |
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| CN104914440B (en) * | 2015-06-23 | 2017-06-16 | 重庆大学 | A kind of compressed sensing ultrasonic beam synthetic method for merging dynamic aperture |
| JP6038259B1 (en) * | 2015-10-20 | 2016-12-07 | 株式会社日立製作所 | Ultrasonic diagnostic equipment |
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| CN1212146A (en) * | 1997-05-27 | 1999-03-31 | 索诺塞特公司 | Hand held ultrasonic diagnostic instrument with digital beamformer |
| CN2387863Y (en) * | 1999-07-19 | 2000-07-19 | 开曼迈瑞医疗电子(深圳)有限公司 | All-number real-time B-mode ultrasonic receiving dynamic apodization beam synthetic device |
| CN1286963A (en) * | 1999-09-08 | 2001-03-14 | 开曼迈瑞医疗电子(深圳)有限公司 | Full-digital wave beam synthesizer for B-mode ultrasonic diagnostic equipment |
| US6315723B1 (en) * | 1999-10-08 | 2001-11-13 | Atl Ultrasound | Ultrasonic diagnostic imaging system with synthesized transmit focus |
-
2002
- 2002-08-28 CN CNB021346321A patent/CN1307427C/en not_active Expired - Fee Related
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5345426A (en) * | 1993-05-12 | 1994-09-06 | Hewlett-Packard Company | Delay interpolator for digital phased array ultrasound beamformers |
| US5544128A (en) * | 1994-07-05 | 1996-08-06 | Siemens Medical Systems, Inc. | Multi-beam digital beamforming method and apparatus |
| CN1212146A (en) * | 1997-05-27 | 1999-03-31 | 索诺塞特公司 | Hand held ultrasonic diagnostic instrument with digital beamformer |
| CN2387863Y (en) * | 1999-07-19 | 2000-07-19 | 开曼迈瑞医疗电子(深圳)有限公司 | All-number real-time B-mode ultrasonic receiving dynamic apodization beam synthetic device |
| CN1286963A (en) * | 1999-09-08 | 2001-03-14 | 开曼迈瑞医疗电子(深圳)有限公司 | Full-digital wave beam synthesizer for B-mode ultrasonic diagnostic equipment |
| US6315723B1 (en) * | 1999-10-08 | 2001-11-13 | Atl Ultrasound | Ultrasonic diagnostic imaging system with synthesized transmit focus |
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