CN1309090C - Thin film transistors with self aligned light dosed resource structure and their manufacture - Google Patents

Abstract

The present invention relates to a thin film transistor with a self-aligned lightly doped drain structure. An effective layer comprises a channel district, a first doping district and a second doping district. A gate electrode insulation layer is formed on the effective layer, and comprises at least one central district, a shielding district and an extending district, wherein the central district is covered on the channel district. The shielding district is positioned on the periphery of the central district, and is covered on the first doping district. The extending district is positioned on the periphery of the shielding district, and is covered on the second doping district. A gate electrode layer is formed on the gate electrode insulation layer, and is covered on the central district, and the shielding district and the extending district are exposed. The shielding district of the gate electrode insulation layer is thicker than the extending district of the gate electrode insulation layer.

Description

Have the thin-film transistor and the manufacture method thereof of aiming at ldd structure voluntarily

Technical field

The invention relates to a kind of thin-film transistor technologies, be particularly to a kind of ldd structure and manufacture method thereof of polycrystalline SiTFT.

Background technology

(thin film transistor TFT) is intended for the switch module of picture element to the thin-film transistor of LCD (liquid crystal display is hereinafter to be referred as LCD), generally can be distinguished into two kinds of patterns of non-crystalline silicon tft and multi-crystal TFT.Because the carrier transport factor integrated level higher, drive circuit of multi-crystal TFT is preferable, leakage current is less, so multi-crystal TFT more often is applied in the circuit of high service speed, as: static RAM (static random accessmemory, SRAM).But the problem of leakage current (leakagecurrent) takes place down easily in multi-crystal TFT in off position, so can cause LCD loss electric charge or make the non-firm power consumption of SRAM.In order to address this problem, (lightly doped drain, LDD) structure are used for reducing the electric field of drain junction place (drain junction), can effectively improve the phenomenon of leakage current to adopt a lightly doped drain at present.

Shown in Figure 1A and 1B, it shows the generalized section of manufacture method of the LDD structure of known multi-crystal TFT.

Shown in Figure 1A, be manufactured with a polysilicon layer 12 on the presumptive area of a transparent insulation substrate 10, and a gate insulator 14 covers polysilicon layer 12.Multi-crystal TFT with making PMOS is an example, at first definition forms a photoresist layer 16 on gate insulator 14, utilize photoresist layer 16 to plant technology 17 to carry out a heavy doping ion cloth then, in the polysilicon layer 12 around the photoresist layer 16, to form a N as mask ⁺Doped region 18.

Shown in Figure 1B, after 16 removal of photoresist layer, carry out the deposition of metal material, little shadow and etch process, form a grid layer 20 with definition on gate insulator 14.Because the follow-up grid layer 20 that will utilize is as the pattern of mask with definition LDD structure, so grid layer 20 part doped region not that only covers polysilicon layer 12.Then, utilize grid layer 20 as mask to carry out a light dope implanting ions technology 21, make the not doped region of the polysilicon layer 12 around the grid layer 20 form a N ^-Doped region 22.Thus, N ^-Doped region 22 is to be used as a LDD structure, N ⁺ Doped region 18 is to be used as one source/drain region, and the not doped region of the polysilicon layer 12 that is covered by grid layer 20 then is to be used as a channel region.

Therefore yet said method need come the pattern of definition source/drain region by the figure of photoresist layer 16, and need define the pattern of LDD structure by the figure of grid layer 20, the accurate pattern of grid layer 20 position that just can guarantee the LDD structure.And, be subject to the alignment error (photo misalignment) of exposure technique, be not easy to control the side-play amount of grid layer 20, then twice implanting ions technology can make the problem of the offset of LDD structure can be more serious.Very and, the complex process of said method, production speed are low, the lateral length of also wayward LDD structure all can influence micro rate, electrical performance and the reliability of multi-crystal TFT.

Shown in Fig. 2 A to Fig. 2 C, it shows the generalized section of manufacture method of the LDD structure of known another kind of multi-crystal TFT.

At first, shown in Fig. 2 A, including in regular turn in the transparent insulation substrate 30 has a polysilicon layer 32, a gate insulator 34 and a grid layer 36.Then, provide one first photoresist layer 38 as mask, by the pattern of etching mode definition formation grid layer 36 with gate insulator 34, and the subregion of exposed polysilicon layer 32.

Be example then with the multi-crystal TFT of making PMOS, shown in Fig. 2 B, after the first photoresist layer 38 removed, the figure that utilizes grid layer 36 as mask to carry out a light dope implanting ions technology 39, with formation one N in the polysilicon layer 32 around the grid layer 36 ^- Doped region 40.

Follow-up, shown in Fig. 2 C, carry out the deposition of photo anti-corrosion agent material, little shadow and etch process to form one second photoresist layer 42, make its cover gate layer 36 with the surface and the sidewall of gate insulator 34, and the N of the part around the cover gate layer 36 ^-Doped region 40.At last, utilize the second photoresist layer 42 to plant technology 43 to carry out a heavy doping ion cloth, make second photoresist layer 42 N on every side as mask ^- Doped region 40 becomes a N ⁺Doped region 44.Thus, the N that is covered by the second photoresist layer 42 ^- Doped region 40 is to be used as a LDD structure, N ⁺ Doped region 44 is to be used as one source/drain region, and the not doped region of the polysilicon layer 32 that is covered by grid layer 36 then is to be used as a channel region.

Said method is the pattern that utilizes the graphical definition LDD structure of grid layer 36 earlier, utilizes the graphical definition source/drain region of the second photoresist layer 42 again, therefore can avoid the influence of the side-play amount of grid layer 36 to the LDD structure.But, the phenomenon of the offset of LDD structure still can take place in the implanting ions technology of the alignment error of exposure technique (photo misalignment) and twice, and can't improve complex process, problem that productive rate is low.

Summary of the invention

Main purpose of the present invention is to propose a kind of multi-crystal TFT of aiming at the LDD structure voluntarily that has, utilize the thickness difference that is positioned at LDD structure and source/drain region of gate insulator, and collocation primary ions cloth value technology, then can reach the making of LDD structure and source drain region simultaneously, to solve the problem of known technology.

For reaching above-mentioned purpose, the invention provides a kind of thin-film transistor of aiming at ldd structure voluntarily that has, comprising: a substrate; One effective layer, be to be formed on this substrate, include a channel region, one first doped region and one second doped region, wherein this first doped region is the outer peripheral areas that is positioned at this channel region, and this second doped region is the outer peripheral areas that is positioned at this first doped region; One gate insulator, be to be formed on this effective layer, comprise have a middle section at least, a shaded areas and an elongated area, wherein this middle section is to cover this channel region, this shaded areas is to be positioned at the peripheral of this middle section and to cover this first doped region, and this elongated area is to be positioned at the peripheral of this shaded areas and to cover this second doped region; And a grid layer, be to be formed on this gate insulator, wherein this grid layer is to cover this middle section and expose this shaded areas and this elongated area; Wherein, the thickness of the shaded areas of this gate insulator is greater than the thickness of the elongated area of this gate insulator.

For reaching above-mentioned purpose, the invention provides a kind of method of manufacturing thin film transistor of aiming at ldd structure voluntarily that has, comprise the following steps: to provide a substrate; Form an effective layer on this substrate; Form a gate insulator on this effective layer, wherein definition has a middle section, a shaded areas and an elongated area at least on this gate insulator, and this shaded areas is the outer peripheral areas that is positioned at this middle section, and this elongated area is the outer peripheral areas that is positioned at this shaded areas; Form a grid layer on this gate insulator; Carry out etch process, so that this grid layer covers the middle section of this gate insulator, and expose the shaded areas and the elongated area of this gate insulator, wherein the thickness of the shaded areas of this gate insulator is greater than the thickness of the elongated area of this gate insulator; And carry out implanting ions technology, in the effectively layer that is covered by this shaded areas, form one first doped region, and in the effective layer that is covered by this elongated area, form one second doped region.

Description of drawings

Figure 1A and Figure 1B are the generalized sections of manufacture method that shows the LDD structure of known a kind of multi-crystal TFT;

Fig. 2 A to Fig. 2 C is the generalized section of manufacture method that shows the LDD structure of known another kind of multi-crystal TFT;

Fig. 3 is the generalized section of aiming at the LDD structure voluntarily that shows the thin-film transistor of first embodiment of the invention;

Fig. 4 A is the generalized section of aiming at the LDD structure voluntarily that shows the thin-film transistor of second embodiment of the invention with Fig. 4 B;

Fig. 5 A to Fig. 5 F is the generalized section of the manufacture method of aiming at the LDD structure voluntarily that shows the thin-film transistor of third embodiment of the invention;

Fig. 6 A to Fig. 6 D is the generalized section of the manufacture method of aiming at the LDD structure voluntarily that shows the thin-film transistor of fourth embodiment of the invention.

Symbol description:

Transparent insulation substrate-10

Polysilicon layer-12

Gate insulator-14

Photoresist layer-16

Heavy doping ion cloth is planted technology-17

N ⁺Doped region-18

Grid layer-20

Light dope implanting ions technology-21

N ^-Doped region-22

Transparent insulation substrate-30

Polysilicon layer-32

Gate insulator-34

Grid layer-36

The first photoresist layer-38

Light dope implanting ions technology-39

N ^-Doped region-40

The second photoresist layer-42

Heavy doping ion cloth is planted technology-43

N ⁺Doped region-44

Substrate-50

Resilient coating-52

Effective layer-54

Source/drain region-54a

LDD structure-54b

Channel region-54c

Gate insulator-56

Middle section-56a

Shaded areas-56b

Elongated area-56c

First insulating barrier-55

Second insulating barrier-57

Grid layer-58

Patterning photoresist layer-60

Implanting ions technology-62

Intraconnections dielectric layer-64

Contact hole-65

Intraconnections-66

Embodiment

For above and other objects of the present invention, feature and advantage can be become apparent, preferred embodiment cited below particularly, and conjunction with figs. are described in detail below:

First embodiment:

As shown in Figure 3, it shows the generalized section of aiming at the LDD structure voluntarily of the thin-film transistor of first embodiment of the invention.Be manufactured with a resilient coating 52, one effective layer 54, one gate insulator 56 and a grid layer 58 on one substrate 50 in regular turn.Substrate 50 be preferably a transparent insulation substrate, for example: substrate of glass.Resilient coating 52 be preferably a dielectric materials layer, for example: silicon oxide layer, layer 54 is formed in the substrate 50 its purpose in order to help effectively.Effectively layer 54 be preferably the semiconductor silicon layer, for example: polysilicon layer.The stack layer that is preferably one silica layer, a silicon nitride layer, a silicon oxynitride layer or its combination of gate insulator 56.Grid layer 58 be preferably a conductive material layer, for example: metal level, polysilicon layer.

The architectural feature of the thin-film transistor of first embodiment of the invention below is described in detail in detail.Gate insulator 56 includes a middle section 56a, two shaded areas 56b and two elongated area 56c, middle section 56a is covered by the bottom of grid layer 58, shaded areas 56b be exposed to grid layer 58 the bottom both sides and be positioned at the periphery of middle section 56a, and elongated area 56c is the periphery that is positioned at shaded areas 56b.Effectively layer 54 includes a channel region 54c, two LDD structure 54b and two source/drain region 54a, channel region 54c is covered and corresponds to the position of middle section 56a by the bottom of grid layer 58, LDD structure 54b is the both sides that crested zone 56b covered and be positioned at channel region 54c, and source/drain region 54a is extended the both sides that regional 56c covered and be positioned at LDD structure 54b.

According to above-mentioned,, just can control the thickness D of elongated area 56c by adjusting grid layer 58 and the gold-tinted of gate insulator 56 and the conditional parameter of etch process ₁Thickness D with shaded areas 56b ₂Difference so that thickness D ₁And thickness D ₂Meet following relationship formula: D ₁＜D ₂, be more: the thickness D of elongated area 56c ₁Thickness D much smaller than shaded areas 56b ₂, also can make the thickness D of elongated area 56c ₁Near a minimum.Thus, then can utilize the mask of the bigger shaded areas 56b of thickness as the implanting ions technology of LDD structure 54b, and the cloth that implanting ions technology is adjusted in collocation plants energy and dosage, then just can finish the making of LDD structure 54b and source/drain region 54a simultaneously via implanting ions technology once.Be preferably, the transverse width of shaded areas 56b is 0.1-2.0 μ m, and it is 10-100keV that cloth is planted energy, and cloth is planted dosage less than 2 * 10 ¹⁸Atom/cm ³, the doping content of LDD structure 54b is 1 * 10 ¹²-1 * 10 ¹⁴Atom/cm ², the doping content of source/drain region 54a is 1 * 10 ¹⁴-1 * 10 ¹⁶Atom/cm ²

Therefore, the thin-film transistor of first embodiment of the invention has the following advantages:

The first, by adjusting the just thickness D of may command elongated area 56c of etching condition ₁Thickness D with shaded areas 56b ₂Difference, but and then the bigger shaded areas 56b of used thickness as the mask of the implanting ions technology of LDD structure 54b, therefore the position of LDD structure 54b of the present invention is accurate, can reach the electrical demand of thin-film transistor.

Second, do not need extra light shield to define the pattern of LDD structure 54b, can avoid the alignment error (photo misalignment) of exposure technique that LDD structure 54b is caused the problem of offset, thus the position of LDD structure 54b can accurately be controlled, and then guarantee the electrical performance of thin-film transistor.

The 3rd, a light shield capable of reducing using and minimizing are carried out primary ions cloth and are planted technology, thus have advantages such as the processing step of simplification, reduction technology cost, and then can improve product yield, increase speed of production, to meet mass-produced demand.

In addition, the thin-film transistor of first embodiment of the invention can be applicable to a P type thin-film transistor, and then LDD structure 54b is a N ^-Doped region, source/drain region 54a is a N ⁺Doped region.The thin-film transistor of first embodiment of the invention can be applicable to a N type thin-film transistor, and then LDD structure 54b is a P ^-Doped region, source/drain region 54a is a P ⁺Doped region.The present invention does not limit the profile of grid layer 58, the preferable square or up-narrow and down-wide trapezoidal that can be.

Second embodiment:

Shown in Fig. 4 A and Fig. 4 B, it shows the generalized section of aiming at the LDD structure voluntarily of the thin-film transistor of second embodiment of the invention.The assembly of the thin-film transistor of second embodiment is roughly described identical with first embodiment with architectural feature, and something in common no longer repeats book.Difference is, the gate insulator 56 of second embodiment is by one first insulating barrier 55 and one second insulating barrier 57 and constitute, wherein, first insulating barrier 55 be preferably one silica layer, a silicon nitride layer, a silicon oxynitride layer or its combination, second insulating barrier 57 be preferably one silica layer, a silicon nitride layer, a silicon oxynitride layer or its combination.

Definition has a middle section 56a, two shaded areas 56b and two elongated area 56c on the gate insulator 56.Be positioned at middle section 56a, the double-decker of first insulating barrier 55 and second insulating barrier 57 is to cover channel region 54c; Be positioned at shaded areas 56b, the double-decker of first insulating barrier 55 and second insulating barrier 57 is the both sides that cover LDD structure 54b and be exposed to grid layer 58; Be positioned at elongated area 56c, first insulating barrier 55 is covering source/drain region 54a.Therefore, in comparison, the thickness D of the gate insulator 56 in the 56c of elongated area ₁Less, and the thickness D of the gate insulator 56 in the shaded areas 56b ₂Bigger.

The difference in thickness that the storehouse effect that being characterized as of second embodiment of the invention adjusted first insulating barrier 55 and second insulating barrier 57 is made shaded areas 56b and elongated area 56c can be controlled the thickness D of the gate insulator 56 of elongated area 56c ₁Thickness D with the gate insulator 56 of shaded areas 56b ₂Meet following relationship formula: D ₁＜D ₂, be more: the thickness D of elongated area 56c ₁Thickness D much smaller than shaded areas 56b ₂, also can make the thickness D of elongated area 56c ₁Near a minimum.Thus, then can utilize the mask of the bigger shaded areas 56b of thickness as the implanting ions technology of LDD structure 54b, and the cloth that implanting ions technology is adjusted in collocation plants energy and dosage, then just can finish the making of LDD structure 54b and source/drain region 54a simultaneously via implanting ions technology once.Be preferably, the transverse width of shaded areas 56b is 0.1-2.0 μ m, and it is 10-100keV that cloth is planted energy, and cloth is planted dosage less than 2 * 10 ¹⁸Atom/cm ³, the doping content of LDD structure 54b is 1 * 10 ¹²-1 * 10 ¹⁴Atom/cm ², the doping content of source/drain region 54a is 1 * 10 ¹⁴-1 * 10 ¹⁶Atom/cm ²Therefore, the thin-film transistor of second embodiment of the invention still can be reached the described advantage of first embodiment, no longer repeats book in this.

In comparison, the making of the elongated area 56c shown in Fig. 4 A is that the etching with second insulating barrier 57 stops on first insulating barrier 55, and the making of the elongated area 56c shown in Fig. 4 B is over etching first insulating barrier 55.Therefore, the thickness of first insulating barrier 55 of the elongated area 56c of Fig. 4 A is bigger, and the thickness of first insulating barrier 55 of the elongated area 56c of Fig. 4 B is less, but can satisfy above-mentioned requirement equally: D ₁＜D ₂, and can reach identical advantage.In addition, gate insulator 56 can also adopt the insulating barrier storehouse effect more than three layers or three layers, with the effect of the difference in thickness of reaching shaded areas 56b and elongated area 56c.

The 3rd embodiment:

As Fig. 5 A to Fig. 5 F, the generalized section of the manufacture method of aiming at the LDD structure voluntarily of the thin-film transistor of its demonstration third embodiment of the invention.

Method of manufacturing thin film transistor of the present invention can be applicable to a P type thin-film transistor or a N type thin-film transistor.Below be that thin-film transistor with first embodiment is an example, describe the manufacture method of aiming at the LDD structure voluntarily in detail.

At first, shown in Fig. 5 A, provide a substrate 50, and on substrate 50, deposit a resilient coating 52, on resilient coating 54, make an effective layer 54 again.Substrate 50 be preferably a transparent insulation substrate, for example: substrate of glass.Resilient coating 52 be preferably a dielectric materials layer, for example: silicon oxide layer, layer 54 is formed in the substrate 50 its purpose in order to help effectively.Effectively layer 54 be preferably the semiconductor silicon layer, for example: polysilicon layer.The present invention does not limit the thickness and the manufacture method thereof of effective layer 54, for instance, effectively the making of layer 54 can be adopted low temperature polycrystalline silicon (low temperaturepolycrystalline silicon, LTPS) technology, prior to forming a noncrystalline silicon layer on the glass substrate, (excimer laser annealing, mode ELA) converts amorphous silicon layer to the polysilicon material to utilize the annealing of heat treatment or excimer laser then.

Then, shown in Fig. 5 B, deposition one gate insulator 56 and a grid layer 58 on effective layer 54 form a patterning photoresist layer 60 again on grid layer 58 in regular turn.The stack layer that is preferably one silica layer, a silicon nitride layer, a silicon oxynitride layer or its combination of gate insulator 56.Grid layer 58 be preferably a conductive material layer, for example: metal level, polysilicon layer.The size of patterning photoresist layer 60 and position are the patterns that corresponds to follow-up formation grid layer 58.

Follow-up, shown in Fig. 5 C, utilize patterning photoresist layer 60 as mask carrying out an etch process, grid layers 58 beyond patterning photoresist layer 60 zone and part of grid pole insulating barriers 56 are removed, with the pattern of definition grid layer 58.Be preferably, use electric paste etching (plasmaetching) or reactive ion etching method, and this step can suitably be adjusted the etching degree of gate insulator 56, can keep grid layer 58 patterns part of grid pole insulating barrier 56 in addition, on the predetermined origin/drain region of effective layer 54, to form an elongated area 56c and the thickness D of elongated area 56c ₁With with the thickness D of the gate insulator 56 of grid layer 58 belows ₂Must meet following relationship formula: D ₁＜D ₂

Then, shown in Fig. 5 D, with the profile of grid layer 58 make become one up-narrow and down-wide trapezoidal, the bottom that can make grid layer 58 is the middle section 56a of cover gate insulating barrier 56 only, then make the shaded areas 56b of gate insulator 56 be exposed to the two bottom sides of grid layer 58, and the elongated area 56c of gate insulator 56 is covered on the predetermined origin/drain region of effective layer 54.And this step can suitably be adjusted the etching degree of gate insulator 56, so that the thickness D of elongated area 56c ₁With with the thickness D of the gate insulator 56 of grid layer 58 belows ₂Meet following relationship formula: D ₁＜D ₂

For instance, the reacting gas of etch process use one has the mist of oxygen-containing gas and chlorine-containing gas, can adjust the flow of individual gases according to needs in good time.In the etching process of grid layer 58, the flow of oxygen-containing gas can be adjusted to gradually greatly, or even only use oxygen-containing gas as etching reaction gas, the profile of grid layer 58 can be made become one up-narrow and down-wide trapezoidal.In the etching process of gate insulator 56, the flow of oxygen-containing gas can be adjusted to minimumly, or even only use oxygen-containing gas as etching reaction gas.In addition, this step more can replace the etching step shown in Fig. 5 C, to reduce process time and technology cost.

Thereafter, shown in Fig. 5 E, after patterning photoresist layer 60 removed, utilize grid layer 58 and shaded areas 56b as mask to carry out an implanting ions technology 62.Thus, effective layer 54 that crested zone 56b covers is to become a lightly doped region, in order to be used as a LDD structure 54b; Be not to become a heavily doped region, in order to be used as a source drain region 54a by effective layer 54 of grid layer 58 and shaded areas 56b covering; As for the effective layer 54 that is covered by grid layer 58 and middle section 56a is to become a doped region not, in order to be used as a channel region 54c.

The operating condition of implanting ions technology 62 is preferably, and it is 10-100keV that cloth is planted energy, and cloth is planted dosage less than 2 * 10 ¹⁸Atom/cm ³, the doping content of LDD structure 54b is 1 * 10 ¹²-1 * 10 ¹⁴Atom/cm ², the doping content of source/drain region 54a is 1 * 10 ¹⁴-1 * 10 ¹⁶Atom/cm ²Be more preferred from, cloth is planted dosage less than 1 * 10 ¹³Atom/cm ³The inventive method can be applicable to a P type thin-film transistor, and then LDD structure 54b is a N ^-Doped region, source/drain region 54a is a N ⁺Doped region.The inventive method also can be applicable to a N type thin-film transistor, and then LDD structure 54b is a P ^-Doped region, source/drain region 54a is a P ⁺Doped region.

At last, shown in Fig. 5 F, carry out interconnecting process, include the making of an intraconnections dielectric layer 64, a plurality of contacts hole 65 and a plurality of intraconnections 66, the execution mode of this step can materially affect feature of the present invention and effect, so book in detail.

Therefore, the method for manufacturing thin film transistor of third embodiment of the invention has the following advantages:

The first, by adjusting the just thickness D of may command elongated area 56c of etching condition ₁Thickness D with shaded areas 56b ₂Difference, but and then the bigger shaded areas 56b of used thickness as the mask of the implanting ions technology of LDD structure 54b, therefore the position of LDD structure 54b of the present invention is accurate, can reach the electrical demand of thin-film transistor.

Second, do not need extra light shield to define the pattern of LDD structure 54b, so can avoid the alignment error (photo misalignment) of exposure technique that the LDD structure is caused the problem of offset, thus the position of LDD structure 54b can accurately be controlled, and then guarantee the electrical performance of thin-film transistor.

The 3rd, minimizing is used a light shield and is only carried out primary ions cloth and plant technology, thus have advantages such as the processing step of simplification, reduction technology cost, and then can improve product yield, increase speed of production, to meet mass-produced demand.

The 4th, the inventive method can be simultaneously carried out in various degree doping to adjust its component characteristic, to simplify technology, improve the product yield, to increase speed of production to nmos area territory and PMOS zone.

The 4th embodiment:

Shown in Fig. 6 A to Fig. 6 D, the generalized section of the manufacture method of aiming at the LDD structure voluntarily of the thin-film transistor of its demonstration fourth embodiment of the invention.

Method of manufacturing thin film transistor of the present invention can be applicable to a P type thin-film transistor or a N type thin-film transistor.Below be that structure with the thin-film transistor of second embodiment is an example, describe the manufacture method of aiming at the LDD structure voluntarily in detail.The implementation step of the 4th embodiment is roughly described identical with the 3rd embodiment, and the material of same components and characteristic no longer repeat book in this.

At first, as shown in Figure 6A, provide a substrate 50, and on substrate 50, form a resilient coating 52, one effective layer 54,1 first insulating barrier 55, one second insulating barrier 57, a grid layer 58 and a patterning photoresist layer 60 in regular turn.Substrate 50 be preferably a substrate of glass, resilient coating 52 be preferably one silica layer, effectively layer 54 is preferably a polysilicon layer.First insulating barrier 55 be preferably one silica layer, a silicon nitride layer or a silicon oxynitride layer, second insulating barrier 57 be preferably one silica layer, a silicon nitride layer or a silicon oxynitride layer.Grid layer 58 be preferably a conductive material layer, a metal level, a polysilicon layer.The size of patterning photoresist layer 60 and position are the patterns that corresponds to follow-up formation grid layer 58.

Being characterized as of fourth embodiment of the invention, the combination of first insulating barrier 55 and second insulating barrier 57 are as a gate insulator 56, and definition has a middle section 56a, two shaded areas 56b and two elongated area 56c on gate insulator 56.

Then, shown in Fig. 6 B, utilize patterning photoresist layer 60 as mask carrying out an etch process, grid layers 58 beyond patterning photoresist layer 60 zone and part of grid pole insulating barriers 56 are removed, with the pattern of definition grid layer 58.Be preferably, use electric paste etching (plasmaetching) or reactive ion etching method, and this step can suitably be adjusted the etching degree of first insulating barrier 55, second insulating barrier 57, to remove second insulating barrier 57 of elongated area 56c, and first insulating barrier 55 of reservation elongated area 56c, first insulating barrier 55 is covered on the predetermined origin/drain region of effective layer 54.Thus, the thickness in monolayer of first insulating barrier 55 in the 56c of elongated area can be less than first insulating barrier 55 in the shaded areas 56b and the bilayer thickness of second insulating barrier 57.

Then, shown in Fig. 6 C, with the profile of grid layer 58 make become one up-narrow and down-wide trapezoidal, can make the bottom of grid layer 58 only cover middle section 56a, then make first insulating barrier 55 in the shaded areas 56 be exposed to the two bottom sides of grid layer 58, and first insulating barrier 55 in the 56c of elongated area is covered effectively on predetermined origin/drain region of layers 54 with the double-decker of second insulating barrier 57.And this step also can be selected the etching degree of first insulating barrier 55 according to the demand of product, so that the thickness D of first insulating barrier 55 of elongated area 56c ₁And first insulating barrier 55 in the shaded areas 56b and the bilayer thickness D of second insulating barrier 57 ₂Meet following relationship formula: D ₁＜D ₂In addition, this step more can replace the etching step shown in Fig. 5 C, to reduce process time and technology cost.

Thereafter, shown in Fig. 6 D, after 60 removal of patterning photoresist layer, the double-decker that utilizes the first interior insulating barrier 55 of grid layer 58 and shaded areas 56b and second insulating barrier 57 is as mask, to carry out an implanting ions technology 62.Thus, the effective layer 54 in the shaded areas 56b is to become a lightly doped region, in order to be used as a LDD structure 54b; Effective layer 54 in the 56c of elongated area is to become a heavily doped region, in order to be used as a source drain region 54a; As for the effective layer in the middle section 56a 54 is to become a doped region not, in order to be used as a channel region 54c.The operating condition of implanting ions technology 62 is preferably, and it is 10-100keV that cloth is planted energy, and cloth is planted dosage less than 2 * 10 ¹⁸Atom/cm ³, the doping content of LDD structure 54b is 1 * 10 ¹²-1 * 10 ¹⁴Atom/cm ², the doping content of source/drain region 54a is 1 * 10 ¹⁴-1 * 10 ¹⁶Atom/cm ²Be more preferred from, cloth is planted dosage less than 1 * 10 ¹³Atom/cm ³

At last, carry out interconnecting process, the execution mode of this step can materially affect feature of the present invention and effect, so book in detail.The manufacture method of fourth embodiment of the invention also has and is same as the described advantage of the 3rd embodiment, no longer repeats book in this.In addition, gate insulator 56 can also adopt the insulating barrier storehouse effect more than three layers or three layers, with the effect of the difference in thickness of reaching shaded areas 56b and elongated area 56c.

Claims (9)

1. one kind has the thin-film transistor of aiming at ldd structure voluntarily, it is characterized in that: described thin-film transistor comprises:

One substrate;

One effective layer, be to be formed on this substrate, include a channel region, one first doped region and one second doped region, wherein this first doped region is the outer peripheral areas that is positioned at this channel region, and this second doped region is the outer peripheral areas that is positioned at this first doped region;

One gate insulator, be to be formed at this effectively on the layer and have a up-narrow and down-wide trapezoidal shape, comprise have a middle section at least, a shaded areas and an elongated area, wherein this middle section is to cover this channel region, this shaded areas is to be positioned at the peripheral of this middle section and to cover this first doped region, and this elongated area is to be positioned at the peripheral of this shaded areas and to cover this second doped region; And

One grid layer is to be formed on this gate insulator, and wherein this grid layer is to cover this middle section and expose this shaded areas and this elongated area;

Wherein, the thickness of the shaded areas of this gate insulator is greater than the thickness of the elongated area of this gate insulator.

2. according to claim 1 have a thin-film transistor of aiming at ldd structure voluntarily, and it is characterized in that: this gate insulator includes one first insulating barrier and one second insulating barrier, wherein:

The shaded areas of this gate insulator is to be formed by this first insulating barrier and this second insulating barrier institute storehouse; And

The elongated area of this gate insulator is made of this first insulating barrier.

3. according to claim 1 have a thin-film transistor of aiming at ldd structure voluntarily, and it is characterized in that: the doping content of this first doped region is less than the doping content of this second doped region.

4. according to claim 1 have a thin-film transistor of aiming at ldd structure voluntarily, and it is characterized in that: the transverse width of the shaded areas of this gate insulator is 0.1-2.0 μ m.

5. according to claim 1 have a thin-film transistor of aiming at ldd structure voluntarily, it is characterized in that:

This substrate is a transparent insulation substrate or a substrate of glass;

Effectively layer is a semiconductor silicon layer or a polysilicon layer; And

This gate insulator is one silica layer, a silicon nitride layer, a silicon oxynitride layer.

6. one kind has the method for manufacturing thin film transistor of aiming at ldd structure voluntarily, comprises the following steps:

One substrate is provided;

Form an effective layer on this substrate;

Form a gate insulator on this effective layer;

Form a grid layer on this gate insulator;

Carry out an etch process, so that definition has a middle section, a shaded areas and an elongated area at least on this gate insulator, and this shaded areas is positioned at the outer peripheral areas of this middle section, and this elongated area is positioned at the outer peripheral areas of this shaded areas, and make this grid layer cover the middle section of this gate insulator and have a up-narrow and down-wide trapezoidal shape, and expose the shaded areas and the elongated area of this gate insulator, wherein the thickness of the shaded areas of this gate insulator is greater than the thickness of the elongated area of this gate insulator; And

Carry out implanting ions technology, in the effectively layer that is covered by this shaded areas, form one first doped region, and in the effective layer that is covered by this elongated area, form one second doped region.

7. according to claim 6 have a method of manufacturing thin film transistor of aiming at ldd structure voluntarily, and wherein the manufacture method of the shaded areas of this gate insulator and elongated area comprises the following steps:

Form one first insulating barrier on this effective layer;

Form one second insulating barrier on this first insulating barrier; And

Carry out etch process, removing this second insulating barrier of this elongated area, and keep this first insulating barrier of this elongated area;

Wherein, this shaded areas is made of this first insulating barrier and this second insulating barrier, and this elongated area is made of this first insulating barrier.

8. according to claim 6 have a method of manufacturing thin film transistor of aiming at ldd structure voluntarily, and wherein the doping content of this first doped region is 1 * 10 ¹²-1 * 10 ¹⁴Atom/cm ², the doping content of this second doped region is 1 * 10 ¹⁴-1 * 10 ¹⁶Atom/cm ²

9. according to claim 6 have a method of manufacturing thin film transistor of aiming at ldd structure voluntarily, wherein:

This substrate is a transparent insulation substrate or a substrate of glass;

Effectively layer is a semiconductor silicon layer or a polysilicon layer; And

This gate insulator is one silica layer, a silicon nitride layer, a silicon oxynitride layer.

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