CN1315027A - 具有印刷天线的射频识别标签和方法 - Google Patents

具有印刷天线的射频识别标签和方法 Download PDF

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CN1315027A
CN1315027A CN99807676A CN99807676A CN1315027A CN 1315027 A CN1315027 A CN 1315027A CN 99807676 A CN99807676 A CN 99807676A CN 99807676 A CN99807676 A CN 99807676A CN 1315027 A CN1315027 A CN 1315027A
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antenna
antenna element
coupled zone
substrate
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诺埃尔·H·埃伯哈特
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Motorola Solutions Inc
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Abstract

一种射频识别标签(14)包括一射频识别标签电路芯片(12),射频识别标签电路芯片耦合到包括印刷在基片(16)上的导电图形(22)的天线(10)。该基片可以形成物品、包装、包装容器、信封、证件、运货单、标签和/或认证证章之一的一部分。该导电图形包括第一耦合区(28)和第二耦合区(30),被设计成耦合到射频识别标签电路芯片上。第一耦合区和第二耦合区通过形成在该基片上的缝隙(31)精确定位并且相互隔离。

Description

具有印刷天线的射频识别标签和方法
本申请是Noel H.Eberhardt等人于1998年6月9日提交的申请序号为＿的“具有物品集成天线的射频识别标签”，代理记录号IND10149的共同转让的美国专利申请的后续部分申请，该在先申请在此引用作为参考，如同在此将这些公开内容一字不差地进行阐述所具有的相同效果。
本申请与下列共同转让的在先美国专利申请有关。Ted Geiszler等人于1995年10月11日提交的申请序号为08/540813的“远端供电电子标签和相关激励器/读取器和有关方法”，代理记录号IND00701；Victor Allen Vega等人于1998年2月27日提交的申请序号为09/031848的“利用为耦合接地设计的标签的射频识别标签系统”，代理记录号IND10153；Victor Allen Vega等人于1998年3月12日提交的申请序号为09/041480的“为磁存储标签状态信息设计的射频识别标签”，代理记录号IND10146；以及Victor Allen Vega等人于1998年3月20日提交的申请序号为09/045357的“具有可编程电路状态的射频识别标签”，代理记录号IND10174；这些在先申请在此引用作为参考，如同在此将这些公开内容一字不差地进行阐述所具有的相同效果。
本发明总的涉及射频识别标签领域，包括但不限于具有印刷天线的射频识别标签。
射频识别标签和射频识别标签系统是公知的，并且有许多应用。例如，射频识别标签经常用于自动门卫应用中的人员认证，以保护固定的建筑或地区的安全。在射频识别标签中存储的信息识别寻求进入被固定建筑的人。射频识别标签系统方便地提供在短距离内利用射频(RF)数据传输技术从射频识别标签中读取信息。通常，用户简单地手持或将射频识别标签放在接近基站处，该基站向包含在射频识别标签中的射频识别标签的供电电路发射激励信号。该电路响应于激励信号，将存储的信息从射频识别标签传送给基站，由基站接收和解码该信息。通常，射频识别标签能够保持和在工作中发射丰富的信息——足够用于唯一识别个人，包装，库存等的信息。
供电和读取射频识别标签的典型技术是电感耦合或电感电源耦合和电容数据耦合的组合。电感耦合利用射频识别标签中的线圈元件。该线圈元件被来自基站的激励信号所激励，为射频识别标签电路提供电源。射频识别标签线圈，或第二线圈，可以用于在射频识别标签和基站之间发射和接收所存储的信息。依赖电感耦合的射频识别标签对射频识别标签相对基站的方向敏感，因为由激励信号产生的电场必须与线圈元件以基本上直角相交才能有限耦合。电感耦合装置的读取范围一般在几个厘米数量级。对于某些应用，例如电子宠物识别、行李跟踪、包裹跟踪和库存管理应用需要更长的读取距离。
对射频识别标签供电和读取的另一个技术是静电耦合，例如在上述参考应用中所公开的射频识别标签系统和射频识别标签中所采用的。这些系统有利地提供了对于现有技术的那些应用明显增加的读/写距离。从所公开的系统和标签的使用获得的另一个优点是用户不需要将射频识别标签靠近基站或对着基站方向。因此，有可能将基站的天线合并到例如门口或门厅、包裹传送机或物品分类系统中，以在更大距离上对标签供电和读取标签信息。
为在基站和射频识别标签之间耦合电感或静电信号，标签必须包括一个具有至少一个，通常为两个的天线单元的天线。通常，标签电路芯片和天线电连接并粘合到标签基片上。由标签基片尺寸所决定的标签尺寸一般保持非常小。因此，天线通常受尺寸限制。可是，更小的天线不利地影响了读取范围。天线也必须与标签基片形成在同平面上，这潜在地使标签对方向敏感。因为不希望，通常也不现实，将射频识别标签制造得更大，有效的天线尺寸仍然受限制。通常平面的标签设计也限制了天线是平面的、方向敏感的构形。
按照标题为“具有物品集成天线的射频识别标签”的上述美国专利申请所公开发明的优选实施例，建议把天线集成到物品上。例如，优选实施例利用把导电墨水印刷在卡片或纸包装上的天线。然后将射频识别标签电路芯片固定在物品上并且与该天线电连接。另外，建议提供射频识别标签芯片组件。该芯片组件提供将射频识别标签电路芯片粘合在包括导电图形的基片上。如同所公开的，通过利用导电墨水将图形印刷在纸基片上来形成优选导电图形。然后可将该芯片组件固定在物品上并且通过导电图形与该天线电连接。
如同所理解的，电路芯片与印刷在物品上天线或与印刷在基片上导电图形的对准对于该电路芯片正常工作是非常重要的。更具体地，电路芯片必须定位在大约+/-0.125毫米(mm)内，以将电路芯片上的导电焊盘与该天线和/或导电图形正确配合。可是，在纸或纸类材料上印刷天线和/或导电图形的的一般技术只获得在+/-1.5mm数量级的边缘公差。此边缘公差的大小大于一般的电路芯片。产生不严密边缘公差的几个因素包括印刷图形边缘渗漏和印刷图形相对基片位置改变。
因此，需要一种改善的射频识别标签。
在附图中将说明本发明优选示范性实施例，图中相同的参考标号代表相同的部件。
图1是按照本发明优选实施例的射频识别标签的分解装配图。
图2是图1沿线2-2的截面图。
图3是天线和/或导电图形印刷在基片上的平面图。
图4是图3中在圆圈A中天线部分的放大平面图。
图5是图4中按照本发明优选实施例形成的天线和/或导电图形平面图。
图6是图5中沿线6-6的截面图，进一步说明按照本发明的一个优选实施例制作天线的装置。
图7是类似图6的截面图，说明按照本发明的另一个优选实施例。
图8是类似图6的截面图，说明按照本发明的另一个优选实施例。
图9是类似图2的截面图，说明按照本发明的另一个优选实施例。
图10是类似图6的截面图，说明按照本发明的另一个优选实施例。
图11是类似图2的截面图，说明按照本发明的另一个优选实施例。
按照本发明优选实施例的射频识别标签利用了形成在基片上的印刷天线。该基片可以形成物品、一个包装、一个包装容器，一个证件，一个货运单、一个标签和/或一个认证证章的一部分。在本发明的优选实施例中，通过印刷沉积墨水，在基片上形成导电图形，在印刷图形中形成耦合区，然后在导电图形中相对基片精确地形成耦合区。
参照图1，在分解装配图中所示的射频识别标签14包括一个射频识别标签电路芯片(“电路芯片”)12，固定在天线10上。天线10可以形成个人认证证章、证件、货运单、标签、包装容器(例如盒子或信封)一部分的基础，或形成它们的一部分。如同可以理解的，天线10也可以形成射频识别标签电路芯片组件的基础(即基片和导电图形)，如同在题目为“具有物品集成天线的射频识别标签”的上述美国专利申请中所描述的，而并不脱离本发明的范围。如同所见，天线10包括安置在基片16上的一个导电图形22。
继续参照图1，基片16可以是纸、塑料(包括聚酯和金属化的聚酯材料)、合成纸、强化纸，卡片、合成纸涂层卡片和为特定应用所选择的物品。基片16包括第一表面18和第二表面20。形成在第一表面18上的导电图形22包括第一天线单元24和第二天线单元26。第一天线单元24和第二天线单元26的每个由粘合或形成在基片16上的导电材料形成。最好，第一天线单元24和第二天线单元26的每个利用适合的可印刷的导电介质通过印刷形成。例如，当印刷在纸和/或卡片上时，碳/石墨基墨水形成有效导电图形22。另外可使用合成和涂层纸，但增加成本。特别为在塑料上进行印刷，可以使用银和其它贵金属墨水，但由于材料成本较高而较少选择。所示的导电图形22具有H形状，适合于用在静电应用中。应当理解，可以印刷更适合于例如电感耦合的其它图形而不脱离本发明范围。用第一耦合区28形成第一天线单元24和用第二耦合区30形成第二天线单元26。第一耦合区28和第二耦合区30向着形成在基片16上通常在H形状中心的缝隙31延伸并由该缝隙隔离。
参照图1和图2，由为耦合到导电图形22而设计的导电焊盘38和导电焊盘40形成电路芯片12。如图所示，导电焊盘38和导电焊盘40是“凸起”焊盘。即，它们从电路芯片12的底表面32向外突出。这与“表面”焊盘相反，表面焊盘基本上形成在与电路芯片底表面32的共平面上。当固定在天线10上时，导电焊盘38电连接到第一耦合区28而导电焊盘40电连接到第二耦合区30。如图2所示，导电黏合剂层34和导电黏合剂层36分别安置在导电焊盘38与第一耦合区28之间和导电焊盘40与第二耦合区30之间，提供电连接并将电路芯片12粘合到天线10上。在本发明的优选实施例中，各向同性黏合剂被使用并且精确施加在电路芯片12和天线10之一或两者上。另一个方式，各向异性黏合剂也可以使用但成本高。也应当注意，并没有使用凸起焊盘的特别爱好，也可以使用凸起焊盘、表面焊盘或凹槽焊盘(即，所形成的导电焊盘凹进在电路芯片12的外表面内)，其根据成本和特定应用而选择。在读/写实施例中，电路芯片12可以由TEMICe5550电路芯片(可以从TEMIC NORTH AMERICA公司，BaskingRidge,New Jerswy获得)方便地构成。在只读实施例中可以使用Indala1341电路芯片(可以从MOTOROLA INDALA公司，San Jose,California获得)。
优选的各向异性黏合剂是可以从3M公司获得的3M9703黏合剂。优选黏合剂是各向异性的，其中它只在Z或垂直方向导电(图2)。该黏合剂制造得在黏合剂基底中包含镀金属的微小颗粒，使黏合剂层从上表面到下表面形成电接触。而在X或Y方向，即黏合剂层的平面上没有形成电接触。因此，黏合剂可以施加在整个层而不短路相邻导线。优选的各向同性黏合剂是#8103可以从ADHESIVES RESEARCH公司获得。
为有助于理解本发明，参照图3，示出天线10′处在中间处理阶段。天线10′代表天线10的中间制造阶段。为清楚，最初的参考标号用于识别在中间阶段没有完全形成的元件。参照图3，天线10′通过首先在基片16′上最好是印刷形成导电图形22′。如同可以看到的，缝隙31还没有形成，而第一耦合区28′和第二耦合区30′在导电图形22′的中心仍是相连的。
图3也说明了与在基片16′上形成导电图形22′有关的制造公差。这些公差和它们对完成的天线10的影响的讨论将提供对本发明优点更多的理解。参照图3，即使利用非常精确的印刷工艺，导电图形22′将分别在相对基片16′的边缘42和边缘44的方向X和Y上变形。通常变形分别表示为+/-X和+/-Y，在每个方向为大约0.5mm数量级。另外，参照图4，导电图形22′的周边45不是明显的线，由不均匀干燥的结果，致使周边46具有粗糙的轮廓，而代之以导电墨水的“渗漏”。周边46的变形在图4中表示为+/-，可以大到+/-0.125mm。由图形位置变化和渗漏两者产生的总变形可以高达+/-1.5mm范围。此数字的重要性是因为电路芯片12只是1mm见方。因此，导电图形的变形可能大于电路芯片12。结果，仅参照边缘42和边缘44将电路芯片12定位到导电图形22上是不可能的。因此自动附着电路芯片12需要复杂、昂贵的图象技术，以将导电图形22精确地放置在基片16上。对昂贵图象自动处理的另一个选择是人工附着。人工附着耗费时间并且不能提供自动处理的工艺重复性。在任何一个情况下，成本、质量和加工效率受很大影响。
参照图5，完成阶段的天线10包括形成在基片16上的缝隙31，将第一耦合区28和第二耦合区30隔离。按照本发明的优选实施例，缝隙31通过在相对基片基准的导电图形22的中心冲压掉基片16一部分形成。
参照图5和图6，天线10′定位在夹具100中。夹具100包括角定位块102和边缘定位块104，延伸在基座106上。另一个方式的定位设计可以使用形成在基片16上的针啮合孔/缝定位器。角定位块102安排成与边缘42和边缘44两者啮合，利用边缘42和边缘44提供基片基准。边缘定位块104安排成与边缘44啮合。以此方式，相对边缘42和边缘44建立了形成缝隙31的一致的、可重复的基准。图6所示，一个冲头108还被相对夹具100固定。在工作中，天线10′相对基板106上的角定位块102和边缘定位块104定位。当冲头108穿过导电图形22′和基片16′并且进入扣眼缝隙120时，冲头108啮合导电图形22′和基片16′从中剪切下塞子112。这样缝隙31精确地将第一耦合区28和第二耦合区30隔离。另外，第一耦合区28和第二耦合区30相对边缘42和边缘44精确定位，有可能简化电路芯片12的自动附着。可以预计，第一耦合区28的边缘46和第二耦合区的边缘48，可以分别形成距边缘42和边缘44在+/-0.025mm的范围内。
在完成按照本发明优选实施例的射频识别标签14时，电路芯片的元件拾取-放置自动操作(未图示)可以对基准边缘42和边缘44进行安排。根据该基准，电路芯片12可以相对第一耦合区28和第二耦合区30精确定位。应当进一步理解，可以构成单一的制造/组装元件。这种组装元件提供自动安置基片16′，利用适合的打印头印刷导电图形22′，形成缝隙31，并定位电路芯片12。可是，按照本发明的优选实施例，这些操作的每个可以按单独制造/组装元件的安排来完成，例如以生产线的形式来完成。在整个过程中，保持相对基片16精确形成第一耦合区28和第二耦合区30并且相对这些区域精确安置电路芯片12。这样，本发明有利地提供了制造的明显灵活性。
参照图7，表示本发明另一个方式的优选实施例。天线10′再次代表天线10的中间制造阶段。为清楚，最初的参考标号用于表示在中间阶段没有完全形成的元件(如图3所示)。如图7所见，冲头208安排得切断导电图形22′和表面18并且挤压基片16′一部分而不形成基片16′中的通孔。夹具100按上述构成，并且包括角定位块102和边缘定位块104。省略了扣眼缝隙120。冲头208在第一耦合区28′和第二耦合区30′分界线上啮合导电图形22′和表面18′，在啮合点处切断导电图形22′和表面18。冲头208进一步挤压基片16′的一部分，以致产生隔离第一耦合区28和第二耦合区30的缺口231。再次获得第一耦合区28和第二耦合区30相对边缘42和边缘44非常精确的定位，由此允许自动安置电路芯片12。在图8中，冲头308被设计成具有刀刃边缘330，以更好地刺入导电图形22′和表面18，而形成基片16上的缺口331。
然后参照图9，在完成按照本发明优选实施例的射频识别标签114时，电路芯片元件拾取-放置自动操作(未示出)可以对基片16的基准边缘42和边缘44进行安排(图9所示边缘42)。根据该基准，电路芯片12可以利用通过黏合剂34将导电焊盘38电连接到第一耦合区28和通过黏合剂36将导电焊盘40电连接到第二耦合区30而精确定位。第一耦合区28和第二耦合区30通过穿过导电图形22和表面18进入基片16的缺口231精确定位并且电绝缘。
图10表示本发明另一个优选实施例，用于从天线10′形成天线110。天线10′仍代表天线110的中间制造阶段，和为清楚，最初的参考标号用于表示在中间阶段没有完全形成的元件(如图3所示)。夹具400包括角定位块402和边缘定位块(未示出)延伸到基底406上。另一个方式的定位设计可以使用形成在基片16′上的针啮合孔/缝定位器。角定位块402被安排成啮合基片116的两个边缘(在图10所示边缘142)，边缘定位块按所描述的被设计成啮合基片116的一个边缘。成型/冲头408还被相对夹具400固定。冲头408包括一个冲头部分410，被设计成当它穿过导电图形22′和基片16′并且进入扣眼缝隙420时，啮合导电图形22′和基片16′从中剪切下塞子412。以此方式，在基片16′上形成缝隙431将耦合区128和耦合区130隔离。另外，第一耦合区128和第二耦合区130相对基片116精确定位，有可能简化电路芯片112的自动附着。
冲头408进一步被设计成具有肩部或成型部分424。当冲头408啮合基片16′时，基片16′的局部区域418被压缩并且形成基本上对应肩部424的形状。以此方式，在基片116上缝隙431附近形成凹槽416，第一耦合区128和第二耦合区130延伸到凹槽内。
参照图11，使用天线110组装射频识别标签414。按照本发明的优选实施例，电路芯片元件拾取-放置自动操作(未示出)可以被安排成参照基片116的边缘(图11中所示的边缘142)。根据该基准，电路芯片112可以利用通过黏合剂134将导电焊盘138电连接到第一耦合区128、通过黏合剂136将导电焊盘140电连接到第二耦合区130而精确定位。第一耦合区128和第二耦合区130精确地定位并且通过延伸穿过导电图形122和基片116的缝隙431相互隔离开。以此方式，电路芯片112耦合到安置在基片116表面118上的第一天线单元124和第二天线单元126的每个上。另外，电路芯片112保持在表面118之下，由此减少的使用射频识别标签414期间从基片116移动的可能性。也应当理解，填充材料和/或盖子可以安置在电路芯片112上方，由此提供进一步保护。
总之，再次参照图1，射频识别标签14包括一个射频识别标签电路芯片12，固定在天线10上。该天线包括形成在基片16的表面18上的第一天线单元24和第二天线单元26。第一天线单元和第二天线单元被形成在基片内的缝隙31隔离和精确定位。
参照图7和图8，天线10的另一种方式的优选实施例包括形成在基片16的表面18上的第一天线单元24和第二天线单元26。第一天线单元和第二天线单元由形成穿过该表面和部分延伸到基片内分别表示在图7和图8的缺口231和331隔离和定位。
参照图9，射频识别标签214包括一个射频识别标签电路芯片12，固定在天线10上。该天线包括形成在基片16的表面18上的第一天线单元24和第二天线单元26，而第一天线单元和第二天线单元由形成在基片内的缺口31隔离并精确定位。
在本发明的又一个优选实施例中，参照图10，天线110包括形成在基片116的表面118上的第一天线单元124和第二天线单元126。该基片被形成为包括形成在该基片上的凹槽416。第一天线单元包括第一耦合区128而第二天线单元包括第二耦合区130。第一耦合区和第二耦合区延伸到凹槽内并且由形成在凹槽内的缝隙431隔离和精确定位。
参照图11，射频识别标签414包括射频识别标签电路芯片112，固定在天线110上。该天线包括形成在基片116的表面118上的第一天线单元124和第二天线单元126。天线110还包括形成在基片116内的凹槽416，并且第一耦合区128和第二耦合区130延伸到凹槽内并且由形成在凹槽内的缝隙431隔离和精确定位。射频识别标签电路芯片固定在凹槽内并且耦合到第一耦合区和第二耦合区。第一耦合区和第二耦合区由此将射频识别标签电路芯片耦合到第一天线单元和第二天线单元。
按照制造分配认证标签的优选方法，提供一具有表面的基片。在该表面上印刷导电图形，和在该基片上相对基片基准形成缝隙，该缝隙将导电图形隔离成为第一天线单元和第二天线单元。然后射频识别标签电路芯片被固定在基片上并且与第一天线单元和第二天线单元电连接。该方法可以另一种方式提供在基片上形成缺口和/或凹槽。
现在讨论本发明的某些优点。
控制印刷天线尺寸和定位公差能力方面的极限已经限制了在射频识别标签方面的该项成本有益和强化性能的技术。本发明通过克服这些公差极限有助于利用印刷天线技术。
在减少射频识别标签成本的同时，通过利用容易匹配射频识别标签电路芯片的印刷天线改进了性能。
通过本发明改善了制造效率，其中射频识别标签电路芯片被迅速和精确地固定并且耦合到射频识别标签天线上。
本发明也允许用单一元件和多个元件制作方案，利用普通可用的元件拾取-放置自动操作经济地制造射频识别标签。
可以进行许多另外改变和修改而不脱离本发明范围和精神。上面讨论的某些改变的范围。其它修改的范围根据附带的权利要求书是显而易见的。

Claims (12)

1．一种射频识别标签，包括：
一射频识别标签电路芯片，固定到天线上，该天线包括形成在基片表面上的第一天线单元和第二天线单元，第一天线单元和第二天线单元通过形成在基片上的缝隙隔离开。
2．权利要求1的射频识别标签，第一天线单元包括第一耦合区而第二天线单元包括第二耦合区，并且该缝隙将第一耦合区和第二耦合区隔离开。
3．权利要求2的射频识别标签，第一耦合区和第二耦合区被设计成与射频识别标签电路芯片耦合。
4．权利要求1的射频识别标签，该缝隙相对基片基准形成。
5．权利要求1的射频识别标签，该天线是印刷在基片表面上的导电图形。
6．权利要求1的射频识别标签，一种导电黏合剂将射频识别标签电路芯片耦合到该天线上。
7．一种用于射频识别标签的天线，包括：
一印刷在基片表面上的导电图形，和一形成在基片上的缝隙，将导电图形隔离成为第一天线单元和第二天线单元。
8．权利要求7的天线，第一天线单元包括第一耦合区而第二天线单元包括第二耦合区，第一耦合区和第二耦合区由缝隙限定。
9．权利要求7的天线，该天线形成物品、包装、包装容器、信封、证件、运货单、标签和认证证章之一的一部分。
10．权利要求7的天线，该缝隙相对基片基准形成。
11．一种制造射频识别标签的方法，该方法包括以下各步骤：
提供具有表面的基片；
在该表面上印刷导电图形；
在该基片上相对基片基准形成缝隙，该缝隙将导电图形隔离成为第一天线单元和第二天线单元；和
将射频识别标签电路芯片电连接到第一天线单元和第二天线单元。
12．权利要求11的方法，其中印刷导电图形的步骤包括印刷由第一耦合区和第二耦合区连接的第一天线单元和第二天线单元，并且形成缝隙的步骤，包括形成将第一耦合区和第二耦合区隔离开的缝隙。
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CN100361150C (zh) * 2005-06-24 2008-01-09 清华大学 带有硅基集成天线的射频识别标卡
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CN102272780B (zh) * 2008-11-25 2016-11-30 艾利丹尼森公司 制造rfid设备的方法
CN102272780A (zh) * 2008-11-25 2011-12-07 艾利丹尼森公司 制造rfid设备的方法
CN101882235B (zh) * 2010-06-28 2012-08-22 武汉华工赛百数据系统有限公司 一种缝隙耦合的激光全息电子标签及其制作方法
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CN113516220A (zh) * 2014-06-04 2021-10-19 艾利丹尼森零售信息服务公司 并入无线通信装置的货物标签
CN109546299A (zh) * 2017-09-21 2019-03-29 英飞凌科技股份有限公司 增益天线、芯片卡、天线结构及其制造方法和装置
CN110739535A (zh) * 2018-07-18 2020-01-31 英飞凌科技股份有限公司 调整天线的方法和设备、载体结构及其制造方法和芯片卡
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CN111478018B (zh) * 2020-04-15 2021-04-20 合肥工业大学 一种应用于密集环境下的射频识别标签天线

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CA2334832A1 (en) 1999-12-29
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MXPA00012438A (es) 2002-06-04
KR20010053113A (ko) 2001-06-25
AU750290B2 (en) 2002-07-11
WO1999067754A1 (en) 1999-12-29
DE69934007D1 (de) 2006-12-28
US6018299A (en) 2000-01-25
BRPI9911407B1 (pt) 2016-11-16
JP2002519771A (ja) 2002-07-02
EP1090379B1 (en) 2006-11-15
BR9911407A (pt) 2001-03-13
EP1090379A4 (en) 2004-08-04
EP1090379A1 (en) 2001-04-11
AU4573099A (en) 2000-01-10
ES2275345T3 (es) 2007-06-01
ATE345556T1 (de) 2006-12-15

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