CN1316602C - 形成半导体器件的位线的方法 - Google Patents
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Abstract
本发明公开一种形成半导体器件的位线的方法。在用于形成一半导体器件的动态随机存取存储器中的位线的线图案化工艺中,通过化学气相沉积方法,在包含接触孔的层间绝缘膜中相继形成一阻挡金属层及一钨层,以填满该接触孔。接着,去除该阻挡金属层及该钨层直到暴露出该层间绝缘膜以形成一位线接触插塞,对该层间绝缘膜及该位线接触插塞的上表面执行一溅射蚀刻工艺,并且通过物理气相沉积方法,在该暴露的层间绝缘膜及位线接触插塞上重新形成一薄厚度的钨层。结果,使位线区的缩小量如同从该层间绝缘膜的上部去除的该阻挡金属层的量,从而具有低位线电容。
Description
技术领域
本发明关于一种形成半导体器件的位线的方法,具体而言,关于一种形成具有低位线电容的半导体器件的位线的方法。在用于形成一半导体器件的DRAM(Dynamic Random Access Memory;动态随机存取存储器)中的位线的线图案化工艺中,会藉由CVD(Chemical Vapor Deposition;化学气相沉积)方法,在一包含一接触孔的层间绝缘膜中相继形成一阻挡金属层及一钨层以填充该接触孔。接着,去除该阻挡金属层及该钨层直到暴露出该层间绝缘膜,并且藉由PVD(physical Vapor Deposition;物理气相沉积)方法,在该暴露的层间绝缘膜上重新形成一薄厚度的钨层。结果,使位线区减小如从该层间绝缘膜的上部去除的该阻挡金属层那样多,从而具有低位线电容。
背景技术
由于半导体器件的高度集成且高容量,DRAM器件的容量随充电位和放电位数目的增加而增加。然而,半导体器件的单元尺寸减小,并且难以获得器件运行所需的足够电容。电容C与介电常数ε和存储电极表面面积A成正比,并且与介电膜厚度d成反比,如下面的等式1所示。
[等式1]
如果器件的电容未得到保证,则用于形成单元阵列的各种布线的耦合电容增加,并且后续一感应放大器的感应限度减小。因此,通过使用增加单元电容Cs或减少位线电容Cb的方法来保证电容。
然而,为了使用增加单元电容的方法,则会使用具有大介电常数的介电材料,或形成一厚的罩氧化物膜(cap oxide film)。结果,位线的布线由低电阻的钨和TiN所形成,以减小位线的电容。然而,由于难以使用如上文所述的方法来减小位线电容,因而已在研究解决之道。
图1a到图1d是说明用于形成半导体的位线的传统方法的截面图。
参阅图1a,在包含器件隔离膜2的半导体衬底1上,相继形成一多晶硅层(未示出)、一用于栅极电极的导电层(未示出)、以及一硬掩模氮化物膜(未示出)。
对该硬掩模氮化物膜(未示出)、用于栅极电极的该导电层(未示出)、以及该多晶硅层(未示出)执行一选择性蚀刻工艺。在一多晶硅图案3、一用于栅极电极的导电层4以及一硬掩模氮化物膜图案5相继堆叠处,形成一栅极线6。
如图1b所示,在包含图1a的该栅极线6的该半导体衬底6上形成一层间绝缘膜(未示出)。接着,执行选择性蚀刻工艺,直到该硬掩模氮化物膜图案5的上表面(upper surface)及该半导体衬底1,从而形成一具有单元区的位线接触孔10及一周边电路区的位线接触孔12的层间绝缘膜图案8。
如图1c所示,在图1b的包含位线接触孔10和12的该半导体衬底上,相继形成一使用Ti/TiN的阻挡金属层14及一CVD钨层16。
该阻挡金属层14的厚度为100至200埃,而该CVD钨层的厚度小于1000埃。
经由曝光及显影工艺,在图1c的该CVD钨层16的上表面上形成一光致抗蚀剂图案18。接着,如图1d所示,使用该光致抗蚀剂图案18当做一蚀刻掩模来蚀刻该CVD钨层,从而形成一CVD钨图案16-1。
然而,由于在该层间绝缘膜的上表面上以小厚度堆叠阻挡金属层(当做位线的导体)及该CVD钨层,因此位线面积变得更大,并且后续电容器形成过程中电容变得更高,从而减小后续DRAM运作的感应限度。
发明内容
本发明的目的是提供一种形成半导体器件的位线的方法,该方法可实现低位线电容,其方式为:在去除一形成在一层间绝缘膜上的阻挡金属层后重新形成一薄钨层,藉此缩小一位线的面积。
在一具体实施例中,提供一种形成半导体器件的位线的方法,包括步骤:
在一包含一器件隔离膜的半导体衬底上形成一栅极电极;
在包含该栅极电极的该半导体衬底上形成一层间绝缘膜;
选择性蚀刻该层间绝缘膜,藉此形成一暴露该栅极电极上表面及该半导体衬底一部分的位线接触孔;
在包含该位线接触孔的该层间绝缘膜上形成一阻挡金属层;
形成一CVD钨层以填充该阻挡金属层上的该位线接触孔;
抛光该CVD钨层及该阻挡金属层,直到暴露该层间绝缘膜以形成一位线接触插塞;
对该层间绝缘膜及该位线接触插塞的上表面执行一溅射蚀刻工艺;
在该层间绝缘膜上及该位线接触插塞的上表面上形成一PVD钨层;
选择性蚀刻该PVD钨层以形成一钨位线。
如上所述,在形成一位线的传统方法中,在一层间绝缘膜上厚堆叠一阻挡金属层及一CVD钨层。然而,在本发明一具体实施例中,去除了一形成在一层间绝缘膜上的阻挡金属层,并且在所得结构上重新形成一薄PVD钨层。结果,位线接触插塞具有缩小的面积,藉此实现低位线电容,并且增加后续DRAM运行中的感应限度。
附图说明
图1a到图1d是说明形成位线的传统方法的截面图;
图2a到图2e是说明根据本发明一实施例的形成位线的方法的截面图;
图2f是说明根据本发明一实施例形成的位线的刷新操作的图表;
图2g是说明根据本发明一实施例形成的位线的电容的图表。
附图标记说明
1、21半导体衬底
2、22器件隔离膜
3、23多晶硅图案
4、24用于栅极电极的导电层图案
5、25硬掩模氮化物膜图样
6、26栅极线
8、28层间绝缘膜图案
10、12、30、32位线接触
14、34阻挡金属层
16、36CVD钨层
16-1CVD钨图案
18、38光致抗蚀剂图案
37PVD钨层
具体实施方式
下文中,将参考附图来详细说明本发明。
图2a到图2e是说明根据本发明一实施例的形成位线的方法的截面图。
请参阅图2a,在包含器件隔离膜22的半导体衬底21上,相继形成一多晶硅层(未示出)、一用于栅极电极的导电层(未示出)、以及一硬掩模氮化物膜(未示出)。
对该硬掩模氮化物膜(未示出)、用于栅极电极的该导电层(未示出)、以及该多晶硅层(未示出)执行一选择性蚀刻工艺。于是,形成一栅极线26,在该栅极线处,一多晶硅图案23、一用于栅极电极的导电图案24、以及一硬掩模氮化物膜图案25相继堆叠。
如图2b所示,在图2a的包含该栅极线26的该半导体衬底上形成一层间绝缘膜(未示出),然后执行选择性蚀刻工艺,直到暴露该硬掩模氮化物膜图案25的上表面及该半导体衬底21的一部分。结果,形成一包括单元区(cellregion)的位线接触孔20和周边电路区的位线接触孔30的层间绝缘膜图案28。
此处,该层间绝缘膜的厚度在1000到2000埃范围内。
如图2c所示,在包含图2b的位线接触孔30和32的该半导体衬底上,相继形成一阻挡金属层(barrier metal layer)34及一填满该位线接触插塞的CVD钨层36,从而填满该些位线接触孔。
此处,优选地使用Ti/TiN形成厚度为100至200埃的阻挡金属层。该CVD钨层的厚度在2000到3000埃范围内。
对图2c的该CVD钨层36及该阻挡金属层34执行抛光工艺,直到暴露该层间绝缘膜28。如图2d所示,去除该阻挡金属层和该钨层、以及该层间绝缘膜的上部(upper portion)。
该抛光工艺包括使用SF6(sulphur hexafluoride;六氟化硫磺)、Cl2及BCl3的回蚀刻工艺(etch-back process)。在该蚀刻工艺中,可同时去除该阻挡金属层及该CVD钨层,直到暴露该层间绝缘膜。否则,在蚀刻该CVD钨层直到暴露该阻挡金属层后,可经由使用惯用金属浆料的后续抛光工艺来去除该阻挡金属层,直到暴露该层间绝缘膜。
参阅图2e,优选地对该层间绝缘膜图案28及该位线接触孔的上表面执行一溅射蚀刻工艺,以在去除该阻挡金属层及该CVD钨层的工艺中去除Ti/TiN残余物。
之后,一PVD钨层(未示出)的厚度在500到700埃范围内。
此处,优选地通过使用PVD方法来形成该钨层,因为藉由CVD方法形成的钨层不均匀地形成在属于氧化物膜的层间绝缘膜的上表面上。
在去除该CVD钨层36及该阻挡金属层34后,在2小时内形成该PVD钨层,以防止因工艺延迟导致的污染增加接触电阻。
之后,在该PVD钨层(未示出)上形成一光致抗蚀剂图案38,并且使用该光致抗蚀剂图案38当作蚀刻掩模,通过蚀刻该PVD钨层(未示出)来形成PVD钨层图案37。
如图2f所示,通过根据本发明一实施例的如上所述的方法所形成的该位线将暂停刷新从234ms(毫秒)改良至283ms,并且将YMC(Y-March行)刷新从297ms(毫秒)改良至374ms。也就是说,刷新特性改良至30ms。
如图2g所示,传统的位线电容为85fF/256单元(cell),而本发明揭示的位线电容为70fF/256单元,从而Rs改良了15%,并且感应限度改良了30mV。
本发明揭示的形成半导体器件的位线的方法可用于储存节点接触形成方法中的线型SAC(self-alignment contact;自对准接触)工艺及孔型SAC工艺。
如上所述,在本发明一实施例中,在层间绝缘膜的上部形成一薄厚度的金属沉积层,从而缩小位线面积及电极电容,改良后续DRAM工作的感应限度(sensing margin)。
Claims (6)
1.一种形成半导体器件的位线的方法,包括步骤:
在一包括器件隔离膜的半导体衬底上形成一栅极电极;
在包括该栅极电极的该半导体衬底上形成一层间绝缘膜;
选择性蚀刻该层间绝缘膜,形成暴露该栅极电极上表面及该半导体衬底的一部分的位线接触孔;
在包括该位线接触孔的该层间绝缘膜上形成一阻挡金属层;
在该阻挡金属层上形成填满该位线接触孔的CVD钨层;
抛光该CVD钨层及该阻挡金属层,直到暴露该层间绝缘膜以形成一位线接触插塞;
对该层间绝缘膜及该位线接触插塞的上表面执行一溅射蚀刻工艺;
在该层间绝缘膜及该位线接触插塞的上表面上形成一PVD钨层;
选择性蚀刻该PVD钨层以形成一钨位线。
2.如权利要求1的方法,其中该PVD钨层的厚度在500到700埃范围内。
3.如权利要求1的方法,其中该阻挡金属层包括Ti/TiN。
4.如权利要求1的方法,其中该阻挡金属层的厚度在100到200埃范围内。
5.如权利要求1的方法,其中该CVD钨层的厚度在2000到3000埃范围内。
6.如权利要求1的方法,其中抛光该CVD钨层及该阻挡金属层的步骤包括使用六氟化硫磺的回蚀刻工艺。
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2003
- 2003-12-23 KR KR1020030095303A patent/KR100557626B1/ko not_active IP Right Cessation
-
2004
- 2004-06-24 TW TW093118340A patent/TWI239074B/zh not_active IP Right Cessation
- 2004-06-28 CN CNB2004100620551A patent/CN1316602C/zh not_active Expired - Fee Related
- 2004-06-30 JP JP2004193068A patent/JP2005183918A/ja active Pending
- 2004-06-30 US US10/879,299 patent/US7101783B2/en not_active Expired - Fee Related
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US20020173129A1 (en) * | 2001-05-18 | 2002-11-21 | Ju-Cheol Shin | Metal interconnection with low resistance in a semiconductor device and a method of forming the same |
Also Published As
Publication number | Publication date |
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US20050136594A1 (en) | 2005-06-23 |
US7101783B2 (en) | 2006-09-05 |
KR100557626B1 (ko) | 2006-03-10 |
CN1638098A (zh) | 2005-07-13 |
TWI239074B (en) | 2005-09-01 |
TW200522272A (en) | 2005-07-01 |
JP2005183918A (ja) | 2005-07-07 |
KR20050064034A (ko) | 2005-06-29 |
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